ECE 450:DIGITAL SIGNAL
PROCESSORS AND APPLICATIONS
Lecture 12:
Computational Building Blocks of DSP
Amrita School of Engineering, Bangalore
Last Session
• DSP Architectures
– General architectures
• Architectural aspects
– H/W and S/W aspects
– RISC, CISC
– Endianess
07/ 02/ 14
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Amrita School of Engineering, Bangalore
Today’s Session
• DSP Computational building blocks
– Multiplier
– Shifter
– Barrel Shifter
07/ 02/ 14
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Amrita School of Engineering, Bangalore
Computational building blocks
• DSP computational building blocks
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Multiplier
Shifter
MAC Unit
ALU
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Amrita School of Engineering, Bangalore
Multiplier
• Single chip multiplier
• Multiplication of 2 binary numbers
implemented in single processor cycle
• Parallel multiplier
– Consider multiplication of two 4-Bit unsigned
numbers A and B
– Each bit of product is obtained by summation using
an array of single bit adders
– A 4 x 4 braun multiplier requires 12, 3 input, 2
output adders.
– For an n x n multiplier number of adders is n(n-1)
07/ 02/ 14
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Amrita School of Engineering, Bangalore
Multiplier Cont..
• Speed:
– The shift & add technique requires n cycles for nxn
multiply
• The parallel multiplier is a fully combinational
implementation & once the operands are
available the multiply time is the longest path
delay time through the gates & adders
– It is desirable to have multiplication time
comparable to processing time of other
computational units & access time of memories.
– High speed multiplier is achieved through fully
parallel implementation
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© Dr.Shikha Tripathi,ASE, Bangalore
Amrita School of Engineering, Bangalore
Multiplier Cont..
• Bus Width:
– Consider Z = X .Y. If X & Y are n bit wide Z can
have maximum 2n bits. In single cycle
implementation we require 3 buses, which is quite
expensive
– As an alternative, program bus can be used to carry
one of the operands (say X) after multiplication
instruction is fetched from prog. Memory
– Separate bus for Z can be avoided as one of the
buses (say X) can be used to transfer Z as X would
have been latched before Z is made available.
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Amrita School of Engineering, Bangalore
• To handle 2n bits of Z there are 2 alternatives:
a. Use X (n bits) & save Z at 2 successive locations
using 2 memory accesses
b. Discard lower n bits of Z & save only higher n bits
(most often used)
– If Z is to be further processed, all 2n bits are
retained & passed to next stage to retain accuracy
of the product. The lower n bits are discarded after
all operations are done
– For applications where speed is not an issue buffers
& latches may be provided at input & output
07/ 02/ 14
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Amrita School of Engineering, Bangalore
Shifter
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Required to scale down or scale up operands
& results to avoid errors resulting from
overflows and underflows during
computations
(a) When N number of n bits are added, the
number of required bits increases to
(n+log2N) bits
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07/ 02/ 14
Loss due to overflow can be avoided by scaling
down each number by log2N
Results in decrease in accuracy but loss due to
overflow can be avoided
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Amrita School of Engineering, Bangalore
Shifter Cont..
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The actual sum can be obtained by scaling up the
result by log2N bits
(b) When 2 numbers represented by n bits are
multiplied the product can have maximum 2n
bits. Discarding lower n bits results is loss of
accuracy. In multiplying 2 signed numbers
accuracy is slightly increased by shifting the
product by 1 bit to left before storing higher
order bits.
(c) While carrying out floating point additions,
the operands should be normalized to have
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07/ 02/ 14 same exponent.
© Dr.Shikha
Tripathi,ASE, Bangalore
Shifting
is required.
Amrita School of Engineering, Bangalore
Barrel Shifter
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07/ 02/ 14
In DSPs multibit shifts are common
Shifts by multibit is possible in one cycle using a
combinational circuit called Barrel shifter
It connects the input lines representing a word to a
group of output lines with required shift determined
by its control inputs. Control unit also determines
the direction of shift
For input word of n bits, 0 – (n-1) bit shifts require
log2n control lines
Bits shifted out in the left shift are filled with zeros
in LSB & new bit positions are filled with MSB to
retain the sign in case of right shift
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© Dr.Shikha Tripathi,ASE, Bangalore
Amrita School of Engineering, Bangalore
Next Session
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Barrel Shifter
MAC
ALU
Architecture of TMS 320C54x Processor
07/ 02/ 14
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12
Amrita School of Engineering, Bangalore
Thank You
07/ 02/ 14
© Dr.Shikha Tripathi,ASE, Bangalore
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