UNIVERSITI MALAYSIA PERLIS
Mid-Term Examinations
Academic Session 2011/2012
April 2012
EKT222 – Microprocessor System
[Sistem Mikropemproses]
Duration : 1 ½ hours
I AM NUMBER FOUR
Name: ___________________________________________
ID: ___________________________________________
Program: ___________________________________________
Part A (10 Marks)
Answer ALL questions.
Determine whether each statement about 8085 microprocessor below is true (T) or false (F).
It can address up to 64K of memory locations.
T
Opcode fetch machine cycle requires only 4 processor states to complete.
F
Program counter will be reset to 0000H after hardware reset (power up).
T
Active signal on the READY (RDY) pin causes it go into hold state.
F
XCHG instruction will exchange the contents of register pair HL with register SP.
F
IO/M signal will be at logic low during memory read machine cycle.
T
ALE signal is generated during T2 state for each machine cycle.
F
INX and DCX instructions do not affect any of flag after execution.
T
Using a 4 MHz crystal, the memory write machine cycle is 1.5 us.
T
The I/O Map contains 1024 addresses.
F
[10 Marks]
Part B (30 Marks)
Answer ALL questions.
1. List the 5 common types of machine cycle for an 8085 microprocessor. Provide the number of states
required by each machine cycle listed.
[5 marks]
- opcode fetch (4 states)
- memory write (3 states)
- memory read (3 states)
- i/o write (3 states)
- i/o read (3 states)
2/7
2. Sketch the circuit that can be used to de-multiplex the signal AD0 - AD7 of 8085 microprocessor. Label
all required signals accordingly.
[5 marks]
D0-D7
AD0-AD7
Latch
A0-A7
ALE
3. Explain how stack memory is implemented in 8085 microprocessor. State 2 instructions in 8085 that
uses basic stack operation implicitly (not directly requested, used by underlying hardware).
[5 marks]
- stack operations: POP and PUSH
- in 8085 managed by stack pointer (system register)
- ALWAYS 2-bytes operation
PUSH: decrement stack pointer and place UPPER byte, then
decrement stack pointer again and place LOWER byte
POP: get LOWER byte and increment stack pointer, then get
UPPER byte and increment stack pointer again
- 2 instructions: CALL (PUSH) and RET (POP)
4. Discuss the difference between STA and STAX instructions. Write a code to clear (put 00H to) 50
memory locations starting from 2010H.
[5 marks]
- sta requires fixed parameter (absolute address)
- stax uses a register pair to obtain the address (pointer)
lxi d,2010h
mvi a, 00h
mov b,50
loop:
stax d
inx d
dcr b
jnz loop
OR the long way!
3/7
5. For the following code, figure out the content of the SP register and stack memory (show addresses of
the stack) after ALL instructions have been executed.
LXI SP, 4000H
XRA A
PUSH PSW
ANI 0FFH
PUSH PSW
[5 marks]
- SP: 3FFCH
- stack memory:
[3fffh] 00h
[3ffeh] 44h
[3ffdh] 00h
[3ffch] 54h
6. For the following program, what is the content of the registers B, C, D, E, H, L, A and flag after ALL
instructions have been executed? Assume initial contents BC=1010H, DE=8F2EH, HL=9549H and
A=8CH.
LXI SP, 4000H
XRA A
PUSH B
PUSH PSW
PUSH H
INR A
POP D
POP B
POP H
XRA A
[5 marks]
-
B:
D:
H:
A:
00h,
95h,
10h,
00h,
C:
E:
L:
F:
44h
49h
10h
44h
4/7
Part C (60 Marks)
Answer ALL questions.
1. Construct a timing diagram that shows the execution of 8085 instruction LDA 2010H. Show all machine
cycles involved. Also show the number of T-States, the contents of data bus and the contents of
address bus for each machine cycle. Assume the instruction is at location 0210H, and the data at
location 2010H is 5AH.
[15 marks]
INSTRUCTION
LDA 2010H
MACHINE CYCLE
T-STATES
OF
MR
T1 T2 T3 T4 T1
T2
MR
T3
T1
T2
MR
T3
T1
T2
DATA BUS
3AH
10H
20H
5AH
ADDRESS BUS
0210H
0211H
0212H
2010H
T3
OR... THE MORE DETAILED TIMING (WITH MULTIPLEXED ADDR/DATA) – NOTICE THAT THE
QUESTION DID NOT EVEN REQUEST FOR ALE, IO/M, S1, S0!
2. Construct a simple state machine diagram for the execution of 8085 microprocessor instructions.
Include only the main states. The RESET, HOLD, WAIT and HALT states can be ignored. Provide brief
information of each states (if applicable).
[15 marks]
T1
T2
T3
T1 – ALE generated, status pins updated
T2 – RD/WR asserted
T3 – RD/WR deasserted
T4 – only if an OF
T5 – bridge to T6
T6 – special OF
T4
T5
T6
5/7
3. A sub-routine for an 8085 microprocessor in assembly language is shown below.
START:
CHKCR:
PUT_NULL:
NEXT:
STOP:
DATA:
RESULT:
ORG 0400H
LXI H, DATA
MVI D, 0DH
MVI E, 0AH
MVI B, 0
MOV A, M
CPI 0
JZ STOP
CMP D
JZ PUT_NULL
CMP E
JZ PUT_NULL
INR B
JMP NEXT
MVI A, 00H
MOV M, A
INX H
JMP CHKCR
MOV A, B
STA RESULT
RET
ORG 2000H
DFB
0FFH, 41H, 42H, 43H, 44H, 45H, 0DH, 0AH, 00H
DFS
1
a. Translate the program into machine codes manually.
[20 marks]
[0400]
[0403]
[0405]
[0407]
[0409]
[040A]
[040C]
[040F]
[0410]
[0413]
[0414]
[0417]
[0418]
[041B]
[041D]
[041E]
[041F]
[0422]
[0423]
[0426]
START
CHKCR
PUT_NULL
NEXT
STOP
LXI H,DATA
MVI D,0DH
MVI E,0AH
MVI B,0
MOV A,M
CPI 0
JZ STOP
CMP D
JZ PUT_NULL
CMP E
JZ PUT_NULL
INR B
JMP NEXT
MVI A,00H
MOV M,A
INX H
JMP CHKCR
MOV A,B
STA RESULT
RET
21
16
1E
06
7E
FE
CA
BA
CA
BB
CA
04
C3
3E
77
23
C3
78
32
C9
00 20
0D
0A
00
00
22 04
1B 04
1B 04
1E 04
00
09 04
09 20
(10)
(7)
(7)
(7)
(7)
(7)
(7/10)
(4)
(7/10)
(4)
(7/10)
(4)
(10)
(7)
(7)
(6)
(10)
(4)
(13)
(10)
6/7
b. How much time is required to execute the routine if the 8085 microprocessor is driven by a 4 MHz
crystal?
[5 marks]
Total States: NS
+ 6(73)
+ 1(65)
+ 1(76)
+ 1(24)
+ 27 //
= 661
= 31 // before CHKCR
// 438 - full path
// 65 - path for 0D
// 76 - path for 0A
// 24 - path for 00
STOP till end
Total time: Texec = NS x TS = NS x 1/fs = NS x 2/fcrystal
= 661 x 0.5 us = 330.5 us
c. Describe in words what value will storage RESULT holds. Give the address of that storage and its
content AFTER the code is executed.
[5 marks]
It will hold the length of the given character array EXCLUDING
newline characters.
RESULT @[2009H]: 06H
- THE END -
7/7