Power supply and substrate noise analysis;
Reference tool experience with
silicon validation
Yoji Bando*1*4, Daisuke Kosaka*4,
Goichi Yokomizo*2, Kunihiko Tsuboi*2,
Ying Shiun Li*3, Shen Lin*3, Makoto Nagata*1*4
Kobe University*1, STARC*2,
Apache Design Solutions, Inc.*3, A-R-Tec Corp.*4
DAC2009-UT#8.2 -2-
Motivation
Power supply (PS) noise impacts on circuits
- digital: timing variation, leakage increase
- analog-MS: substrate crosstalk, substrate coupling
Digital PS integrity technology, with enhancements
of substrate coupling/noise analysis
On-chip measurements connect EDA analysis
with reality
DAC2009-UT#8.2 -3-
Technical contribution
Multi-party collaboration for validated noise analysis
Chip designer, IP provider, EDA tool provider
Fully integrated power and substrate noise analysis
A high capacity solver for a single large matrix unifying
on-chip power grids and current sources, chip-level
substrate meshes, and off-chip board networks
On-chip noise measurements for silicon correlation
Noise monitors with very many probing channels for
thorough correlation of simulation and measurements
Multi-party collaboration for
confidence noise analysis
DAC2009-UT#8.2 -4-
Power library: Logic
cell characterization
Dynamic and static
PS noise analysis
Integrity design tool developer
(cf. Apache Design Solutions)
Substrate network
and noise analysis
Verification planning
and test chip design
On-chip noise meas.
and correlation
Physical design and
sign-off flow
Integrity design consultant
(cf. A-R-Tec)
User company
(cf. IDM, design house)
DAC2009-UT#8.2 -5-
Key technology contributions #1
Power library: Logic
cell characterization
Dynamic and static
PS noise analysis
Substrate network
and noise analysis
Verification planning
and test chip design
On-chip noise meas.
and correlation
Physical design and
sign-off flow
PSA and SNA
DAC2009-UT#8.2 -6-
Key technology contributions #2
Power library: Logic
cell characterization
Integrated PS and
substrate noise
simulation
Verification planning
and test chip design
On-chip noise
measurements
Physical design and
sign-off flow
Simulation and
Silicon correlation
Noise evaluation chip overview
Substrate noise
probe array
in left top area
PS noise
probe array
for 32-bit µP
DAC2009-UT#8.2 -7-
5.0 mm
SRAM
macros
32-bit µP
core
Substrate noise
probe array
in right btm. area
A 32-bit processor (SH-4*) with 210 kB memory capacity
Densely distributed on-chip dynamic noise monitors
90-nm CMOS, 5LM, 1.0 V technology
SH-4* Renesas technology
DAC2009-UT#8.2 -8-
Noise probing locations in µP core
2.5 mm
32-bit uP
core
2.0 mm
DAC2009-UT#8.2 -9-
Noise probing locations on substrate
Substrate noise evaluation area
(120 probing points in total)
P+ GR
(guard ring)
deep Nwell deep Nwell
pocket
GR
1.6 mm
0.5 mm
P+ probing points
PS noise
probing array
On-chip noise monitor circuitry
Vdd
Digital Gnd
n-SF
Iout
p-SF
DAC2009-UT#8.2 -10-
Vout
Substrate (P+) noise
probing array
psub
p-SF
p-SF
Vout
n-Gm
On-chip
Off-chip
DAC2009-UT#8.2 -11-
PS noise waveform measurements
Probing @SH-4 center, Fclk = 50 MHz
Voltage (V)
Voltage (V)
1.00
0.98
0.96
0.94
Vdd
0.02 Gnd
0.01
0.00
-0.01
-0.02
200 nsec
DAC2009-UT#8.2 -12-
V (mV)
0
# test code with higher level of internal logic activity
20
Voltage
PS noise intensity: code dependence
Vnominal
Static
drop
Dynamic Vpp
40
60
40
30
20
10
0
Dynamic Vpp
#40
#39
#38
#37
#36
#35
#34
#33
#32
#31
#30
#29
#28
#27
#26
#25
#24
#23
#22
#21
#20
#19
#18
#17
#16
#15
#14
#13
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
80
uP Vdd Static drop
uP Gnd Static drop
Dynamic Vpp
DAC2009-UT#8.2 -13-
Unified matrix of chip-level noise analysis
PS current
sources
Off-chip networks
Vdd/Gnd grids
Vertical
impurity
profile
Silicon substrate model
Resistive as well as capacitive
elements involved
(e.g. pwell, nwell, deep well)
DAC2009-UT#8.2 -14-
Full chip PS and substrate noise analysis:
flow overview
Pkg Model
SoC Layout
Cell Library
RLC or S-Para
LEF/DEF
.lib, spice
RedHaw k-EV
Substrate Model
Macro Geometry
Macro Netlist
Technology
GDSII
spice netlist
file
Digital
Totem _SE
Ex traction, Sim ulation
Debugging, W hat-if and FAO
DAC2009-UT#8.2 -15-
Noise source modeling
well network
Standard cell library (LEF/DEF)
Vdd wiring
Cwell
Apache Power Library (APL)
- SPICE simulation: I(t)
LUT for in/out condition, load caps
- Post-layout extraction
logic cell level: Cesc, Resr
I(t)
Resr
Cpg
Cesc
Vss wiring
Substrate network modeling
DAC2009-UT#8.2 -16-
Noise Sources
•DGnd
•DGnd
n+ n+
n+ n+
p+
•DVdd
p+ p+ n+ p+ p+ n+
p-well
p+
Pwell RES
n-well
(in deepNwell)
Deep
n-well
•DVdd
p-well
Nwell RES
n-well
Pwell_CAP
(in deepNwell)
Pwell_CAP
(in deepNwell)
Pwell_CAP
deepNwell RES
Psub CAP
Bulk RES
Psub CAP
p-sub
DAC2009-UT#8.2 -17-
Off-chip network modeling
L
C
Off-chip power delivery network (PDN)
- FR4 board, package, bonding wires – macroscopically seen by a chip
- Lumped LCR extraction between Vdd and Gnd terminals
- Considerable impacts on noise components from DC to a few 100 MHz
DAC2009-UT#8.2 -18-
Unified matrix for quality noise analysis
Vgnd-pp (mV)
80
75
70
Substrate coupling analysis enhances
accuracy of noise analysis in digital as
well as mixed-signal circuits.
w/o off-chip model
w/o substrate model
65
60
only w/ off-chip
model
55
w/ off-chip and
substrate models
50 meas.
45
0
2 4 6
Probe point
1 SH-4
2 core
3
4
5
Ground noise in SH-4 processor @ 50 MHz,
comparing simulation with on-chip measurements
DAC2009-UT#8.2 -19-
Dynamic PS noise waveforms
(V) Vdd noise @ Fck = 50 MHz
1.00
0.98
0.96
0.94
0.92
0.90
0
20
40
(V) Gnd noise @ Fck = 50 MHz
0.08
0.06
0.04
0.02
0.00
-0.02 0
20
40
60
80
Measured
100
Simulated
(ns)
60
80
100
(ns)
DAC2009-UT#8.2 -20-
Gnd/Psub noise: chip-wide Vpp map
Simulated drop of uP Gnd/Psub
@ Fck = 50 MHz
y(µm)
Measured, left top
1000
30
900
20
800
10
700
0
600
500
yL
xU
-500
xL
-700
yR
(mV)
40
-1600 -1400 -1200 -1000 -800 -600 -400 -200 x(µm)
Measured, right bottom
(mV)
30
-600
-800
20
-900
10
-1000
y(µm)
0
-200 -400 -600 -800 -1000 -1200 -1400 -1600 x(µm)
0
DAC2009-UT#8.2 -21-
Substrate noise (Vpp) trend: yL axis
Vpp (mV)
60
xU
xL
yL
yR
Fck = 50 MHz
40
20
y-left (yL)
meas.
sim.
0
Distance -2.0
(mm)
-1.0
uP Gnd
0.0
1.0
Psub
DAC2009-UT#8.2 -22-
Substrate noise (Vpp) trend: xL axis
Fck = 50 MHz
Vpp (mV)
60
xU
xL
yL
yR
40
x-lower (xL)
meas.
sim.
20
0
Distance -1.0 0.0
(mm)
uP Gnd
1.0
Psub
2.0
DAC2009-UT#8.2 -23-
Cost of Simulation
Chip to simulate
Mesh size
CPU time
Memory usage
Machine spec.
SH-4 core: 670k gates, SRAM cells: 11.2M trs.,
# of I/O: 208 pins, chip area: 5.0 mm x 5.0 mm
750 k
extraction 1.0 h, simulation 1.5 h (for 120 nsec)
extraction 6.6 GB, simulation 3.5 GB
2-core Opteron x 2 @ 2.8GHz, 64 GB memory
DAC2009-UT#8.2 -24-
Summary
Unification of on-chip power grids, substrate, and
off-chip network realizes dynamic PS and substrate
noise simulation with high accuracy
Comprehensive on-chip noise measurements
establish reference experience of silicon validation
Close correlation of simulation and measurements
achieves designers’ confidence of noise analysis