ECE 5070 Microelectronics Fabrication Technology
Process specifications
Process specifications
Temperature, pressure, time,
RF power, gas flow rates, etc.
Thickness, dielectric constant,
stress, charge, etc.
Device specifications
Breakdown voltage, leakage current,
threshold voltage, gain, etc.
1. Constraints by device specifications.
Examples:
(a) MOS: Threshold voltage constrains oxide thickness.
(b) Bipolar: gain constrains base-width.
(c) Interconnect: RC delay constrains resistivity.
2. Constraints by process compatibility.
Examples:
(a) Presence of Al constrains process temperature.
(b) Etch selectivity constrains choice of materials.
ECE 5070 Microelectronics Fabrication Technology
Process integration
Microsystems
Microelectronic
devices
Micromechanical
devices
Film Formation
Photolithography
Etching
Techniques of construction
1. Process modules: construction techniques.
(a)
(b)
(c)
(d)
Film formation: reaction, PVD, CVD, spin coating, plating.
Film modification: doping, diffusion, reaction, annealing.
Photolithography: intermediate pattern transfer.
Etching: final pattern transfer, CMP.
2. Device construction: module integration.
(a) Microelectronics: NMOS, CMOS, Bipolar, BiCMOS.
(b) Micromachines: gears, resonators, etc.
(c) Microsystems: microelectronics + micromachines.
ECE 5070 Microelectronics Fabrication
Technology
Process Integration
Photolithography
Film
Formation
Photolithography
Module 1
Clean
Etch
Film
Formation
Etch
Clean
Photolithography
Etch
Photolithography
Module 2
Film
Formation
Clean
Etch
Film
Formation
Film
Formation
Unit Processes
CVD
PVD
React
Etch
Photo
Modules
Mod 1
Mod 2
Mod 4
Device
Integration:
DRAM
Device
Integration:
Microprocesser
Mod 3
Mod 5
Device
Integration:
Flash EPROM
etc …
ECE 5070 Microelectronics Fabrication Technology
Module: Traditional device isolation
1. LOCOS isolation.
Nitride: oxidation mask
Oxide: stress relief
Field oxide: isolation
Silicon: active area
Bird’s beak: lateral diffusion through stress relief oxide.
2. Poly-buffered LOCOS (PBL).
Poly-Si: stress relief buffer
Oxide: thinner than in LOCOS
Reduced bird’s beak: less diffusion through thinner stress
relief oxide.
ECE 5070 Microelectronics Fabrication Technology
Module: Shallow trench isolation (STI)
1)
2)
3)
4)
5)
6)
Mask stack formation.
STI etch.
Liner oxidation.
Gap fill with CVD oxide.
CMP.
Hard mask removal.
STI is a more scalable isolation technology than those
based on LOCOS.
ECE 5070 Microelectronics Fabrication Technology
Module: STI etch and trench fill
1) Sidewall angle control (70o to 90o).
2) Corner rounding.
CVD oxide: LPCVD furnace, APCVD TEOS/ozone, HDP
ECE 5070 Microelectronics Fabrication Technology
Module: STI CMP
ECE 5070 Microelectronics Fabrication Technology
Module: STI and narrow channel effect
ECE 5070 Microelectronics Fabrication Technology
Module: Drain engineering (I)
Shallow junction formation and RTA
1) Low energy implant.
2) Rapid thermal activation.
ECE 5070 Microelectronics Fabrication Technology
Module: Contact engineering (I)
Silicided source/drain: Ti, Co, Ni, etc.
Two-step process for TiSi2 and CoSi2, one-step for NiSi.
Silicide
TiSi2 (C49)
TiSi2 (C54)
CoSi
CoSi2
NiSi
NiSi2
Resistivity (µΩcm)
60-70
13-16
100-150
14-20
14-20
40-50
Sintering temperature(oC)
500-700
700-900
400-600
600-800
400-600
600-800
ECE 5070 Microelectronics Fabrication Technology
Module: Contact engineering (II)
Silicide Trend
TiSi2
Silicide
TiSi2
CoSi2
NiSi
=> CoSi2
Native oxide
reduction
Strong ☺
Weak Weak silicide
=> NiSi
Diffusing species
Si Co ☺
Ni ☺
Line width
sensitivity
Strong Weak ☺
Weak ☺
metal
Higher formation temperature, silicon
diffusing: more encroachment
Lower formation temperature,
metal diffusing: less encroachment
ECE 5070 Microelectronics Fabrication Technology
Module: Aluminum/copper damascene
CMP
Metal
Oxide
glue/
barrier layer
ECE 5070 Microelectronics Fabrication Technology
Module: Dual damascene
ECE 5070 Microelectronics Fabrication Technology
Module: Damascene etch issues
ECE 5070 Microelectronics Fabrication Technology
Module: Low-k dielectrics
11
10
4
10
10
9
3.5
9
9
3
8
8
2.5
7
7
2
6
6
1.5
1
300
5
250
200
150
100
Technology node (nm)
DRAM 0
50
Maximum no. of metal levels (logic)
Maximum interlevel dielectric constant
4.5
ECE 5070 Microelectronics Fabrication Technology
NMOS process: active area definition.
Silicon nitride
Stress relief oxide
Field implant (Boron)
p-type
starting substrate
Active area
Layout:
1. Film formation.
(a) Oxidation: stress relief oxide, etch stop.
(b) Silicon nitride deposition: oxidation mask.
2. Film etch.
(a) Active area photolithography. (Mask# 1)
(b) Silicon nitride dry etch: active area.
3. Film modification.
Implantation: field region Vth adjust.
ECE 5070 Microelectronics Fabrication Technology
NMOS process: LOCOS device isolation
Field oxide (FOX)
Threshold adjust/punch-through
implant
Bird’s beaks
1. Film formation.
Selective oxidation: device isolation.
2. Film etch.
(a) Silicon nitride: blanket wet etch.
→ removes oxidaton mask.
3. Film modification.
(a) Implantation: transistor Vth adjust.
→ Vth > 0 for enhancement mode.
→ Vth < 0 for depletion mode (additional mask).
(b) Implantation: punch-through prevention.
ECE 5070 Microelectronics Fabrication Technology
NMOS process: gate module
Self-aligned gate and source/drain
implant (Phosphorus/arsenic)
Polysilicon
Gate oxide
Junctions
Channel
Gate
Contact landing pad
1. Film formation.
(a) Oxidation: gate oxide.
(b) Undoped polysilicon deposition: gate.
2. Film etch.
Polysilicon etch: gate definition. (Mask# 2)
3. Film modification.
(a) Implantation: gate, source/drain doping.
(b) High temperature anneal: dopant activation.
ECE 5070 Microelectronics Fabrication Technology
NMOS process: contact and metallization.
Interlevel dielectric (ILD)
Interconnections (Al-Si-Cu)
PSG
Contacts
Contact hole
1. Film formation.
(a) Low temperature oxide (LTO) deposition:
→ Inter-level dielectric. (ILD)
2. Film etch.
LTO etch: contact holes. (Mask# 3)
3. Film formation.
Al-Si-Cu deposition: metallization.
4. Film etch.
Metal etch: interconnections. (Mask# 4)
5. Film modification.
(a) Forming gas anneal (FGA): contact sintering.
→ Reduces contact resistance.
ECE 5070 Microelectronics Fabrication Technology
NMOS process: final passivation
Contact pad
Final passivation
(PECVD nitride)
Contacts
Passivation for device protection.
1. Film formation.
PECVD silicon nitride.
2. Film etch.
PECVD nitride etch: (Mask# 5)
→ contact pads for external connections.
ECE 5070 Microelectronics Fabrication Technology
NMOS process: spacer technology
1. Lightly doped drain. (LDD)
→ Improves hot carrier reliability.
Anisotropic etch
Oxide or nitride
Spacers
Lightly doped drain
Heavily doped drain
(a) Light dose implantation.
(b) Spacer formation.
(c) High dose implantation.
2. Self-aligned (maskless) silicidation. (Salicide)
→ Reduces RC delay.
Spacers
Refractory metal
Refractory metal silicide
S/D junctions
(a) Spacer formation.
(b) Refractory metal (Ti, Ni, Co) blanket deposition.
(c) React, strip, and anneal.
ECE 5070 Microelectronics Fabrication Technology
CMOS process: well formation
1. N-well.
Phosphorus implantation
Lightly doped epitaxy
n+substrate
Silicon nitride
Silicon oxide
ν - epitaxy
n-well
(a) Nitride/oxide p-well mask. (Mask# 1)
(b) Phosphorus implant and drive-in.
2. P-well.
Boron implantation
p-well
(a) Self-alighed boron implant and drive-in.
(b) Blanket oxide etch.
ECE 5070 Microelectronics Fabrication Technology
CMOS process: threshold adjust implant
1. Well and device isolation module. (Mask# 2)
2. Transistor threshold voltage adjust.
(a) NMOS: p-well surface remains p-type.
→ Surface channel FET.
Blanket boron implantation
p-well
Well isolation
n-well
Device isolation
(b) PMOS: n-well surface slightly compensated. (Mask# 3)
→ Buried channel FET.
Boron implantation
Photoresist
p-well
n-well
ECE 5070 Microelectronics Fabrication Technology
CMOS process: source/drain doping
1. Gate module.
(a) Gate oxidation.
(b) Polysilicon deposition and doping (n-type).
(c) Gate definition. (Mask# 4)
2. Source/drain doping.
(a) PMOS: BF2 implant.
BF2 implantation
p+source/drain
p-well
n-well
(b) NMOS: P/As implant. (Mask#5)
Phosphorus/arsenic implantation
Photoresist
p-well
n+source/drain
p+source/drain
n-well
ECE 5070 Microelectronics Fabrication Technology
CMOS process: metallization and passivation
1. LTO deposition and densification.
2. Contact formation. (Mask# 6)
3. Metal deposition and definition. (Mask# 7)
Metallization
p-well
n+source/drain
p+source/drain
ILD
n-well
4. PECVD nitride deposition.
5. Pad opening. (Mask# 8)
PECVD silicon nitride
p-well
n+source/drain
p+source/drain
n-well
ECE 5070 Microelectronics Fabrication Technology
Bipolar process: buried layer and epitaxy
Sb (or As) implantation
Oxide implant mask
n-epitaxial layer
p-type substrate
n+buried layer
1. Oxidation and buried layer mask. (Mask# 1)
2. Buried layer Sb (or As) implantation.
→ reduction of collector resistance.
3. Oxidation and implant activation.
4. Oxide removal and epitaxial layer formation.
→ intrinsic collector.
ECE 5070 Microelectronics Fabrication Technology
Bipolar process: isolation formation
Boron channel stop implant
Oxide
Nitride
Recessed field isolation oxide
p+channel stop
1. Nitride/oxide double layer formation.
(a) Oxide: stress relief, etch stop.
(b) Nitride: oxidation mask.
2. Double layer etchback. (Mask# 2)
Silicon etch → recessed isolation.
3. Channel stop implant.
→ raises field threshold.
4. Field oxidation.
ECE 5070 Microelectronics Fabrication Technology
Bipolar process: Base module
Boron base implantation
p+base contact implantation
Resist
Base diffusion
p+base contact diffusion
1. Intrinsic base patterning. (Mask# 3)
2. Intrinsic base implant and activation.
→ lightly doped base.
3. Extrinsic base patterning. (Mask# 4)
4. Extrinsic base implant and activation.
→ heavily doped base.
ECE 5070 Microelectronics Fabrication Technology
Bipolar process: emitter and collector module
P/As implantation
Low temperature oxide (LTO)
n+emitter/collector
1. Emitter and collector patterning. (Mask#5)
2. Emitter and collector implantation.
→ heavily doped contact regions.
3. LTO isolation formation.
ECE 5070 Microelectronics Fabrication Technology
Bipolar process: contact and metallization.
PECVD nitride passivation
Metal interconnections
Vertical npn bipolar
transistor
1. Contact patterning and formation. (Mask# 6)
2. Interconnection formation. (Mask# 7)
3. PECVD nitride Passivation formation.
4. Pad openining. (Mask# 8)
ECE 5070 Microelectronics Fabrication Technology
BiCMOS process: basic n-well CMOS process
NMOS
PMOS
Field oxide
p epitaxy
n-well
p + substrate
1. n+: NMOS source/drain.
→ Bipolar collector contact and emitter.
2. p+: PMOS source/drain.
→ Bipolar extrinsic base contact.
3. n-well: PMOS transistor.
→ Bipolar intrinsic collector.
4. To realize bipolar transistor:
(a) Major issue: missing intrinsic p-base.
(b) Minor issue: missing n+ buried layer.
ECE 5070 Microelectronics Fabrication Technology
BiCMOS process: addition of bipolar transistor
NMOS
PMOS
p base
Field oxide
G
G
S
NPN bipolar
D
S
D
E
B
C
p epitaxy
p + substrate
p+: extrinsic base
n-well
n+: emitter & collector
1. Shallow p-type diffusion.
→ Intrinsic base for NPN bipolar transistor.
2. No n+ buried layer.
→ High collector resistance.
3. Simple process: CMOS+1.
→ Bipolar transistor not optimized.
ECE 5070 Microelectronics Fabrication Technology
BiCMOS process: n epitaxy and n+ buried layer
NMOS
PMOS
G
G
S
NPN bipolar
S
D
E
n-well
n+buried layer
n epitaxy
D
B
C
p-well
p+substrate
n+collector plug
1. Addition of n type epitaxy
(a) Optimized bipolar intrinsic collector doping.
(b) Optimized PMOS n-well doping.
2. Reduced extrinsic collector resistance.
(a) n+ buried layer.
→ Prevents p+ substrate from depleting PMOS n-well.
(b) Deep collector plug contact.
3. CMOS+3.
ECE 5070 Microelectronics Fabrication Technology
BiCMOS process: poly-emitter
NMOS
NPN bipolar
PMOS
Poly-emitter
G
S
D
p-well
p substrate
G
S
n-well
C
B
D
p buried layer
n epitaxy
1. Self-aligned NMOS p-type buried layer.
(a) Optimized p-well doping.
(b) Isolate n+ buried layers.
2. Poly-emitter: high gain bipolar transistor.
3. Complex process: CMOS+4.
→ Optimized CMOS and bipolar transistor.
ECE 5070 Microelectronics Fabrication Technology
High-κ/Metal Gate (HKMG)
1. Silicon oxynitride (SiON) ran out of steam at the 90nm node. Films could not
be made much thinner than ~1nm without excessive tunneling-induced leakage
current.
High-κ dielectric can be made thicker to reduce leakage current without
reducing capacitance.
2. High-κ dielectric must be used with a metal gate: electronic states at the
interface of polysilicon gate and high-κ dielectric cause “Fermi level pinning”,
which results in a high threshold voltage.
An added advantage of a metal gate is that polysilicon depletion is suppressed.
3. High-κ has many challenging material/process requirements. Thermal stability
is typically poor. Amorphous morphology is desired, but crystallization often
occurs at higher temperature.
a. Hafnium silicates are relatively more stable than HfO2, but κ is lower.
b. Nitrided hafnium silicates are a good compromise, and could probably be
used for the next device generation.
c. Hf-Al-O offers a wide range of κ-values.
4. HKMG requires tuning of the threshold voltage of both PMOS and NMOS
transistors. One way is through capping layers in between the high-κ and the
metal gate or between an interlevel dielectric (which sits atop the channel
region) and the high-κ material.
Al2O3 and La2O3 are example of capping layer materials.
5. Another approach to threshold voltage tuning is to select an electrode material
with the desired work function. Candidates include TaN, TiN and TaSiN.
However most metals tend to migrate towards midgap work functions after
high-temperature anneals. Consequently, it is important for the metal not to be
exposed to high temperatures, such as adopting a gate-last process strategy
(sometimes called gate replacement or “cold flow” process).
ECE 5070 Microelectronics Fabrication Technology
Gate Last HKMG
The high-κ material is deposited and dummy gates are created.
This is followed by source/drain formation and an interlevel
dielectric deposition and polish. The dummy gates are removed
and different workfuction metals are deposited for NMOS and
PMOS.
High-k first, gate-last structure.
An on-going problem with HKMG is flat-band voltage roll-off
with reducing channel length, resulting in a higher threshold
voltage for the PMOS transistor. This problem is caused by oxygen
vacancies/defects in the high-k material, which can diffuse during
the growth of the interlayer dielectric.
There are two approaches to solving this problem:
1. Since it is a thermally activated issue, going to lower or neutral
thermal budgets would help: such as spike or laser anneal.
2. The second solution is to passivate by oxygenation, either
lateral oxygenation after source/drain activation, or oxygenation
through a thin layer of TiN.
ECE 5070 Microelectronics Fabrication Technology
Cost of IC R&D and Factory
Transition to new semiconductor technologies are becoming
technologically and financially challenging. (Source: In-Stat,
World Fab Watch; analyst reports; press clippings; McKinsey team
analysis; 2008)