SIMULATION AND DESIGN OF RF OSCILLATORS
L. Eichinger1, F. Sischka1, G. Olbrich2, R. Weigel3
Agilent Technologies, Germany, 2Munich University
of Technology, Germany, 3University of Erlangen-Nuernberg, Germany
1
Abstract – An accurate simulation and design was
achieved with Computer-Aided-Engineering (CAE)
of RF oscillators. Signal and phase noise modeling of
all passive- and active components in the RF
oscillator circuit is the prerequisite for accurate
simulation. The design showed a very good
agreement between simulated and measured data. The
required modeling methods, the measurements, the
used simulation technologies and the design steps are
presented.
I. INTRODUCTION
Wireless communication systems with complex
digital modulation schemes require low phase noise
RF oscillators. With today’s trend to even more
complex modulation schemes, low phase noise
becomes even more critical. Surface acoustic wave
filters (SAW) and acoustic surface transverse wave
delay lines (STW) are the key components in RF
oscillators as the frequency controlling components to
achieve low phase noise.
CAE models, frequency- and time domain simulators,
optimization and statistical design methods allow an
accurate design of RF oscillators. The Advanced
Design System ADS provides these different types of
RF analyses including DC, linear frequency,
harmonic balance (HB) and phase noise analysis for
non-linear circuits, planar electromagnetic (EM) for
physical design and layout verification, convolution
and circuit envelope for oscillator startup (advanced
time domain and envelope analysis respectively,
which can process frequency models in time domain)
[1].
The design includes both linear and nonlinear
modeling techniques as well as 1/f-noise modeling
and extraction to arrive at specific design goals for
phase noise and output power.
A prototype of this RF oscillator circuit was built up
[2]. The simulation in ADS showed an accurate
oscillator design. A very good agreement between
simulated and measured data was achieved.
II. RF OSCILLATOR DESIGN FLOW AND
CONSIDERATIONS
Accurate oscillator designs require exact linear
models for passive and nonlinear models for active
components as well as phase noise parameters. Fig. 1
shows the schematic of the RF oscillator circuit.
RF_Output
Amplifier1
Matching1
Power_Splitter
Phase_Shift
STW_Delay_Line
Amplifier2
Matching2
Fig. 1: RF oscillator block diagram schematic.
Two identical silicon bipolar low noise MMIC
amplifiers are used. A spice model of the MMICAmplifier was available on the manufacturer‘s Webpages. Flicker-noise (1/f-noise) of the BJT device
strongly influences the phase noise. Unfortunately the
phase noise parameters were not included in the spice
model. 1/f-measurements are required to extract the
phase noise parameters.
The RF oscillator frequency is controlled by the
STW delay line. A set of S-Parameters represents the
model, but these don’t show the 1/f-noise behavior.
1/f-Mesurements have to be performed to model the
STW delay line and finally improve the accuracy of
the RF oscillator design.
The dielectric loss (tanδ) of the substrate material
must be known for precise phase noise analysis.
Even a low factor of quality of components such as
capacitors and inductors have a bad influence on the
phase noise performance.
For each component in this RF oscillator circuit an
approved model must be used and therefore different
measurements and extraction methods are applied.
III. PASSIVE FREQUENCY MODELS AND
SUBSTRATE MATERIAL
Several models for passive components such as a
capacitor (Fig.2) are available. The simplest model is
to define the capacity and the factor of quality. A
more precise model needs a more complex model [4].
In this RF oscillator design high Q components are
used. The models are provided within the ADS
libraries.
delay line, whereby both must have a similar
characteristic (Fig. 3a).
Fig. 3a: 1/f-measurement setup of STW delay line
The flicker frequency fα[STW] was experimentally
determined to be 3.5 kHz and the system noise floor
is -163 dBc/Hz. Fig. 3b shows the 1/f-measurement
of the STW delay line.
C1
C=1.0 pF
C2
C=1.0 pF
Q=50.0
F=100.0 MHz
Mode=proportional to freq
SRLC1
R=1.0 Ohm
L=1.0 nH
C=1.0 pF
Fig. 2: RF models for capacitor
The RF oscillator was built on a high Q substrate
material (RT-Duroid). The substrate data was
provided by the manufacturer.
The most important parameters are the dielectric loss
(tanδ=0.002) and the conductivity (Cond= 5.8E+7
Siemens/Meter) for accurate phase noise simulation.
Fig. 3b: 1/f-measurement results of STW delay line
These two parameters are sufficient to make a 1/fnoise model of the STW, because the system noise
floor has an approximately constant level of -163
dBc/Hz with frequency and intercepts with the
determined flicker frequency at fα[STW]=3.5 kHz. For
offsets below fα[STW] the phase noise increases with
1/f-. Fig. 4a demonstrates the nonlinear noise (1/fnoise) simulation setup.
S-parameter
data set
of the STW
IV. 1/F-NOISE MEASUREMENT AND
MODELLING OF THE STW DELAY LINE
S-parameters of the STW delay line were measured
using a network analyzer. These measured Sparameters don’t contain the 1/f-noise. Measurements
were made with a phase noise system to characterize
the noise floor and the flicker frequency fα[STW] of the
STW delay line. A highly stable source is splitting the
signal into two paths. Each path contains a STW
Source
1
SRC1
V_Noise=(0.13/(sqrt(noisefreq))) uV
2
Vout
Ref
SNP1
File="saw.s2p"
Term2
Fig. 4a: Schematic of the 1/f-noise simulation of the
STW delay lines.
The frequency of the RF signal source is set to the
STW delay line center frequency. The noise voltage
source is connected in series with the S-parameter
data set to get the 1/f-noise noise characteristic of the
real STW. Equation 1 is used in the noise voltage
source element to determine the noise voltage.
Vnoise =
k0
[µV]
(1)
f noise
V. 1/F-NOISE MODEL EXTRACTION OF
THE MMIC-AMPLIFIER
An ADS and a SPICE model of the MMIC
amplifier (MSA0835) is available. However, it does
not cover the noise performance.
1/f-NOISE MEASUREMENT
In order to extract the 1/f-noise parameters of the
MMIC amplifier, measurements of the noise voltage
power spectral density across the load resistance have
to be performed at several bias conditions [3]. Fig. 5
shows the schematic of the measurement setup.
The phase noise analysis mixes the frequency down
to zero and delivers the 1/f-phase noise spectrum at
the node Vout. An optimization of ko was performed.
The goal was to fit the simulated (Fig. 4b) to the
measured (Fig. 3b) 1/f-noise curves. The final
simulation results are depicted in Fig. 4b with an
optimized parameter of k 0 =0.13.
Psb/Pc (dBc/Hz)
To demonstrate the absence of 1/f-noise in the Sparameter data set we run the same simulation of Fig.
4a without the noise voltage source. The trace in Fig
4b (indicated with x) resulted from this simulation.
The modified model (S-parameter data set and the
noise voltage source in series) is used in the oscillator
circuit to simulate an accurate phase noise.
m1
noisefreq=4.078MHz
pnmx=-163.0 dBc
0.0000
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-170.0
ko
m1
40.00M
10.00M
1.000M
100.0k
10.00k
1.000k
100.0
10.00
1.000
noisefreq, Hz
Fig. 4b: Simulation results of the 1/f-noise.
A very good agreement between measured and
simulated results could be achieved.
Fig. 5: Low frequency noise measurement setup.
Device under test (DUT) is the amplifier. The supply
voltage (VCC) is fed via low-pass filters in order to
achieve a low system noise level. A blocking
capacitor decouples the noise voltage of the amplifier
output signal from DC components. The output signal
is fed to the baseband noise input of a phase noise
measurement system. The amplified noise power
spectral density is then detected using an FFT
analyzer in the frequency range from 1Hz to 100kHz
and using an analog spectrum analyzer in the range
from 100kHz to 10MHz. By replacing the DUT with
a 50 Ohm load, the noise floor of the entire
measurement setup is checked. In the frequency range
of interest the system noise floor is found to be 50dB
to 30 dB below the measured noise data of the
amplifier in the operating bias point.
1/f-NOISE EXTRACTION
The amplifier chip comprises two transistors and six
diodes. In the amplifier model, the diodes are used to
represent the nonlinear distributed base-collector
capacitance. They are not forward biased and should
not conduct any current. Therefore they are not
significant contributors to 1/f-noise, which is
proportional to DC current. The dominant 1/f-noise
source location is in the input bias current of a bipolar
A
inb
2
I f
= K f ⋅ b ⋅ ∆f .
f
(2)
-100
-110
Sv[dBV/sqr(freq)]
junction transistor (BJT) and is integrated in the
Gummel-Poon model as a noise current source
parallel to the base-emitter contact. The 1/f-noise
model equation for a bipolar transistor follows the
equation
-120
1/f
-130
-140
-150
-160
Af and Kf are the noise parameters we are looking for.
It is important to check the DC model performance
first (fitting of Ib). In our case, referring to the whole
amplifier chip rather than individual transistors, we
compare the DC supply current ICC vs. VCC from
measurements and simulations with the DC
parameters. The extraction Software IC-CAP [4] was
applied to this task. As depicted in Fig. 6, the fit is
very good, which allows to continue with the second
step, the 1/f modeling. Applying an IC-CAP toolkit
[5], the parameters Af and Kf identical for both
transistors, were extracted as Af = 1.0 and Kf = 28.5E15 respectively over different bias voltages VCC. Fig 7
shows the measured and simulated noise voltage
spectra at the used bias voltage of VCC=15V in the
oscillator circuit. The flicker frequency of the
amplifier fα[amp] was determined to be 8 kHz. Again, a
very good fit between measurement (
) and
) was obtained.
simulation (
Fig. 6: The measured (─) and the simulated (---)
supply current ICC versus supply voltage VCC in order
to quickly check the provided chip model parameter
quality.
-170
1E1
1E2
Flicker Frequency
1E3
1E4
1E5
1E6
Noise Freq [Hz]
Fig. 7: 1/f-noise modeling result of the amplifier chip.
V. RF OSCILLATOR SIMULATION AND
OPTIMIZATION
In our design flow we used different simulation
technologies of ADS [1]. These technologies
incorporate the effects of nonlinear distortion, high
frequency effects and noise. The extracted and
approved models from previous sections are used in
the design. The layout traces are represented as
microstrip lines, corners, tees and vias, etc. to model
the effects of the layout parasitics in the oscillator
circuit.
First a DC simulation was performed to make sure the
DC-operating point of the oscillator circuit is correct.
The linear frequency oscillator analysis and the
advanced Hybrid Optimizer [1] found the various
values of the phase shift component and of the
matching networks to meet the oscillation conditions.
The linear frequency simulation can’t show the exact
operation frequency of the RF oscillator, but it helps
to approximate and find the first guess. With that
knowledge the HB-simulator will find the correct
oscillation frequency, the higher harmonics and the
output power belonging to them very quickly and
easily. The phase noise analysis is part of HB.
RF oscillator startup frequency was evaluated with
Circuit Envelope.
Before building up the prototype a harmonic balanceplanar electromagnetic (HB-EM) Co-Simulation was
performed for verification.
8
4
0
-4
-8
-12
180
135
90
45
0
-45
-16
-20
-24
-90
-135
-180
O pen Loop Phase (G rad)
O pen Loop G ain (dB)
LINEAR CIRCUIT SIMULATION
In the first design step the Matching1, the Matching2
and the Phase Shift component, in Fig. 1 of oscillator
circuit were simulated and optimized with the high
frequency linear circuit simulator (S-parameter
analysis) to get an open loop gain greater than one
and zero phase angle. The linear simulator first
performs a DC analysis, while the nonlinear devices
are linearized at the bias point. All components are
characterized by their small-signal [S] or [Y]
parameters. It finds the solution such that the sum of
all AC currents into each circuit node is zero. Then it
computes the S- and Y- Parameters of the overall
circuit at external ports [1]. In order to compute the
oscillation condition of the closed loop oscillator
circuit, the test component OscTest was placed
between the phase shift element and amplifier1 (Fig
1). It computes the small signal loop gain of the
oscillator without breaking up the oscillator loop. The
initial linear frequency analysis shows that the open
loop gain is higher than 0 dB and the phase is 0
degrees at the operating frequency (Fig. 8). To get the
exact oscillation frequency and output power, a
harmonic balance simulation has to be performed.
1.9820
1.9815
1.9810
1.9805
1.9800
1.9795
1.9790
1.9785
1.9780
freq, GHz
Fig. 8: Open-loop gain (indicated with x) and phase
(indicated with o) of the oscillator.
HARMONIC BALANCE SIMULATION
The harmonic balance (HB) simulator [1] and the
ADS test element “OscPort” was used for nonlinear
oscillator circuit analysis, noise analysis and
optimization. In the HB simulation, the OscPort was
used instead of the OscTest element. The OscPort is a
special element used in HB analysis of an oscillator
where the simulator must find both the frequency of
oscillation and the spectral solution. It is used to
intercept the oscillator feedback loop without
breaking it or altering the circuit characteristics. The
HB simulator and the “OscPort” component
automatically determine the operating characteristics.
Power Out [dBm]
DC SIMULATION
The first step in the oscillator design is to perform a
DC analysis to verify the operating point of the
Amplifier. The DC analysis automatically checks the
topology of the circuit and finds the solution
iteratively such that the sum of all DC currents into
each circuit node is zero. It uses the Newton-Raphson
convergence algorithm for nonlinear devices (BJTs,
FETs, diodes).
10
0
-10
-20
-30
-40
-50
-60
-70
m1
m2
0
2
4
m1
freq=1.98078E9
dBm(vout)=6.42135
m3
6
8
10
freq, GHz
12
m2
freq=3.962E9
dBm(vout)=-17.764
14
16
18
m3
freq=5.942E9
dBm(vout)=-22.100
Fig. 9: Simulation of the oscillator output spectrum.
The initial simulation process performs three steps:
First, finding the frequency, where the circuit satisfies
the linear oscillation condition. Second, it calculates
the frequency and the power such that the open-loop
gain is at unity magnitude and zero phase angle. The
third step is a harmonic balance analysis of the
closed-loop oscillator to get an accurate solution. Fig.
9 shows the simulated spectrum.
PHASE NOISE SIMULATION
The phase noise analysis is incorporated in the ADS
HB simulator [1]. ADS analyzes the phase noise in an
oscillator by two separate, independent methods,
from the oscillator frequency sensitivity to noise
(pmfm), and from small-signal mixing of noise
(pnmx) [1]. The frequency sensitivity to noise may be
viewed as the oscillator acting as a VCO and
changing its operating frequency due to FM
modulation caused by noise generated in the
oscillator. The small-signal mixing of noise comes
from the nonlinear behavior of the oscillator, where
noise mixes with the oscillator fundamental and
harmonics mix into sideband frequencies on either
side of the oscillator signal. These two models are
two different ways of looking at the same problem.
The simulated single sideband phase noise results are
shown in Fig. 10. These phase noise simulation
results have the names pnmx and pnfm and are the
results from the two different phase noise analyses
that are performed for an oscillator. The mixing
analysis (pnmx) for phase noise is automatically
performed by ADS. Below the oscillator feedback
frequency f τ , both results, pnmx and pnfm, are
identical. The oscillator feedback frequency f τ is
equal to
1
.
(3)
fτ =
2πτ
In our case the oscillator feedback frequency
f τ =290kHz, while the STW delay line has a group
delay of τ=550ns [2]. Above f τ , pnmx is the correct
result, because the FM noise analysis is not capable
of displaying the broadband noise floor.
0
m3
m2
noisefreq=1.000kHz noisefreq=10.00kHz
pnfm=-100.4 dBc pnfm=-128.5 dBc
-20
Psb/Pc (dBc/Hz)
-40
-60
-80
m2
-100
m3
-120
-140
-160
-180
-200
1.000
10.00
100.0
1.000k 10.00k 100.0k 1.000M 10.00M
noisefreq, Hz
Fig. 10: Simulation of single-sideband phase noise of
RF oscillator.
VERIFICATION OF LAYOUT PARASICTICS
WITH HB-EM-CO-SIMULATION
In a typical high frequency design flow, single
analytical microstrip models are used. If microstrip
lines are placed very closely, coupling effects could
disrupt the RF-circuit. In our design we verified the
RF oscillator design with a Co-Simulation of
harmonic balance (HB) and planar electromagnetic
(EM) before building up the prototype, to take the
layout parasitics into account.
A layout component was automatically generated by
Momentum for usage in the schematic as an EM
based model. The symbol is a scaled version of the
layout artwork. Fig. 11 shows the schematic of the
layout component connected to the MMICAmplifiers, the STW delay line and the lumped
components. The HB-EM-Co-simulation showed
very good agreement with the analytical models.
Fig. 11: Schematic with layout component for HBEM-Co-simulation
VI. INFLUENCE OF THE MODEL
PARAMETERS ON PHASE NOISE
PERFORMANCE
In this section the impact of the model parameters on
the phase noise performance is discussed. The
following models are used in the RF oscillator design,
which are described in previous sections.
- STW delay line model: S-parameters were
measured and a 1/f-noise model was extracted
(Section IV).
- MMIC amplifier model: A Spice model was
available. The phase noise parameters were
extracted and used in the Spice model (Section
V).
- High Q capacitors model: The models were used
from the ADS library.
The phase noise analysis delivered -100.4dBc/Hz at
1kHz offset, based on these parameters (Fig. 10).
If only one parameter is not considered, an error
would occur, e. g.
-
if the 1/f-noise of the STW delay line is not
considered, the phase noise simulation results
will have an error of 3.8 dB.
a phase noise simulation without having the
phase noise parameters Af and Kf will result in an
error of 1.9dB.
an error of 0.6 dB will occur, if no capacitor
models are available.
If all these 1/f-noise parameters are not considered
(all phase noise parameters are ideal), then the error
of the phase noise simulation is 13.1dB.
If a lower Q-substrate would be used, e.g. tanδ=0.06,
the phase noise would be degraded to -96.5dBc/Hz
against –100.4dBc/Hz.
VII. DISCUSSION OF SIMULATED AND
MEASURED DATA
The HB analysis delivered a very accurate oscillation
spectrum (Fig. 9) compared with the measured
results.
The single-side-band phase noise in Fig. 12 was
measured up to 300 kHz with a phase noise
measurement
system
using
the
frequency
discriminator method.
Fig. 12: Measurement of single-sideband phase noise
of RF oscillator.
An excellent agreement of the simulated (Fig. 10) and
the measured (Fig. 12) singe-sideband phase noise
was achieved. The calculated and the simulated
oscillator feedback frequency f τ are identical. The
measured and simulated phase noise of the STW
delay line oscillator is –100 dBc/Hz at 1 kHz and –70
dBc/Hz at 100 Hz.
CONCLUSION
In this paper an accurate RF oscillator design and
simulation is described. Most important is the correct
signal and phase noise modeling of all passive and
active devices. We used a nonlinear model (Gummel
Poon) for the active devices, measured the 1/f-noise
at different operating points and extracted the phase
noise parameters. A 1/f-noise model of the STW
delay line was developed. Exact substrate data and
RF-models of the lumped components were used to
achieve the goal. All these resulted in accurate phase
noise simulations. This demonstrates an example of
an accurate design before building up the prototype.
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Weigel, „A 2 GHz surface transverse wave
oscillator with low phase noise“, IEEE Trans.
Microwave Theory and Techniques, MTT-36, no.
12, pp. 1677-1684, Dec. 1988
[3] F. X. Sinnesbichler, M. Fischer, G. R. Olbrich,
„Accurate extraction method for 1/f-noise
parameters used in Gummel-Poon type bipolar
junction transistor models”, IEEE MTT-S Digest,
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[4] Franz Sischka, „ IC-CAP Characterization &
Modeling Handbook”, Agilent Technologies,
[5] EEsof-EDA 2003,
http://eesof.tm.agilent.com/docs/iccap2002/iccap
_mdl_handbook.html
[6] F. Sischka, „1/f noise modeling IC-CAP Toolkit”,
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http://eesof.tm.agilent.com/docs/iccap2002/MDL
GBOOK/7DEVICE_MODELING/6NOISE/NOI
SEdoc.pdf