Digital IF Implementation of the GSM and
EDGE Modulation/Demodulation Schemes on
the same Hardware Platform
Christophe Moy Ph.D., Apostolos A. Kountouris Ph.D., Luc Rambaud, Pascal Le Corre*
Mitsubishi Electric ITE, Telecommunication Laboratory (TCL),
Rennes, France (tel.: +33-(0)2-99842110,
e-mail: {kountouris, moy, rambaud}@tcl.ite.mee.com
Abstract --This paper illustrates that the software
radio principles are of great interest in the context of
multi-standard environments. Taking advantage of last
generation VLIW DSPs and configurable DUC/DDC,
waveforms are generated at Tx and processed at Rx, in
the digital domain, using the same HW components. In
software radio as much as possible of the processing is
done in software. Our case study is A real-time dual
mode GSM-EDGE modulation/demodulation IF testbed.
The functional mapping of the SW blocks on the HW
platform and its performance are described.
Index Terms--Software Radio, multi-mode, digital IF,
dual mode GSM/EDGE, VLIW DSP, undersampling…
I.
D
INTRODUCTION
mode radio systems are currently most of
the time made of the juxtaposition of two
physical hardware chains integrated in the
same box. In these transceiver chains, architecture
commonality stops at the point that the digital signal
processing accelerates. In most present designs specific analog circuitry handles frequency up-conversion
from baseband (BB) for Tx and down-conversion to
baseband for Rx. The extension of the digital processing closer to the antenna, in other words replacing
the former analog processing, permits to use of the
same components and contributes to bring more and
more re-configurability to the radio part. Digital often
indeed means configurable.
This paper gives a concrete illustration of these assessments in the context of a dual mode GSM-EDGE
system, combining that way both voice and high data
rate services. Only modulation and demodulation
functions are concerned here, from baseband to a low
IF of several MHz. In the following, after presenting
the generic platform used as a proof of concept for
SoftWare Radio (SWR) implementations, we describe
*
UAL
P. Le Corre is with IPSIS, Rennes, France (tel.: +33-(0)299275327, e-mail: plecorre@ipsis.fr).
in detail the dual GSM-EDGE modem implementation. Finally, performance, in terms of signal quality
and processing speed, is discussed.
II. A SWR EXPERIMENTATION PLATFORM
A. General description
In our laboratory an experimentation platform was
assembled to study SWR system design, as well as
reconfigurability and reconfiguration issues [1].
This platform, shown in FIG. 1, has a modular
hardware architecture making future upgrades possible. The presence of multiple DSPs enables the study
of multiprocessing issues. In the future the introduction of FPGA modules will permit to apply co-design
techniques and address hardware and software reconfiguration in a unified manner. A/D and D/A boards
interface the digital part to the air medium, enabling
digital IF applications. All code development is done
in C offering a high degree of portability from this
platform to any other processor, as SWR dogma requires. Finally, taking advantage of the universal
decomposition of any radio signal by its quadrature
components, a complex representation of any baseband signal is possible.
B. Detailled Tx
The SWR approach consists in moving the digital
to analog conversion (DAC) as close as possible to
the antenna. Frequency translation can be done digitally by multiplication of the I and Q data streams by
digitally generated cosine and sine waves (DDS: Direct Digital Synthesis) as shown on FIG. 2.
fSymb
fS
fS
fDAC
fDAC
Quad ‘C6201
Complex Mixer
C6201
Decimating
Filter
FIFO
In
I
Pulse
shaping
↑
xp(t)
RAM
C6201
FIFO
Decimating
Filter
C6201
Over
sampling
y(t)
bk
Pulse
shaping
↑
xq(t)
sin
III. SW IMPLEMENTATION
Sin(2πf0t)
DDS
FIG. 2 – Functional diagram of the digital transmitter
The physical architecture of the transmit part of our
platform is depicted in FIG. 3; it is appropriate to
implement the functionality of FIG. 2. Note that the
DDS function may be realized either by the digital
upconverter (DUC) chip or by DSP software when the
DUC is by-passed.
The implementation is described below. Though
our performance target was 270.83 kbauds (as defined
in the standards), the following examples have been
worked out for a symbol rate of 250 kbauds for simplification and ease of understanding.
A. GSM
FIG. 6 and 7 represent the functional block diagram
of the GSM modulator and demodulator.
C6201
FIFO
C6201
C6201
RAM
Q
Gaussian
filter
FSK
h=0.5
Inter
Filter
8
Complex Mixer
Interpolating
Filter
Inv
SINC
12-bit
200 MHz
D/A
Interpolating
Filter
FIFO
IF
Out
< 80 MHz
DDS
FIG. 6 - GSM functional block diagram for Tx
sin
0 - 100 MHz
DDS
Buffer
RF
Out
cos
cos
C6201
4á
DAC
sin
NRZ
DUC & DAC
bypass
Complex Mixer
Inter
Filter
8
Bits
I
DDS
FIG. 5 – Platform receiver
Over
sampling
Quad ‘C6201
IF
In
< 30 MHz
In
Q
Buffer
bandpass
RF
filter
DAC
12-bit
65 MHz
A/D
cos
C6201
Cos (2πf0t)
ak
DDC & ADC
bypass
Complex Mixer
Decim
Filter
8
FIG. 3 – Platform transmitter
sin
ADC
Phase
calculation
(Cordic)
C. Detailled Rx
To adhere to the software radio design philosophy,
a wideband RF sampling ADC replaces the multiple
front ends. A top-level functional block diagram of
such a digital receiver is shown in FIG. 4.
Decision
FSK
4â
BER
Decim
Filter
8
RF
In
cos
DDS
FIG. 7 - GSM functional block diagram for Rx
Cos
xp(t)
I
BPF
ADC
Q
Digital
Low pass
filter
DSP
Demod.
01010
bits
stream
B. EDGE
EDGE [2] functional block diagram of the transceiver is on FIG. 8 and 9.
xq(t)
8á
I
Sin
Mapping
8-PSK
(8-PSK
to
16-PSK)
DDS
8á
FIG. 4 – Functional diagram of the digital transmitter
This has been realized on the hardware (HW) system of FIG. 5. The digital down converter (DDC) is
by-passable.
Rotation
3 pi / 8
Q
Edge
Filter
Inter
Filter
16
Complex Mixer
sin
Inter
Filter
16
DAC
Bits
Edge
filter
RF
Out
cos
DDS
FIG. 8 - EDGE functional block diagram for Tx
Complex Mixer
Decim
Filter
8
Zero
forcing
Filter
sin
ADC
Decim
Filter
8
Zero
forcing
Filter
8â
Rotation
-3 pi / 8
Decision
8 PSK
(Cordic)
(16-PSK
to
8-PSK)
BER
8â
cos
DDS
FIG. 9 - EDGE functional block diagram for Rx
It is worth noting that an important part of Rx
functionality is synchronization (carrier recovery and
sampling time adjustment). These functions were
implemented as well but are not shown to keep the
figures simple.
The mapping operation on the HW results in the
characteristics of TAB 1.
fbits (kbits/s)
fsymbols (ksymbols/s)
BB oversampling
fsamples
(Msamples/s)
DAC interpolation
fDAC (MHz)
decimation
fADC (MHz)
f0 (MHz)
IF (MHz)
GSM
Tx
GSM
Rx
EDGE
Tx
EDGE
Rx
250
250
4
1
250
250
4
750
250
8
2
750
250
8
2
1
8
8
2
10
Error Vector Magnitude (EVM) figures of TAB. 2
reveal quite satisfactory. EVM gives the deviation of
a received constellation from an ideal reference constellation.
Modulation
GSM
EDGE
2
2
RF
EVM (% rms)
2 MHz
10 MHz
2 MHz
1.24
2.32
0.159
TAB. 2 - Error vector magnitude (EVM)
16
32
8
8
2
10
FIG. 10 - EDGE for fRF = 2 MHz
8
8
2
2
TAB. 1 - GSM and EDGE transceivers
C. Undersampling
It can be seen that in the GSM case we use the under-sampling technique. At Tx, the goal is to produce
sampled versions of the modulated signal by using a
sampling rate fDAC greater than 2 f0, where f0 is a low
carrier frequency. Taking advantage of the replicas of
the digital signal the real carrier frequency IF is chosen at n.fDAC+f0 where n is a positive integer. Similarly at Rx, a convenient ratio between IF and fsamples
has to be respected [3].
B. Implemented performances
Several performance measurements were obtained.
Performance was considered in terms of execution
speed (CPU cycle counts) and attained bit rates. The
results are given in TAB. 3. For the two implementation schemes, we measured the global performance of
the Tx, Rx chains as well as the performance of only
the modem functionality.
Implementation parameters to be taken into account
are those of TAB. 1. The Tx the full chain consists of:
Bit Generation - Modulator - IO Data Transfer.
Similarly for Rx, it consists of: IO Data Transfer Demodulator - Synchronizations - BER.
Modem
Required
Perf.
kbits/sec
IV. PERFORMANCES
Performance is considered both in terms of quality
of the transmitted signal, and of computation speed of
the software running on the DSP processor.
A. Measured quality with a VSA
The modulators were validated using a vector signal analyzer (VSA), and the results shown in FIG. 10
were obtained for EDGE.
GSM
EDGE
270.83
812.49
Tx
Rx
Full
Chain
Modulator
Full
Chain
397.85
2353.7
444.6
3107.9
622.45
1329.2
Demodulator
753.56
1520.19
TAB. 3 - Attained bit rates for GSM and EDGE
It can be seen that for single processor implementations (C6201 DSP at 200 MHz) of Tx , Rx for
GSM, EDGE the attained performance is higher than
the required for one channel. The C6x roadmap shows
that soon processors at 1GHz clock speeds will be
available (i.e. C64x). Having the software written in
some IF. In other words, it is possible to design a
dual-mode GSM / EDGE, modulation / demodulation
system running on exactly the same components.
What has been shown here for one 250 kHz channel is applicable in a multi-carrier situation, which we
plan to study in the future. We have also applied the
same concept to other wireless systems such as BlueTooth, and the future 3G cellular phone standard
UMTS [6]. In these cases several processors have to
be involved to obtain real-time performance .
However it should be noted that the components we
used are not those found in current embedded or portable systems for size and energy consumption reasons. Also for the time and analog RF was ignored in
our work. As technology progress in these directions
the SWR concept will find its way in such applications as well.
high-level language code will permit to easily take
advantage of technological progress in processor
design and manufacturing. The present measurements
indicate that a single C6x could handle both Tx, Rx at
the same time and deliver real-time performance.
However it must be noted that currently the C6x
DSP chip is not destined to mobile terminals due to its
high power consumption, size and price.
C. Repartition of the computation load
Another set of measurements investigates how
processing time is distributed among the transceiver
functional blocks, as shown in FIG. 11.
In the GSM Tx implementation the cos, sin calculations are obtained by the CORDIC trigonometric
algorithm [4]. Other more computationally efficient,
tailored to the GMSK case, methods could be used.
[5] combines gaussian filtering and cos, sin computations into table lookups and potentially it can be extremely fast. At the Rx CORDIC is used for angle
(phase) computation using the arctan function.
These comparative results confirm that modulators
are a lot simpler than demodulators especially when
carrier and timing recovery needs to be implemented.
In addition it is clear that filtering for pulse shaping
though a simple operation it is the most time consuming and this gets worse for higher oversampling
factors. Such simple (regular) but time consuming
processing is a good candidate for a more hardware
oriented implementation. FPGA implementation is
very promising in order to retain the flexibility offered
by reprogrammability.
VI. ACKNOWLEDGMENTS
This work was supported by Trium R&D, Rennes,
France.
VII. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
V. CONCLUSIONS
The results presented here show that it is now feasible to implement some kind of SWR by extending
digital, and especially software, domain to at least
A. Kountouris, C. Moy, L. Rambaud, "Re-configurability: a
Key Property in Software Radio Systems", First Karlsruhe
Workshop on Software Radios, March 2000.
Ashkan Mashhour, "Understanding Offset 8-PSK Modulation
for GSM Edge", Microwave Journal, October 1999
H. Meyr, M. Moeneclaey, S. Fetchel,"Digital Communication
Receivers - Synchronization, channel estimation and signal
processing", Wiley Interscience 1998
J.E. Volder, "The CORDIC Trigonometric Computing
Technique", IRE Trans. Elect. Comput., EC(8):330-334,
1959.
GMSK modulator on DSP, article RF Design
C. Moy, A. Kountouris, L. Rambaud and P. Le Corre, "Full
Digital IF UMTS Transceiver for Future Software Radio
Systems", ERSA'2001, 25-28 June 2001, Las Vegas, USA
F u ll E D G E T x c h a i n
Full GSM Tx chain
IO Data Xfer
9%
Bit Gen.
1%
NRZ Mapping
2%
I O D a t a Xfer
19%
Bit G en.
9%
Interp. & Pulse
Shape
31%
EDGE
%
M a p p4ing
Interp. & Pulse
Shape
IQ Gen.
(CORDIC)
53%
Phase Acc.
4%
Full GSM Rx chain
Frame Sync
8%
BER
1%
IO Data Xfer
16%
Carrier Recovery
Decision
17%
Full EDGE Rx chain
Misc.
BER1% IO Data Xfer
11%
Rx filter
41%
1%
Sampl. Time Rec.
& Decimation
9%
IQ angles (CORDIC)
64%
Decision
2%
Frame Sync
17%
3pi/8 Derotation
3%
Sampl. Time Rec. & Decimation
FIG. 11 - Processing time decomposition in Tx and Rx for GSM and EDGE
9%