CH07 Input/Output
Input/Output Problems
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• Wide variety of peripherals
External Devices
I/O Modules
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access
I/O Channels and Processor
The External Interface: SCSI and FireWire
4Delivering different amounts of data
4At different speeds
4In different formats
• All slower than CPU and RAM
• Need I/O modules
TECH
CH06
Computer Science
Input/Output Module
Generic Model of an I/O Module
• Interface to CPU and Memory
• Interface to one or more peripherals
• GENERIC MODEL OF I/O DIAGRAM 6.1
External Devices
I/O Module Function
• Human readable
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4Screen, printer, keyboard
• Machine readable
4Monitoring and control
• Communication
4Modem
4Network Interface Card (NIC)
Control & Timing
CPU Communication
Device Communication
Data Buffering
Error Detection
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I/O Steps
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CPU checks I/O module device status
I/O module returns status
If ready, CPU requests data transfer
I/O module gets data from device
I/O module transfers data to CPU
Variations for output, DMA, etc.
I/O Module Diagram
Systems Bus Interface
External Device Interface
Data Register
Data
Lines
Status/Control Register
Address
Lines
Data
Lines
Input
Output
Logic
I/O Module Decisions
Input Output Techniques
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• Programmed
• Interrupt driven
• Direct Memory Access (DMA)
Hide or reveal device properties to CPU
Support multiple or single device
Control device functions or leave for CPU
Also O/S decisions
External
Device
Interface
Logic
External
Device
Interface
Logic
Data
Status
Control
Data
Status
Control
4e.g. Unix treats everything it can as a file
Three I/O Techniques
Programmed I/O
• CPU has direct control over I/O
4Sensing status
4Read/write commands
4Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time
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Programmed I/O - detail
I/O Commands
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• CPU issues address
CPU requests I/O operation
I/O module performs operation
I/O module sets status bits
CPU checks status bits periodically
I/O module does not inform CPU directly
I/O module does not interrupt CPU
CPU may wait or come back later
4Identifies module (& device if >1 per module)
• CPU issues command
4Control - telling module what to do
f e.g. spin up disk
4Test - check status
f e.g. power? Error?
4Read/Write
f Module transfers data via buffer from/to device
Addressing I/O Devices
I/O Mapping
• Memory mapped I/O
• Under programmed I/O data transfer is very like memory
access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier (address)
4Devices and memory share an address space
4I/O looks just like memory read/write
4No special commands for I/O
f Large selection of memory access commands available
• Isolated I/O
4Separate address spaces
4Need I/O or memory select lines
4Special commands for I/O
f Limited set
Interrupt Driven I/O
Simple Interrupt Processing
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
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Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral whilst CPU
does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
CPU Viewpoint
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Issue read command
Do other work
Check for interrupt at end of each instruction cycle
If interrupted:4Save context (registers)
4Process interrupt
f Fetch data & store
• See Operating Systems notes
Design Issues //
Identifying Interrupting Module (1)
• How do you identify the module issuing the interrupt?
• How do you deal with multiple interrupts?
• Different line for each module
4i.e. an interrupt handler being interrupted
4PC
4Limits number of devices
• Software poll
4CPU asks each module in turn
4Slow
Identifying Interrupting Module (2)
Multiple Interrupts
• Daisy Chain or Hardware poll
• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
• If bus mastering only current master can interrupt
4Interrupt Acknowledge sent down a chain
4Module responsible places vector on bus
4CPU uses vector to identify handler routine
• Bus Master
4Module must claim the bus before it can raise interrupt
4e.g. PCI & SCSI
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Example - PC Bus
Sequence of Events
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• 80x86 has one interrupt line
• 8086 based systems use one 8259A interrupt
controller
• 8259A has 8 interrupt lines
PC Interrupt Layout
8259A accepts interrupts
8259A determines priority
8259A signals 8086 (raises INTR line)
CPU Acknowledges
8259A puts correct vector on data bus
CPU processes interrupt
ISA Bus Interrupt System
8259A
8086
• ISA bus chains two 8259As together
• Link is via interrupt 2
• Gives 15 lines
CPU
• IRQ 9 is used to re-route anything trying to use IRQ 2
416 lines less one for link
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
4Backwards compatibility
INTR
• Incorporated in chip set
I/O Module
ISA Interrupt Layout
Foreground Reading //
• http://www.pcguide.com/ref/mbsys/res/irq/func.htm
(IRQ 2)
8259A
IRQ0 (8)
IRQ1 (9)
IRQ2 (10)
IRQ3 (11)
IRQ4 (12)
IRQ5 (13)
IRQ6 (14)
IRQ7 (15)
8259A
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
80x86
• In fact look at http://www.pcguide.com/
INTR
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Direct Memory Access
DMA Function
• Interrupt driven and programmed I/O require active
CPU intervention
• Additional Module (hardware) on bus
• DMA controller takes over from CPU for I/O
4Transfer rate is limited
4CPU is tied up
• DMA is the answer
DMA Transfer
Cycle Stealing
DMA Operation
• CPU tells DMA controller:-
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
4Read/Write
4Device address
4Starting address of memory block for data
4Amount of data to be transferred
4CPU does not switch context
• CPU suspended just before it accesses bus
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished
4i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU doing
transfer
DMA Configurations (1)
DMA Configurations (2)
CPU
CPU
DMA
Controller
I/O
Device
I/O
Device
• Single Bus, Detached DMA controller
• Each transfer uses bus twice
4I/O to DMA then DMA to memory
• CPU is suspended twice
Main
Memory
DMA
Controller
I/O
Device
I/O
Device
DMA
Controller
Main
Memory
I/O
Device
• Single Bus, Integrated DMA controller
• Controller may support >1 device
• Each transfer uses bus once
4DMA to memory
• CPU is suspended once
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DMA Configurations (3)
I/O Channels
• I/O devices getting more sophisticated
4e.g. 3D graphics cards
DMA
Controller
CPU
I/O
Device
I/O
Device
• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once
I/O
Device
Main
Memory
I/O
Device
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed
4Takes load off CPU
4Dedicated processor is faster
4DMA to memory
• CPU is suspended once
6.7 External Interfacing
Small Computer Systems Interface (SCSI)
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Connecting external devices together
Bit of wire?
Parallel interface; e.g. parallel port, SCSI
Serial interface; e.g. serial port, FireWire
Point-to-point; e.g. keyboard, modem, display
Multipoint; SCSI, FireWire, USB, (Bus)
Parallel interface
8, 16, 32 bit data lines
Daisy chained; host7~d0~d1~…d6~T
Drive 7 has highest priority
Devices are independent
Devices can communicate with each other as well as
host
Configuring SCSI
SCSI - 1
• Bus must be terminated at each end
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4Usually one end is host adapter
4Plug in terminator or switch(es)
• SCSI Id must be set
4Jumpers or switches
4Unique on chain
40 (zero) for boot device
4Higher number is higher priority in arbitration
Early 1980s
8 bit
5MHz
Data rate 5MBytes.s-1
Seven devices
4Eight including host interface
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SCSI - 2
SCSI Signaling (1)
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• Between initiator and target
1991
16 and 32 bit
10MHz
Data rate 20 or 40 Mbytes.s-1
• (Check out Ultra/Wide SCSI)
4Usually host & device
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Bus free? (c.f. Ethernet)
Arbitration - take control of bus (c.f. PCI)
Select target
Reselection
4Allows reconnection after suspension
4e.g. if request takes time to execute, bus can be released
SCSI Signaling (2)
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Command - target requesting from initiator
Data request
Status request
Message request (both ways)
SCSI Timing Diagram
SCSI Bus Phases
Reset
Bus
free
Arbitration
(Re)Selection
Command,
Data,
Status,
Message
SCSI Read e.g. (transfer data from target to
initiator)
• (1) Arbitration
4Each device asserts BSY and one of data lines (0,1,2,…7
highest), highest priority wins
4 Winner is the initiator
• (2) Selection phase
4Initiator asserts SEL, its own ID, target ID
4Initiator negates BSY
4Target recognizes its ID, it assets the BSY
4Initiator release the data bus and negates SEL
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SCSI Read e.g. cont…
SCSI Read e.g. cont…
• (3) Command phase
• (4) Data phase
4Target asserts C/D, then asserts REQ
4Initiator places first byte of the command and asserts
ACK
4Target reads the command, then negates REQ
4Initiator then negates ACK
4(this first command contains operation code and how
many bytes remain to be transferred.)
4Use the same REQ and ACK handshaking to transfer
the remaining bytes.
4(in this e.g. the command is a Read; transfer data from
target to initiator
4After interpreted the command, target negate C/D
(means data bus contains data), it asserts I/O (means
direction of transfer is target to initiator)
4Target places the first byte of data on the bus, asserts
the REQ
4Initiator reads the byte and asserts ACK
4The remaining data transfer using REQ and ACK
handshaking
SCSI Read e.g. cont…
IEEE 1394 FireWire //
• (5) Status phase
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4Target asserts C/D, and remains asserting I/O
4Use REQ and ACK handshaking to transfer
successfully transfer, (no problem)
• (6) Message Phase
4Target asserts MSG, places “Command Complete”
message on the bus, use REQ and ACK
4Target received ACK from initiator, then release all bus
signals and negates BSY
4(Done!)
High performance serial bus
Fast
Low cost
Easy to implement
Also being used in digital cameras, VCRs and TV
Sony call this bus I-link.
FireWire Configuration
FireWire 3 Layer Stack
• Daisy chain
• Up to 63 devices on single port
• Physical
4Really 64 of which one is the interface itself
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Up to 1022 buses can be connected with bridges
May be tree structure
Hot plugging
Automatic configuration
No bus terminators
4Transmission medium, electrical and signaling
characteristics
• Link
4Transmission of data in packets
• Transaction
4Request-response protocol
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FireWire - Physical Layer
FireWire - Link Layer
• Data rates from 25 to 400Mbps
• Two forms of arbitration
• Transmission of data in the from of packets
• Two transmission types
4Based on tree structure
4Root acts as arbiter
4First come first served
4Natural priority controls simultaneous requests
f i.e. who is nearest to root
4Fair arbitration (time for using bus by fairness
intervals)
4Urgent arbitration (urgent device may use up to 75% of
the bus time)
4Asynchronous
f Variable amount of data and several bytes of transaction data
transferred as a packet
f To explicit address
f Acknowledgement returned
4Isochronous
f Variable amount of data in sequence of fixed size packets at regular
intervals
f Simplified addressing
f No acknowledgement
FireWire – Transaction Layer
Foreground Reading
• Define a request-response protocol that hides the
lower-layer details of FireWire from applications
• E.g. TCP/IP
• Check out Universal Serial Bus (USB)
• Compare with other communication standards e.g.
Ethernet
Exercises
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Check up on-line slide show on:
www.laTech.edu/~choi
Read CH 6
Do Problems:
43.1
44.2 & 4.9
45.1
• Due BY Email to:
choi@laTech.edu
• Due by Wednesday
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