A New ATPG Algorithm for 21st Century: The Simplest But Powerful
John Sunwoo, Vishwani D. Agrawal
Dept. of Electrical and Computer Engineering
Auburn University
Auburn, AL 36849-5201
phone: (334)844-1843
john@johnsunwoo.com, vagrawal@auburn.edu
ABSTRACT - In this paper, we proposed a new ATPG
(Automatic Test Pattern Generation) algorithm that can
be easily implemented and learned by college level
student while achieving fairly efficient fault coverage
and fast generation time. Very high level algorithm and
its decision tree have been illustrated. The output of the
ATPG program is the set of test vectors generated by
the new algorithm. The significance of the algorithm is
in the initializing PIs (Primary Inputs) technique. Unlike
like other algorithms that start off with the unknown
(pre-defined as X) PIs values or random (or pseudorandom) PIs values [1], the new algorithm assigns all
PIs values to be non-controlling values according to the
gate which the PI fan-in to. This suggestion seemed to
be an interesting solution for simple but powerful
algorithm. Unfortunately, implementation on software
has not completed. However, we hand-calculated the
TPG vectors using our new algorithm and compared it
with the vectors that Hitec/Proofs generated. We found
the potential advantages of our algorithm over algorithm
that Hitec/Proofs used when testing on c17 bench
circuit.1
1. INTRODUCTION
The main motivation of this project work is to
present a new ATPG technique based on a simple and
robust algorithm. Recently studied algorithm such as
SPIRIT is based on fairly complex heuristic and
solution which is not suitable for college level student.
D-algorithm is known for the simplest ATPG algorithm,
however, lots of later work has proven that D-algorithm
can be developed to be more efficient. The motivation
and objective of this project initially was to develop
such a reliable and efficient ATPG algorithm while
keeping the level of difficulty reasonably low. In other
words, we believed that there would be such ATPG that
is efficient and compatible without the need of complex
implementation based on deep level of heuristic.
The major advantage we were looking for was the
efficiency of the algorithm itself that was cause by its
simple heuristic method. Unlike other algorithm, the
newly invented algorithm starts from fully know PIs
(Primary Inputs). This leads all the nodes in the circuit
This work is done in ELEC7250 (VLSI Testing) course.
1
to be a known state which would be either “0” or “1”.
This will help when the algorithm backtraces because it
can find the way back to PI easier. For example, assume
there are logic “0” and “1” going into an AND gate,
then when the algorithm backtraces to make the AND
gate output “1,” it will simply choose the path where it
holds logic value “0” because through that path, the
value needs to be changed would be found. Efficient
mechanism when assigning PI values is also an
important issue here. The uniqueness of the new
algorithm is mostly presented within this mechanism.
PIs will be assigned with the non-controlling values
according to where the input fan-in to. The reason
behind it is simple and interesting; once the initial PIs
run through the logic simulator, the follow-up change
on only one bit of the PIs enables to achieve higher
chance to activate the target path than using randomly
assigned PIs. The illustrations with figures are presented
in later section. It is based on a simple concept that
would be well followed by any college student.
The new algorithm has been implemented in
software as an embedded object. Initially we were
hoping to use C++ programming language, however, the
plan had changed to use Java programming language
because using Java would take us shorter time to
implement and examine then using C++. One major
drawback of this approach is the performance
degradation of the software due to high CPU memory
usage of the Java programming language. This we hope
to be fixed by rewriting the code in C++. A circuit
reader that reads the circuit, logic simulator has been
implemented in Java software language. In addition,
backtrace () method should have been implemented in
software, however, it has not done yet for this point.
The following section is devoted to the brief
discussion of some of well known ATPG algorithm
from the past years. The algorithm discussed here is
limited to the combinational case only. We will briefly
go over some of the definitions that are important while
reading this paper. And then the following section
illustrates basic problems encountered, followed by the
new ATPG algorithm and its results, this paper finally
concludes.
2.
ATPG ALGORITHM FROM THE PAST
Most of well-known ATPG algorithms such as D,
PODEM, and FAN have common background. The PIs
of the circuit is at the unknown state initially when the
algorithm starts. In these algorithms, a PI will be chosen
to be a logic value only if it helps to obtain the objective
[2][3], otherwise the PI value will remain “unknown”.
However, due to using “unknown” state, the ATPG
algorithm will spend more time on processing &
decision making when it backtraces. This might not be
an efficient way to generate test pattern. Instead, all the
PIs can be fully assigned with known-logical value
initially. This reversed mechanism will bring us some
advantages because before let the algorithm to backtrace
to meet the objective, the fully assigned PIs will let the
fault site get activated by chance. And the fully assigned
PIs found to be helpful since it will turn every node in
the circuit to a known state which is either logic “0” or
“1”. Instead of using 5-value logic [1], it will let the
algorithm use 4-value logic.
3. DEFINITIONS
Terminology that is generally being used as well as
terms that are used in this study is introduced. As shown
in Figure 1, a test for the single stuck fault that causes
node “f” to permanently assume logic “0” state. A
stuck-at-1 (s-a-1) fault on a certain node causes the node
to permanently set on logic “1” state. A stuck-at-0 (s-a0) fault causes a permanent logic “0” state on the node.
The 4-value logic (“0”, “1”, “D”, “D-bar”) of Table 1 is
used to describe the behavior of a circuit with failures.
The value “D” represents a logic value “1” for a node in
the fault-free circuit and logic “0” for the same node in
the faulty circuit, where “D-bar” is the complement of
“D”. Note that when using the 5-value logic, there are
“X” which designates a “don’t care state” [2]. A
behavior difference between the fault-free circuit and
a 0
f 1
b 1
c
1
d
1
s-a-0
D
1
0
1
D
D*
0
0
0
0
0
1
D
D*
0
D
D
0
0
D*
0
D*
Table 1. Four-Valued Logic System Used in Test
Generation (“A” AND “B” Table)
4. ANALYSIS
Conceptually, the algorithm should do two things 1)
activate the fault site and 2) propagate the “D” or “Dbar” to any primary output. Finally when step 1) and 2)
are finished, the PIs inputs are saved. Figure 2 illustrates
the initial PI assignment mechanism used in the new
ATPG algorithm. For PIs “A”, “C” and “D”, logic value
“1” is assigned because they are fan-in to a NAND gate.
When the PIs fan-in to NOR or OR gate as like “B” or
“E” input, then “0” is assigned in order to drive a noncontrolling value.
PI : Assign non-controlling values to start with.
Initial test vector {1, 0, 1, 1, 0}
A=1
...
B=0
...
C=1
D=1
...
1
Figure 2. Sample Combinational Circuit and
Initialized PI Values.
g 0
k 0
e
B
A
0
1
D
D*
E=0
j D-bar
h
assignment of the values, “0”, “1”, “1”, “1”, “1” to the
PIs “a”, “b”, “c”, “d”, “e”, respectly, are the test for the
node f stuck-at-0 [2].
i 1
Figure 1. Example to Illustrate Test Generator
Terminology
the faulty circuit propagates along a sensitized path. In
Figure 1, the signal path “f” – “j” is one of the
sensitized paths. Externally controllable nodes are
referred to as Primary Inputs (PIs) and externally
observable nodes are referred to as Primary Outputs
(POs). A test or test vector is generated when a fault site
become observable through one of the Pos. In Figure 1,
2
Assigning its non-controlling values to each PI
should have advantages over random PI assignment
mechanism. Figure 3. illustrates in a simple logic gate.
Assume there are 4-input AND gate and its inputs are
assigned randomly such that “0”s and “1”s are mixed
together. This can go along with arbitrary input
assignment mechanism shown in [4]. In order to change
the value of the gate output, the algorithm would
backtrace and then changes the PIs by a bit to generate
the effect. It is clearly seen that only one bit change in
the PI is not enough to make the effect on output change
from “0” to “1”. It could also imply that in the actual
algorithm, quite a bit of processing time could be
wasted. In contrast, when all input of the gate assign to
be a non-controlling value of AND gate, then only one
bit change in one of the input definitely changes the
output of the gate from “1” to “0”. We were expecting
to have a higher chance to make a fast and effective
change on the circuit using this approach.
in the circuit. This linked list array is to be updated
simultaneously along with every simulation process. To
compute the logic value of a gate, a function table is
used which looks up and returns the logic value of a
AND, OR, NAND, NOR, XOR gate with any number
of fan-ins.
When the algorithm tries to activate the fault site and
Start
0
1
0
Define an objective
(ex. Z-sa1, then Objective is Z = 0)
Random
1
0
0
Waste of time!
Assign all PIs to its non -controlling
values
0
0
1
1
1
Apply PIs to the circuit
NonControlling
Objective(s) achieved?
{Objective_Check)
1
0
Effective!
no
Backtrace
{To PI ? change a bit of
PI}
yes
Save Vector
Exit Done
1
yes
Fault signal
propagates through output?
no
Find the conflict ? make
it as a secondary
objective
Figure 4. Basic Algorithm Detailing the Bounding
of the Decision Tree.
Figure 3. Disadvantage of random PI assignment
5. NEW ALGORITHM
The high level algorithm can be distinguished by
several phases. First, assign all PIs fully, and simulate.
Then check if the fault site have been activated or not
and if not then change one bit of PIs and simulate until
the fault site gets activated. Once the initial PIs are
assigned to be its non-controlling values to gate where
fan-in to, I expect the follow-up change on only one bit
on PIs enable to achieve higher chance to activate the
target path than using random. If the fault site has been
activated then check if the fault propagates to any PO,
and this can be done by detecting D or D-bar on PO. If
it is successful then save the current PI vector and if not,
then set an additional objective to let the fault propagate
followed by changing an appropriate PI input and
simulate the circuit. The last step will be recursively
done until the fault site become observable through any
PO. Figure 4. shows this in a flow diagram.
Logic simulation is needed to check whether the
fault site has been activated or not. The pseudo-code for
logic simulator is shown in Figure 5. Note that it reads
in a levelized file that Hitec/Proofs generate. The logic
simulator read line by line and parses each line. This
will ensure the simulator evaluates all the nodes in the
circuit from the lowest level to the highest level. This is
because the current logic values of all gate elements at
level 0 need to be computed before the computations at
level 1, etc. A linked list array supported by Java library
utilizes the storage array that holds all the node values
3
Logic Simulator
Read-in circuit file to the buffer
while (no more line in file)
{
Read a line and store them in a linked list, line by
line.
for (int i =0; i < number of nodes; i++)
{
get a line from the level file
for (int j = 0; j < number of elements (tokens)
in the line); j++)
{
if (INPUT) then assign “U” as the value of it
if (OUTPUT) then print out PO value
if (Some GATE) then call the appropriate
input values, evaluate the logic and save the
result in the linked list.
{
if (input value == “U”) then assign the input
value to be the non-controlling value to the
current gate type.
}
}
}
}
Figure 5. Pseudo-Code for a Logic Simulator
propagate the D or D-bar to any primary output, the
procedure such as Backtrace( ) is required. The
following figure presents a pseudo code for a
Backtrace( ) method. Here we are having a fully known
circuit helps backtrace( ) method to be even faster
because the circuit would not have any “unknown state”
Backtrace ( )
Backtrace (label b, value v)
{
while (PI has not updated)
{
1) check input of gate ‘b’
2) change one of the input ‘x’ which needs to be
change to ‘v’. If none of the input value needs to be
change then backtrack.
3) b = b
4) x = v
}
Hitec/Proofs would get. However, the full
implementation on software is still developing, which
made us unable to experiment our algorithm to bigger
circuits. Hand calculated vector was taken and
simulated by Hitec/Proofs software to evaluate the fault
coverage and to compare it with other known algorithm.
myVector = [13,1,1,1,1,1,0,0,1,1,1,0,1$,0$]
}
Figure 7. C17 Bench Circuit
Figure 6. Pseudo Code of Backtrace ( )
thus the backtrace( ) method only needs follow the path
that is conflicting with the objective. This method will
be running recursively until one of the PI changes.
An array type of data structure called “myVector” is
implemented in a linked list which is supported by Java
programming language. It holds the node values of the
whole circuit as shown in Figure 7. The first index
(index 0) indicates the number of nodes. Every index
corresponds to the node number, and numbers with “$”
sign indicates it is a PO value. Based on c17 bench
circuit, hand calculated test generation using the new
algorithm had been done. Table 2. shows an example
decision steps on generating test for node “9” stuck at 1.
Step
path saved=(9-7-4)
PI = [1,1,1,0,1]
check "myVector"
6
7
8
9
Action
Initial objective: set [9] to
"0"
Apply vector
Backtrace from [9] & save
the path (learning)
Apply updated vector
D-bar propagates?
Additional objective: set
[8] to "1"
Backtrace from [8] & learn
Apply updated vector
D detected at PO [13]
10
Save vector, Done
1 0 1 0 1 saved
1
2
3
4
5
Memory
PI = [1,1,1,1,1]
path saved=(8-2)
PI = [1,0,1,0,1]
check "myVector"
The timing information cannot be compared due to hand
calculation. Table 3 provides the comparison between
using Hitec’s ATPG algorithm verses using newly
invented algorithm. The test vector generated by newly
invented algorithm holds smaller size than what Hitec
generated. I believe it shows the potential advantage of
assigning non-controlling values to PIs initially, because
of the simpleness and robustness of backtracing. Note
that both vectors achieve 100% fault coverage, although,
for bigger circuits, higher fault coverage cannot be
guaranteed by the new algorithm.
HITEC
F-coverage
New
Algorithm
5
01111
10011
10001
11111
11100
01101
11011
11101
10100
F-coverage
5
00011
36.40%
36.40%
00010
45.50%
68.20%
00100
50%
77.30%
10001
54.50%
77.30%
10111
77.30%
90.90%
11111
81.80%
95.50%
10000
81.80%
95.50%
01001
90.90%
95.50%
10011
90.90%
100%
01100
100%
Table 3. Performance Analysis on Hitec VS the New
Algorithm.
7. CONCLUSIONS
Table 2. Example Decision Steps Using New ATPG
Algorithm (C17 Bench Circuit)
6. RESULTS
We ran experiments on a c17 benchmark circuit
using new ATPG algorithm. Resulting test vectors and
the fault coverage profile has been compare to what
4
Most of previous ATPG research was based on 5value logic which uses an “unknown” state and assign it
for initial PI values, and showed that they are efficient.
Through this project, we partially examined some
unique approaches such as initial PI assignment
technique, and modified backtracing technique. In this
paper, we proposed potentially efficient techniques
which does not require complex traditional algorithm. In
fact, some of the proposed techniques are adopted from
well-known techniques, while other techniques present
new ideas for improving the robustness of the ATPG
algorithms. As a result, the new algorithm has been
examined for small circuits it shows high chance of
getting 100% fault coverage. However, completeness in
software implementation is required in future to
examine the algorithm to a bigger circuit. There should
be more comparison and analysis on using random PI
verses non-controlling PI. Finally, the new algorithm
gives us a sense of robustness of ATPG algorithm
through the simple but powerful solution on generating
test for combinational circuit.
REFERENCES
[1] M. L. Bushnell and V. D. Agrawal, Essentials of
Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits. Boston: Kluwer Academic
Publ., 2000.
[2] P. Goel, “An Implicit Enumeration Algorithm to
Generate Tests for Combinational Logic Circuits,”
IEEE Trans. Comput., vol. C-30, pp. 215-222, 1981
[3] H. Fujiwara, and T. Shimono, “On the Acceleration
of Test Generation Algorithms,” IEEE Trans.
Comput., vol. C-32, pp. 1137-1144, 1983
[4] V. D. Agrawal, K.-T. Cheng, P. Agrawal,
“CONTEST: A Concurrent Test Generator for
Sequential Circuits,” Proc. 25th Design Automation
Conference, 1988, pp. 84-89
[5] C. Benmenhrez, J. F. McDonald, “The Subscripted
D-Algorithm – ATPG with Multiple Independent
Control Paths,” IEEE 3rd Automatic Test Program
Generation (ATPG) Workshop, pp.71-80, 1980
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