DESIGN AND IMPLEMENTATION OF A SOFTWARE RADIO TESTSET FOR RESEARCH AND
LABORATORY INSTRUCTION
Except where reference is made to the work of others, the work described in this thesis is my own or was
done in collaboration with my advisory committee.
________________________________________
Fraidun Akhi
Certificate of Approval:
Victor P. Nelson
Professor
Electrical and Computer Engineering
Thaddeus A. Roppel, Chair
Associate Professor
Electrical and Computer Engineering
Stuart M. Wentworth
Associate Professor
Electrical and Computer Engineering
Stanley J. Reeves
Professor
Electrical and Computer Engineering
Stephen L. McFarland
Acting Dean, Graduate School
DESIGN AND IMPLEMENTATION OF A SOFTWARE RADIO TESTSET FOR RESEARCH AND
LABORATORY INSTRUCTION
Fraidun Akhi
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
October 30th, 2003
DESIGN AND IMPLEMENTATION OF A SOFTWARE RADIO TESTSET FOR RESEARCH AND
LABORATORY INSTRUCTION
Fraidun Akhi
Permission is granted to Auburn University to make copies of this thesis at its discretion, upon request of
individuals or institutions and at their expense. The author reserves all publication rights.
Signature of Author
Date
Copy sent to:
Name
Date
iii
THESIS ABSTRACT
DESIGN AND IMPLEMENTATION OF A SOFTWARE RADIO TESTSET FOR RESEARCH AND
LABORATORY INSTRUCTION
Fraidun Akhi
Master of Science, November 4, 2003
(B.E.E., Auburn University, 2001)
120 Typed Pages
Directed by Thaddeus A. Roppel
The rapidly evolving wireless communications environment, where standards are constantly created and
modified, has given rise to the software radio concept. This technology seeks to integrate as much of a
transceiver’s functionality into software as possible, thereby making it reconfigurable.
The potential
benefits of this concept are far-reaching. With the aid of software radio technology, wireless transceivers
will become more compact, power-efficient, and adaptive to new standards and environments.
Due to
these and other potential applications, much academic research interest is focused on the development of
software radio.
Software radios are still in the development stages. The ideal software radio, which automatically
digitizes a received radio frequency signal, is constrained by the absence of high-speed data converter
technology and sufficient processing power in low power microprocessors. Thus many physical software
radio systems used in academia and industry feature a RF front end.
The topic of this thesis is the design and implementation of a software radio system that implements a
direct sequence spread spectrum (DSSS) transceiver. This system features a super-heterodyne RF front end
that allows for RF testing and measurements to be made. The digital back-end features digital signal
processors that can be programmed with a vast array of signal processing algorithms. Therefore this
system will be ideal for an academic or research laboratory.
v
Style manual or journal used IEEE Transactions on Wireless Communications
Computer software used Microsoft Word 2000
vii
TABLE OF CONTENTS
LIST OF TABLES....…………...……………………………………………………………………………x
LIST OF FIGURES……………..…………………………………………………………………………..xi
1
INTRORDUCTION...………..…………………………………………………………………………1
1.1 Cellular Communications…….……………………...…………………………………………….1
1.2 Wireless Local Area Networks..……..………..………………………………………………….7
1.3 The Software Radio Concept…………..……………………………………………………….…8
1.4 Practical SDR Architecture..…..…………….…………………………………………………...10
2
BACKGROUND AND LITERATURE REVIEW.…………………………………………………..13
2.1
2.2
2.3
2.4
2.5
3
RF Front End Design Alternatives……………………………………………………………....13
Data Conversion Challenges………………….………………………………………………….16
Signal Processor Alternatives.…………..……………………………………………………….20
Military Software Radio Systems.……………..…………………………………………….......21
Software Radios in Academia.……………..………………………………………………….…24
SYSTEM FEATURES AND PARAMETERS.………………………………………………………26
3.1 RF Front End Architecture.……………………………………………………………………...26
3.1.1 RF2948b 2.4 GHz Spread Spectrum Transceiver………………………….………….…28
3.1.2 RF5117 1.8 GHz to 2.8 GHz Linear Power Amplifier…………………….………….….29
3.1.3 RF2494 High Frequency Low-Noise Amplifier / Mixer……………………………..…...30
3.1.4 SI4136 ISM Band RF Synthesizer……………………………………………………..…30
3.1.5 Linx Technologies λ/2 Dipole Antenna………………………………………………..…32
3.2 System Parameters…………………………………………………………………………….....33
3.2.1 Intermodulation………………………………………………………………………..….34
3.2.2 Sensitivity……………………………………………………………………………...….36
3.3 Digital Back-End Architecture.…………………………………………………………………..37
3.3.1 DSP Starter Kits…….………………………………………………………………….....38
3.3.2 Code Composer Studio………………………………………………………………...…40
4
EXPERIMENTAL TECHNIQUES AND RESULTS………………………………………………...41
4.1 DSP Algorithm Design………………..…………………………………………………….……41
4.2 Digital to Analog Converter……………..………………………………………………….……45
4.3 RF Front End Assembly and Testing Methods…………..……………………………………....46
4.4 RF Measurements………………………………………………………………..…………….…48
5
SOFTWARE RADIO DEVELOPMENT STATUS AND FUTURE OUTLOOK.………………….53
5.1 Progress Report…………………………………………………………………………………..53
5.2 System Enhancements…………………………………………………………………………....55
5.3 Concluding Remarks………………………………………………………………………….….57
A
SYSTEM SCHEMATICS…………………………………………………………………………….58
A.1 RF Transmitter………………………………………………….………………………………..58
A.2 RF Receiver…………………………………………………………….……………….……….60
viii
B
DSP CODE………………………………………………………………………………………….…61
B.1
B.2
B.3
B.4
TMS320C5416 Main Program………………….……………………………………………….61
TMS320C6711 Main Program...……..………………………………………………………….65
Input Data File Format……….…………………………………………………………………..72
DSP/BIOS Configuration Procedure.……………………………………………………………73
C
SOFTWARE RADIO BILL OF MATERIALS AND TOTAL COST ESTIMATE...………………74
D
DIRECT SEQUENCE SPREAD SPECTRUM………………………………………………………75
D.1 DSSS Basics…………….…………………………………………………………………….…75
D.2 PN Sequences……………………………………………………………………………………79
D.3 PN Synchronization……………………….……………………………………………………..84
D.3.1 The Digital Matched Filter……………….……………………………………………..86
D.3.2 Delay-Locked Loop……………………………….…………………………………….87
D.4 The RAKE Receiver……………………………………………….…………………………….88
E
DSSS BASEBAND TRANSCEIVER DESIGN IN VERILOG HDL …………………………...90
E.1
E.2
E.3
E.4
E.5
E.6
E.7
Dsss Transceiver Architecture…………………………………………………………………...90
Digital Matched Filter Implementation In Verilog Hdl……………………………….………....90
DMF Based Acquisition System………………………………………………………………....91
Delay-Locked Loop Based Tracking System…………………………………………………....92
Loop Filter………………………………………………………………………………….……94
Overall System...….……………………………………………………………………………...95
Simulation Results……………………..………………………………………………………..96
E.7.1 DMF Performance………………………………………………………………………..97
E.7.2 Performance Of The DLL…………………………………………………………….…..98
E.7.3 Overall System Performance…………………………………………………………….101
E.8 System Performance In The Presence Of Noise ……………………………………………….103
E.9 Conclusion....…….……………………………………………………………………………..104
E.10 Verilog Hdl Code..……..…...…………………………………………………………….……104
ix
LIST OF TABLES
3.1 RF Front end parameters...…......………………….………………………………...…………………36
C.1 Software radio bill of materials and project costs……...……………………………………………...74
x
LIST OF FIGURES
1.1 FDMA assigns a channel to each of the N users for the duration of their respective calls……….…….2
1.2 TDMA partitions each of the N channel into M time slots..........……………………………………….3
1.3 CDMA users with orthogonal spreading codes occupy the same wideband channel..........…………….4
1.4 The basis of DS spreading with XOR operations…….………………………………………………....5
1.5 Signal power spectral density before and after spreading....…..………………………………………..6
1.6 In an ideal software radio the RF front end is eliminated.…….………………………………………...9
1.7 Functional diagram of transmitter.……………………………………………………………………..12
1.8 Functional diagram of receiver...…..…………………………………………………………………..12
2.1 Super-Heterodyne receiver front end....….…………………………………………………………….14
2.2 Direct conversion receiver front end........……………………………………………………………...15
2.3 The low-IF receiver front end..…..…………………………………………………………………….15
2.4 Spectral reversals in terms of Nyquist zones…………………………………………………………..18
2.5 SPEAKeasy Phase II…………………………………………………………………………………...22
2.6 JTRS compliant radios from Raytheon...….…………………………………………………………...23
2.7 GA Tech.’s software radio platform…………………………………………………………………...24
2.8 Handy 21 handheld software radio from MIT………………………………………………………....25
3.1 RF front end design using the RFMD WLAN chipset………………………………………………....27
3.2 SI4136 Programmer interface…………………………………………………………………………..31
3.3 Third-order intermodulation product may fall within signal band...….………………………………..35
3.4 Third order intercept point……………………………………………………………………………..35
3.5 The DSK is connected to the transceiver unit through the MCBSPs....….……………………………37
3.6 TMS320C6711 DSP starter kit from Texas Instruments...….………………………………………....39
3.7 TMS320C5416 DSK board with THS10082 ADC daughter-card on top……………………………..39
4.1 A screenshot of CCS’s DSP/BIOS configuration menu........……………………………………….…42
xi
4.2 Master/Slave SPI interface between a transmitter/receiver pair……………………………………….43
4.3 The MCBSP operating in SPI mode, as viewed on a logic analyzer…………………………………..43
4.4 Data processing at the transmitter……………………………………………………………………...44
4.5 Data processing at the receiver...….…………………………………………………………………...44
4.6 Digital output from the DSP........……………………………………………………………………...45
4.7 DAC output when the input is a 40 KHz square wave………………………………………………....46
4.8 RF transmitter unit...….………………………………………………………………………………..47
4.9 RF receiver unit...….…………………………………………………………………………………...47
4.10 Spectrum of a narrowband QPSK signal……………………………………………………………....48
4.11 The signal of Figure 4.11 spread by a 16-bit PN sequence.…………………………………………...49
4.12 Transmitted power spectrum for TxVGC = 1.54V (upconverter gain = 2 dB)……….……………….50
4.13 Received power at ½ meter away……………………………………………………………………....51
4.14 Carrier power to that of the main side lobe...…..……………………………………………………...52
5.1 DSP testing with the Tektronix 1225 logic analyzer...….……………………………………………..54
5.2 Signals received through the RF link are displayed on the oscilloscope……………………………....55
A.1 RF transmitter front end.………………………………………………………………………………..59
A.2 RF receiver front end…………………………………………………………………………………...60
D.1. The basis of DS spreading with XOR operations……………………………………………………....75
D.2 Basic DS transmitter architecture...….………………………………………………………………....76
D.3 Signal power spectral density before and after spreading…….………………………………………...77
D.4 Narrowband interference rejection…….………………………………………………………………..77
D.5 Basic DS receiver architecture.………………………………………………………………………....78
D.6 Narrowband interference spreading...…..……………………………………………………………....79
D.7 Shift register m-sequence generator…….……………………………………………………………....82
D.8 Gold code sequence generator……………………………………………………………………….....83
D.9 Correlation of received signal to PN...…..……………………………………………………………...85
D.10 Typical digital matched filter…….……………………………………………………………………..86
D.11 Delay-locked loop....…………………………………………………………………………………....87
xii
D.12 A typical multipath environment..…..………………………………………………………………......88
D.13 RAKE receiver.………………………………………………………………………………………....89
E.1 Implementation of DMF………………………………………………………………………………..91
E.2 DMF based PN acquisition system...….………………………………………………………………..92
E.3 Delay-locked loop....…………………………………………………………………………………...93
E.4 Loop filter implementation.…...………………………………………………………………………..94
E.5 Impulse response of loop filter.………………………………………………………………………...99
E.6 Complete synchronization system.…..………………………………..……………………………......96
E.7 Comparison of simulation results of the DMF on Matlab (top) and Cadence (bottom)…………….....97
E.8 First instance of acquisition.…..…………………………………………………………………..…....98
E.9 One symbol period after Figure E.8...….…………………………………………………………..…..99
E.10 DLL locks when early and late branches output same correlation value...….………………………....99
E.11 Matlab simulation of the DLL..….…………………………………………………………………....100
E.12 S-curve derived from the Matlab (top) and Cadence (bottom) simulations..….……………………...101
E.13 System simulation on Cadence/Signalscan..…..……………………………………………………....102
E.14 System simulation on Veriloger...….………………………………………………………………....102
E.15 System noise performance..….………………………………………………………………………..103
xiii
CHAPTER 1
INTRODUCTION
The infusion of digital technology into wireless communication systems has given rise to the softwaredefined radio (SDR) concept (also known as "software radio")*, which seeks to incorporate as much of a
radio transceiver’s functionality into software as possible. This digitalization process promises to improve
system performance, flexibility, and cost efficiency. As a result, many educational institutions have placed
more emphasis on wireless research and instruction based on SDR infrastructures. Engineering curricula
that concentrate on wireless systems, such as Auburn University’s, include an undergraduate wireless
laboratory that seeks to introduce students to practical signal processing and radio-frequency (RF) design
and measurement principles. Graduate-research-level laboratories seek to build upon the knowledge of
modern wireless systems. The subject of this thesis is the design and implementation of an SDR system
that can form the foundation of an undergraduate wireless education or a graduate wireless research
laboratory.
This chapter begins with a brief introduction to the wireless communications industry. A primer on the
software radio concept and its potential applications follows. The chapter concludes with an overview of
the software radio system designed and implemented in the laboratory as part of this thesis work.
1.1
Cellular Communications
The first cellular systems were rolled out in the early 1980’s. As of September 2003, the number of
cellular phone users topped an estimated 1.3 billion people [17], roughly one out of every five people on
Earth. This number is expected to grow as cellular technology proliferates in developing countries in the
*
Software defined radio is used interchangeably with software radio, coined by Joe Mitola III of Motorola in 1991 [25]
1
2
years to come. The wireless local area network (WLAN) market is much younger than the cellular phone
market but has also seen dramatic growth. As of March 2003, the number of WLAN users in North
America topped 4.3 million people and is expected to surpass 31 million people by 2007 [16].
The first cellular phone system in the United States was the Advanced Mobile Phone System (AMPS),
deployed in 1983 by Ameritech. AMPS is an analog system using frequency modulation (FM) and relies
on frequency division multiple access (FDMA) to allow simultaneous service to multiple users. The
bandwidth allocation scheme used in FDMA is depicted in Figure 1.1. Each user in the system is allocated
a 30 KHz – wide channel for the duration of the call. Not shown in Figure 1.1 are the guard bands placed
Channel N
Channel 3
Channel 2
Channel 1
Time
Frequency
Figure 1.1 - FDMA assigns a channel to each of the N users for the duration of their respective calls
between channels to minimize spectral leakage from one channel into its neighboring channels. When an
FDMA channel is not in use, such as when there is a pause in a conversation, then it sits idle, thus wasting
bandwidth that could otherwise be used to support more users. After the assignment of a channel, the
mobile unit and the base station transmit and receive simultaneously using frequency division duplex
(FDD), thus battery life is short.
Nonlinearities in power amplifiers and combiners cause strong
intermodulation frequencies that have an especially adverse effect on FDMA systems, thus tight filtering is
required to minimize interference between the 30 KHz narrow channels. Mobile phones will experience
handoff problems since it is difficult to scan for one base station while constantly communicating with
another. Another obvious flaw of this system is its lack of security due to the fact that any eavesdropper or
3
jammer can compromise a call by simply tuning into the active frequency. In a nutshell, first generation
cellular systems (1G) such as AMPS are simple and low quality as compared to second- or third-generation
systems. Many of these systems are still in operation, but are slowly being phased out.
Second-generation cellular phone systems (2G) offer improvements in system capacity, security,
performance, and voice quality over 1G systems. 2G systems make heavy use of digital signal processing
and computer technology to achieve these improvements.
Time division multiple access (TDMA) is a
major 2G digital standard, proposed in the IS-54 and IS-136 standards.
Time
Channel N
Channel 3
Channel 2
Channel 1
Frequency
Figure 1.2 – TDMA partitions each of the N channel into M time slots
In a TDMA system each channel is shared between several users. Users are allotted non-overlapping and
cyclically repeating time slots. To provide a forward and reverse link, TDMA systems employ either time
division duplexing (TDD) or frequency division duplexing (FDD). In a TDD system, half of the slots in a
frame would be used for the forward link, and half for the reverse link. In an FDD system, separate
channels are used to implement the forward and reverse links.
The Global Systems for Mobile
Communication (GSM) standard is a popular TDMA/FDD system. This system uses 200 KHz wide
channels and Gaussian minimum shift keying (GMSK) modulation.
TDMA transmissions occur in bursts and are not continuous, thus battery life in these systems is much
longer than in FDMA systems. The discrete nature of the transmission also makes the handoff process
4
much easier because while the phone is idle it can scan for other base stations. Another advantage of
TDMA over FDMA is higher system capacity and transmission efficiency.
The wireless cellular standard most rapidly growing in popularity is code division multiple access
(CDMA), which was developed by Qualcomm Corporation and introduced in the IS-95 standard. As
shown in Figure 1.3, all users share a common wideband channel and are separated by orthogonal
spreading codes.
Code
Channel N
Channel 3
Channel 2
Channel 1
Frequency
Figure 1.3 – CDMA users with orthogonal spreading codes occupy the same wideband channel
CDMA owes its foundation to direct sequence spread spectrum (DSSS). The basic concept of DSSS
can be seen in Figure 1.4, where the data symbols, with period
PN (pseudo-random noise) sequence, with chip period
>>
TC .
TS , are modulo-two added (XORed) to the
TC , at the transmitter. It is necessary to have TS
5
State
TS
TC
1
Data Symbols
-1
1
PN Sequence
-1
1
Spread Sequence
-1
1
Copy of PN Sequence
-1
1
Recovered Data
-1
Time
Figure 1.4 – The basis of DS spreading with XOR operations
The desired receiver has an exact replica of the transmitter’s PN sequence, and if it is able to align the
PN codes correctly, a second modulo-two addition with the PN sequence will lead to the recovery of the
data symbols. The power spectral density of the transmitted symbol stream is thus spread by a factor
known as the processing gain (PG):
T
PG = 10 ⋅ log10  S
 TC



(1.1)
The spreading process is illustrated in Figure 1.5. A detailed introduction into DSSS theory and the design
of a baseband DSSS transceiver is contained in Appendix D.
6
U n s p re a d
S p re a d
− fC
− fS
fS
fC
Figure 1.5 - Signal power spectral density before and after spreading
In IS-95 CDMA systems, the bandwidth of the signal is increased (or spread) to 1.25 MHz by one of the
64 orthogonal Walsh codes.
Two of the Walsh codes (0 and 32) are used to spread the pilot and
synchronization channels, respectively.
Up to seven more Walsh codes are used to spread paging
channels, thus in one wide frequency band, up to 60 users can be accommodated simultaneously [7].
CDMA systems offer many advantages over analog and TDMA based systems. The mobile unit can
communicate with two different base stations simultaneously, thus soft handoffs are possible and the
probability of calls being dropped is reduced.
Higher user capacity and data rates are other major
advantages of CDMA based systems.
A major hindrance faced by CDMA is what is known as the “near-far” problem. Mobile units close to
the base station tend to interfere excessively with those far away, even though their respective spreading
codes are orthogonal.
To mitigate this adverse effect, CDMA employs sophisticated power control
functions to dynamically increase the transmission power of the mobile as it moves farther away from the
base station, or lower its transmission power as it moves closer.
Third-generation cellular phone systems (3G) are envisaged to offer higher data rates, enhanced
multimedia features, and better spectral efficiency over 2G systems. Some of the leading 3G technologies
are CDMA-based standards such as wideband CDMA (WCDMA) proposed by the Universal Mobile
Telecommunications System, and CDMA2000 proposed by Qualcomm Corporation. The deployment of
these systems has been slow due in part to the high migration costs. This is especially true for GSM-based
2G systems, which hold around 74% of the market share [22]. These systems incur great overhead costs in
their migration to CDMA-based 3G systems. The overhead includes expensive wideband 3G licenses and
7
equipment overhauls. For example, Vodafone Airtouch paid $8 billion for a 3G license in the UK. A basic
general packet radio service (GPRS) upgrade to a GSM network would cost only $1 million [11]. This has
lead to the popularity of 2.5G systems such as GPRS.
These systems offer enhancements over their 2G
predecessors in terms of performance and service, and are economically feasible.
1.2 Wireless Local Area Networks
In recent years wireless local area networks (WLANs) have gained much popularity due to their
increasing performance. The IEEE 802.11b standard offers 11 Mb/s (mega bits per second) of throughput,
while the orthogonal frequency division multiplexing (OFDM) based 802.11a and 802.11g standards offer
54 Mb/s.
These rates are comparable to wire-line Ethernet rates. Beside the obvious advantage of
convenience, WLANs have a big advantage over wire-line networks with respect to cost.
WLANs
eliminate the cabling cost and the labor costs associated with the installation and troubleshooting of cabled
networks.
A major hindrance to the long-term success of many of the current WLAN standards is the issue of
security.
Currently, heavy encryption is applied to wireless data in order to maximize its integrity.
However, encryption adds redundancy to the data stream and thus cuts down on throughput. In part, this
has lead to the introduction of WLAN technologies such as ultra wideband (UWB). These systems
modulate the phase of a discrete pulse train, rather than the phase of a carrier with the outgoing data.
Similar to DSSS, UWB uses spreading codes to spread the bandwidth of the transmitted data. The
bandwidth of such a transmission is theoretically close to infinity and thus the power spectral density of the
signal is very close to the noise floor [39]. The data rate of these systems is projected to be in the range of
100 Mbps.
Similar to the cellular phone industry, the WLAN industry is also rapidly evolving with respect to
standards and technologies. Thus, the issue of overhead associated with migration also comes into play in
this environment. The software radio approach discussed next has the potential to drastically reduce these
overhead costs, meanwhile improving system performance and adding useful system features.
8
1.3 The Software Radio Concept
Prior to the proliferation of digital signal processing technology in radio systems most transceiver
functions were implemented in analog circuitry. This confined the capabilities of the transceiver to the
limitations of the analog technology. Some complex communications algorithms were simply impossible
to implement with analog components for a given project budget. Since analog circuitry is specified for a
certain function it is difficult to multitask, thus analog systems tend to be physically large and power
hungry.
Although it is true that in some applications such as filtering, it can outperform its digital
counterpart, an analog system’s performance is jeopardized by environmental variations.
Digital signal processors (DSPs), field programmable gate arrays (FPGAs), and microprocessors allow
analog circuits such as filters, equalizers, and phase-locked loops (PLL) to be packed into one chip,
consuming a fraction of the power, area, and cost. This has led to the implementation of sophisticated
signal processing algorithms such as convolutional encoding, interleaving, and dynamic power control in
small hand-held devices such as cellular phones.
Today’s transceivers consist of a radio-frequency (RF) front end, and a baseband processing section.
The RF front-end is a loose term referring to the analog circuitry between the antenna and the data
converters. The main functions of the RF front end are to modulate and demodulate the carrier with and
from the data, respectively.
Baseband signal processing, voice processing, user interface, power
management, and networking functions are done by a combination of analog and digital chips. Mixed
signal (analog and digital) chip design, which would allow the integration of many of the current analog
and digital functionalities into one chip, is a popular concept in today’s wireless industry.
Texas
Instruments for example, has announced that by 2004 it will introduce a one-chip GSM phone [7].
Software radio strives to pack as much of the transceiver’s functionality into a programmable signal
processor as possible. A block diagram of an ideal software radio is shown in Figure 1.6 where the data
converters are placed very close to the antenna.
9
Microphone Speaker
DSP Unit
ADC
Display
DDS
Baseband
Processing
BPF
1 2 3
4
5 6
7 8 9
DAC
* 0 #
Figure 1.6 – In an ideal software radio the RF front end is eliminated
In this system, the RF front end is eliminated and the DSP is tasked with the modulation and
demodulation, in addition to the baseband signal processing. Thus, if the DSP is programmable, the
characteristics of the radio can be significantly defined by the software that it runs on. A designer can alter
the performance of the radio simply by reprogramming the DSP.
This concept has far-reaching implications in the wireless communications industry. Base station
transceiver equipment at cell sites will no longer become obsolete with changes in wireless standards.
Thus, migration to newer and more powerful systems will be inexpensive. Wireless switches, access
points, and routers will no longer have to be replaced with system upgrades, but reprogrammed. Satellites
and other spacecraft can be reprogrammed from Earth to alter their transmission and reception
characteristics, thus making them more powerful and flexible.
Interoperability is another potential benefit of software radio systems.
Different wireless
communication systems operating on different standards can communicate with each other. This has been
a major focus of the US military because different battlefield units use different communication systems.
Software radios can drastically reduce time to market because software modifications can be done at a
fraction of the time of hardware modifications. Complex 3G handsets take many months to design and
implement. Any errors in this process can lead to a delay of many months for the product to reach market.
Software radio systems cut down this correction time significantly.
10
New software features and upgrades can be downloaded to the handset automatically or on demand,
thus greatly enhancing the degree and quality of services available to cellular customers. Handsets will not
become obsolete as often as they do now with changing standards, thus saving customers money.
Signal
processing
algorithms
such
as
filtering,
encoding/decoding,
equalization,
and
modulation/demodulation can be adaptively altered remotely. For example, in current CDMA systems the
base station controls the power emissions of the handsets to minimize the near-far effects, as well as multiuser interference. This can be applied to all parameters of the handset, and as a result, transmission quality
and capacity can increase. The concept of “cognitive radio”, which seeks to make radio systems intelligent
and adaptive to their environments, is a future goal for software radios.
1.4 Practical SDR Architecture
The main limiting factor in software radio implementation is the sluggish progress in data conversion
technology. This has not matured to the point where the system of Figure 1.6 can be implemented. Ref.
[24] relates ADC power consumption (P in Watts), bit resolution (R in bits), and sampling frequency
fS
(in Hertz) by a figure of merit (FoM in J/conversion):
FoM =
2R fS
P
Thus for a given FoM, increases in either R or
(1.2)
f S result in higher power consumption. Ten-bit resolution
can currently be realized at only 2 GHz or so, at a power consumption of 4.6 W [46], which is high for
handset applications. For operation at 2.4 GHz, the ADC sampling rates would have to exceed 10 GHz at a
fairly good resolution and with low power consumption. The fastest twelve-bit digital to analog converters
on the market today can output a maximum frequency of around 333 MHz, at power consumption levels of
1.9 W [35].
11
As the ADC moves closer to the antenna, more samples will flood into the processors for processing,
thus DSP performance must increase in order to make the software radio concept realizable. According to
[8] the requirement for signal processing is rising at least 10 times faster than Moore’s Law can deliver
increased processor performance, due to the increased complexity of signal processing algorithms. This
means that base station transceivers must use multi-processor motherboards to perform their tasks.
Wireless handsets face the additional limitation of battery life. Processors on wireless handsets must be
low power in order for the battery to last a reasonable amount of time.
As a result of these constraints, practical software radios must include an RF front end so as to lower
the requirements placed on the data converters and digital signal processors. One big constraint placed on a
software radio system that includes an RF front end is the static bandwidths of the RF components such as
the power amplifier (PA) or low noise amplifier (LNA). Thus rather than being host to a wide range of
wireless standards, today’s practical software radio systems support only a selection of similar standards.
For example the software radio designed as part of this thesis can serve as an 802.11b WLAN, a nonstandard DSSS, or a narrowband phase-shift keying (PSK) transceiver.
This thesis outlines the design of a software radio system employing a super-heterodyne RF front end
and a DSP-based digital back end. A baseband receiver design was also done in Verilog HDL and is
discussed in Appendix D. The system, depicted in Figures 1.7 and 1.8, is implemented with RF Micro
Devices’ 802.11b WLAN chipset.
This includes a quadrature phase shift keying (QPSK)
modulator/demodulator (RF2948B), an LNA/mixer (RF2494), and a power amplifier (RF5117), all
designed for operation in the 2.4 GHz license-free ISM band. The RF front end is described in detail in
Chapter 3.
12
PC
RF2948B EVB
DSP
DAC
LPF
RF5117 EVB
LPF
PA
BPF
TMS320C5416 DSK
RF
SI4136 EVM
IF
Figure 1.7 – Functional diagram of transmitter
PC
RF2494 EVB
BPF
RF2948B EVB
LPF
LNA
LPF
ADC
DSP
TMS320C6711 DSK
RF
SI4136 EVM
IF
Figure 1.8 – Functional diagram of receiver
The DSP transmits data in the form of a serial bit stream out of its serial port to a digital to analog
converter (DAC) circuit, as shown in Figure 1.7. This circuit is designed to condition the signal so as to
make it suitable for input into the RF unit. In Figure 1.8, the analog to digital converter circuit conditions
the output of the RF receiver so as to make it suitable for input into the serial port of the DSP.
As will be discussed later, one benefit of this system is that it allows the measurement of the RF
characteristics of its individual components or of the system as a whole. Furthermore, the signal processing
algorithm can be modified at ease, and its performance tested. Thus it serves as an excellent test-bed for a
research and education laboratory.
CHAPTER 2
BACKGROUND AND LITERATURE REVIEW
As suggested in [8], radio systems can be classified into tiers by their degree of software integration.
Tier 0 includes all traditional analog radio systems with no software element. Tier 1 consists of systems
with some software control over hardware components. Tier 2 systems include extensive signal processing
functionality in software, as well as an RF front end. Tier 3 systems are similar to the ideal software radio,
with total software programmability. Tier 4 systems are future systems that could be cognitive, and multistandard. For a system to be classified as a software radio, it must be tier 2 or higher. As we will see in
this chapter, almost all software radio systems discussed in the literature are tier 2 systems, in large part due
to the shortfall in data converter technology and processing power.
This chapter will present some of the design alternatives available in the software radio realm. The goal
is to discuss some of the practical issues involved in software radios.
Most of the mathematical
conceptualization will be left for the following chapter.
2.1
RF Front End Design Alternatives
There are three main RF front end architectures in popular use today. These are superheterodyne, direct conversion (or zero IF), and low IF. The super-heterodyne receiver is
a traditional design that has passed the test of time. As shown in Figure 2.1, a received
message carrying RF signal is down-converted (or mixed down) to baseband in multiple
stages.
13
14
RF BPF
IF BPF
LPF
LNA
ADC
f RF
f IF
Figure 2.1 – Super-Heterodyne receiver front end
The message carrier signal is received by the antenna and band limited by the band-pass filter (BPF)
before being amplified by the low-noise amplifier (LNA) and mixed down to an intermediate frequency
(IF). The signal is then filtered to isolate the message carrying IF carrier (
the images at (
convert
f IF ) at ( f C - f RF ) and reject
f C ± n f IF ), where n is an integer greater than zero. This procedure is repeated to down-
f IF to baseband.
Super-heterodynes offer high performance and few design difficulties. Down-conversion in more than
one stage means that the RF local oscillator is at a different frequency from the incoming carrier, and thus
interference due to leakage is not an issue. This also means that the oscillators and mixers can be rated at
lower frequencies than the carrier. Thus super-heterodynes are low risk and low power designs. This front
end design is high in performance, but has some downsides. It requires a large number of components (at
least two mixers, two oscillators, and two filters) and results in bulkier circuitry. In software radio design,
perhaps the least attractive aspect of the super-heterodyne receiver is that it subjects the incoming signal to
the bandwidth limitations of all of its components. Thus these systems are not as attractive for wideband
communications systems such as WCDMA.
Direct conversion, or zero-IF architectures eliminate all but one of the down-conversion stages of the
super-heterodyne. As shown in Figure 2.2, the message carrying RF signal is directly down-converted to
baseband.
15
RF BPF
LPF
LNA
ADC
fC
Figure 2.2 – Direct conversion receiver front end
The advantages of this design are the obvious cost savings in components, and compactness of design.
Image-rejection is not as important an issue in these designs because the image frequencies occur far away
from baseband. There are however serious challenges faced by this architecture. The local oscillator,
operating at the carrier frequency
f C , self-mixes to cause dc offset at the output of the mixer. In
quadrature transceivers with in-phase (I) and quadrature (Q) channels, achieving I/Q balance at RF is
difficult. Leakage from the local oscillator can radiate out of the antenna and thus interfere with the
incoming message carrying signal. Furthermore, as we will discuss in the next chapter, direct conversion
systems are more susceptible to second order intermodulation distortion.
A compromise between super-heterodyne and direct conversion architectures is the low-IF design
shown in Figure 3.
This design eliminates some of the analog components by transferring their
functionality to the digital domain.
A digital signal processor can perform their duties in software.
Another advantage of this design is that the DC-offset problem faced by the direct conversion receiver is
not an issue.
Digital demodulation
RF BPF
IF BPF
LNA
LPF
ADC
f RF
Figure 2.3 – The low-IF receiver front end
f IF
16
The drawbacks to low-IF designs are that a high performance ADC is required, and also the power
consumption is somewhat higher than that of super-heterodyne.
Although we have only discussed the receiver portions of the three popular front end architectures, the
same principles apply to their transmitter portions.
For example: a super-heterodyne transmitter up-
converts the baseband message signal to RF in more than one stage. A direct conversion transmitter does
so in just one stage, and the low-IF transmitter does so in more than one stage, some in the digital domain.
Of the three main RF front ends discussed, the low-IF design is the most common in modern software
radios, such as in [40, 49, 10, 36,15,18,24], because it gives the software the greatest degree of control over
system parameters, given the current state of technology.
The choice of IF frequency has important implications for any front end design. A high IF leads to
good image rejection by the IF BPF, but adjacent channel interference (ACI) attenuation is poor. A very
low IF leads to good ACI, but image rejection is poor. The design in ref. [40] uses an 11 MHz IF, while
that in ref. [21] uses a 70 MHz IF.
RF front ends suitable for software radios must have wide bandwidths. In other words they must be
able to accommodate a large range of frequencies. The same principle applies to antennas used for
software radio designs. Due to the difficulties in the design of multi-mode antennas and wideband RF front
ends many designs such as those discussed in ref.’s [27] and [31] follow a modular approach whereby a
number of antennas and RF front end modules are used to cover the entire operating spectrum.
2.2 Data Conversion Challenges
The Nyquist theorem states that in order to replicate an analog signal in the digital domain, it must be
sampled at no less than twice the frequency of its highest frequency component.
Software radio
applications have made it necessary to sample at much higher speeds than the current generation of analog
to digital converters allow, as was discussed in the previous chapter.
Therefore, new techniques are being developed in order to work around this sampling frequency deficit.
One popular technique used in analog to digital conversion is known as “subsampling” or “bandpass
17
sampling” [21], which seeks to sample at twice the information bandwidth, rather than the carrier
frequency. This technique, used in [21], intentionally aliases the incoming IF signal and generates samples
its image near baseband. For example, in a low-IF front end, a 100 MHz
80 MHz would result in an image
f im = f IF mod(
f IF signal sampled at an f S of
f im at 20 MHz according to:
fS
)
2
Thus instead of requiring an ADC with a sampling frequency at the Nyquist rate of at least
(2.1)
2 f IF or 200
MHz, subsampling allows an ADC with a sampling rate of just 80 MHz. The lower output rate from the
ADC provides the added benefit of reducing the load of the signal processor that would be used for the
downconversion to baseband in the digital domain.
The design in ref. [3] applies the subsampling technique to a direct digitization GPS receiver. A
modulated RF carrier at 1.577 GHz is amplified and bandpass filtered before being sampled at 20 MHz by
an ADC. The ADC output is the digitized image of the signal at 3 MHz. Thus the information bandwidth
is translated to baseband without the need for a local oscillator, mixer, or image filter.
As shown in ref. [4], the sampling spectrum can be divided into many zones, known as
”Nyquist zones.” This concept is displayed in Figure 2.4, where any signal that resides within the first
Nyquist zone meets the Nyquist criterion. However, the same is true for signals that reside in the second
Nyquist zone. This pattern continues for each multiple of one half of the sampling rate. In subsampling, in
addition to downconverting the sampled spectrum, signals placed in even Nyquist zones become spectrally
inverted. Although this is usually not a problem, it can be useful to reverse a previously inverted spectrum
as may occur in the first downconversion mixer.
18
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
zone
zone
zone
zone
fS / 2
DC
fS
3 fS / 2
5th Nyquist
zone
2 fS
5 fS / 2
Figure 2.4 – Spectral reversals in terms of Nyquist zones
From Figure 2.4 it can also be deduced that an extremely high Q band-pass filtering must precede
subsampling. This is due to the fact that all noise and interfering signals from DC to the input bandwidth
of the ADC will alias into the resulting passband. Another limitation placed on subsampling is that the
ADC bandwidth must accommodate the incoming carrier frequency. The higher the carrier frequency, the
steeper the band-pass filter rolloff.
As discussed in ref. [3], there are also restrictions placed on the sampling frequency so that the signal
spectrum doesn’t fold onto itself. For an input signal that occupies a signal bandwidth from
f L to f L +B,
the sampling frequency has the following lower bound:
fS ≥
fL
)B
B
f
int( L )
B
2(1 +
(2.2)
With current sampling technology, subsampling at wide RF bands is difficult, and requires an increased
sampling rate. Thus most subsampling systems operate in the IF stage.
19
The major challenge in ADC design is that of designing and building low power wideband converters
able to convert bandwidths of 10 to 30 MHz centered at sampling frequencies of 3 to 4 GHz while
guaranteeing a resolution of 16 bits in order to satisfy dynamic range requirements of most transmission
standards [12].
In general, ADC performance begins to degrade with increasing input frequency. There
are two primary areas of performance limitations. The first performance limitation is the slew rate of the
on-chip analog circuitry.
An important goal in the design of ADCs is that of obtaining Spurious Free
Dynamic Range (SFDR).
SFDRmin = 10 log
PB
+ SNRmin
PX
The SFDR of a system with a desired input signal of power
(2.3)
PX , and a blocking signal of power PB ,
can be calculated by (2.1). For example, in order to comply with the GSM standard, a receiver must be
able to distinguish a blocking signal with power 85 dB above the desired signal, where the two signals are 8
GSM channels, or 1.6 MHz apart. Different standards require different minimum SFDR values. The GSM
standard requires
SFDRmin to be around 10 dB while GPS systems require a SFDRmin in the range of 6-
12 dB [49].
The second limitation of ADC performance is from jitter in the sampling clock. This factor results in a
lower SNR. A technology that is making inroads in this field is delay-insensitive logic (DIL) as described
in [6]. DIL seeks to eliminate the clock tree from mixed-signal circuitry. This will potentially solve the
clock jitter problem in ADCs.
Digital to analog converter (DAC) technology is not as limiting a factor in software radio development
as is ADC technology for a number of reasons. DACs are used in wireless transmitters, which are not as
sensitive as receivers because of the much larger SNR. The fastest DACs on the market have operating
ranges close to 800 MHz, and are suitable for handset applications [48].
This operating frequency
surpasses the ability of the current low-power signal processors to overload the DAC.
20
2.3 Signal Processor Alternatives
Digital signal processing in wireless systems is done by three main categories of chips: application
specific integrated circuits (ASIC), digital signal processors (DSP), and field programmable gate arrays
(FPGA). A fairly detailed analysis of the tradeoffs between these three processor types is presented in [2].
ASICs are circuits optimally designed to accomplish specific tasks at high performance levels. They
are unrivaled in speed, power efficiency, and computational density. These chips can be found in anything
from base stations to handsets, performing a wide range of signal processing duties. Due to their high
design and production costs, ASICs are usually used in high volume designs. ASICs are not reconfigurable
thus they are mainly used for the implementation of static functions, such as spectrum spreading in CDMAbased software radios. The role of ASICs in future software radios will be limited to standard-independent
static functions.
FPGAs are programmable logic chips that were initially intended for ASIC prototyping. They consist
of a collection of logic gates that can be used to assemble a digital circuit by opening and closing switches
in the appropriate locations. Due to their programmability and increasing density (millions of gates per
chip) [9], they have gained popularity in wireless applications. Although their unit costs are very high, they
are often a cost effective alternative to ASICs in low volume designs, and have much shorter times to
market.
The hardware description language program (such as VHDL or Verilog) that specifies the circuit is used
by synthesis software to create a list of interconnections, known as a “netlist.” The netlist is then used by
place and route software to map the design to the particular FPGA resources. Logic blocks in the map are
then assigned to specific locations in the FPGA. The interconnections between logic blocks are then
routed. Finally the place and route software generates a bitmap file for configuring the FPGA. In-circuit
programming of RAM-based FPGA’s can be performed in a matter of microseconds. Drawbacks to FPGA
design are the severe learning curves involved in implementing efficient signal processing functions, and
also the immaturity of design tools for FPGA-based signal processing designs. To overcome this problem,
manufacturers such as Xilinx have created innovative designs such as the Virtex II FPGA, which has an
embedded PowerPC microprocessor. Thus static functions can be performed in optimized logic circuits,
21
while dynamic ones are done on the microprocessor. FPGA manufacturers such as Xilinx and Altera try to
make FPGAs an attractive choice for communication applications by providing vast libraries of macros and
optimized logic circuits and reference designs.
DSPs are general-purpose microprocessors with optimized instruction sets for signal processing
applications. These are commercial off-the-shelf components that have moderate unit costs, but have very
short times to market. DSP programs can be written with popular programming languages such as C and
C++, thus development skill levels do not have to be as high as for FPGA programming.
DSPs are seen as the processing power behind future software radios because of their optimized
instruction sets and real-time configurability. Although DSPs lack the gigabit per second interface speeds
of FPGAs, they have been increasing in clock speed, on-chip memory, and complexity. Today’s top of the
line DSPs are as fast as 720 MHz, with 32-bit wide busses, and 5700 MIPS (million instructions per
second) [44]. In addition to a wealth of optimized functions geared toward signal processing applications,
many DSPs include optimized co-processors dedicated to popular communication algorithms such as the
Viterbi decoder.
The interest in software radio technology has led some DSP manufacturers to produce software radio
specific DSPs. Sandbridge Technologies, for example, has produced the Sandblaster DSP, which includes
software support for multiple wireless standards such as WCDMA, GPRS, and 802.11b [37].
Thus
operation modes can be switched from one standard to the next with ease. The Sandblaster is also
optimized for power efficiency and speed.
2.4 Military Software Radio Systems
The SPEAKeasy project began in early 1991 as a Department of Defense effort to build a multi-band,
multi-mode radio system. The inspiration behind this project was the lack of compatibility of wireless
radio systems within the branches of the military. SPEAKeasy would be able to operate from 2 MHz to 2
GHz. It would communicate simultaneously with any combination of 4 common military radios systems,
one GPS satellite, and one cellular base station. It would be compact and designed with commercial offthe-shelf components. Its software and hardware components would be adaptable to new technologies. Its
22
performance in multi-path environments would be excellent. Furthermore, it would improve on the antijamming and interference rejection capabilities of conventional radio systems.
The first phase of the project (1992-1995) produced a 6-ft tall rack mounted radio complemented with a
Sun workstation for user interface. The radio consisted of modules that could be plugged into a VME
(Versa-Module Eurocard) bus during operation. The wide operating range of 2 MHz to 2 GHz couldn’t be
accommodated by a single RF front end with the available technology. Thus it was divided into three
bands, 2 MHz to 30 MHz, 30 MHz to 400 MHz, and 400 MHz to 2 GHz, and a low-IF RF front end was
designed for each. The digital signal processing was done on a quad TMS320C40 16-bit DSP embedded
module from Texas Instruments (TI). The final product demonstrated in 1994 only operated in the 30 MHz
to 400 MHz band, but met most of its other functional requirements. Modules for wideband modulation
schemes such as frequency hopping spread spectrum, and narrowband schemes such as single sideband
AM, were demonstrated successfully. However SPEAKeasy left a lot to be desired in terms of ergonomics
and ease of use.
The second phase of the SPEAKeasy project (1995-1999) produced a 0.4 cubic feet, 30 pounds [27]
radio shown in Figure 2.5:
Figure 2.5 – SPEAKeasy Phase II [41]
This system was based on a PCI (Peripheral Component Interconnect) bus interface. User interface is
provided through a PDA (personal digital assistant) type device. The signal processing was done using a
combination of DSPs, and for the first time in radio systems, FPGAs. A separate microprocessor was used
for data security. The RF front end was based on a low-IF architecture, and accommodated the 4 MHz to
400 MHz frequency range. The main drawback to this system was that it only handled narrowband
23
modulation schemes. SPEAKeasy phase II was supposed to be a four-year project, but after only fifteen
months it had made the aforementioned progress. The DoD was satisfied with the achievements of the
project enough to stop further development and go into production [8].
The joint tactical radio system (JTRS) is an evolving standard adopted by the Department of Defense in
order to make all radio systems within the US military interoperable. JTRS systems build on the legacy of
SPEAKeasy projects. Although these systems are still tier-2 software radios, they are the cutting edge in
software radio technology.
Figure 2.6 – JTRS compliant radios from Raytheon [33]
24
JTRS compliant radios from Raytheon, shown in Figure 2.6, feature operational capability in the 2 MHz
to 2 GHz range with different sets of interchangeable modules. Low-IF front ends support a host of
narrowband and wideband modulation schemes. Operation is possible on up to four simultaneous bands.
Processing power is provided by a combination of DSPs, FPGAs, and Pentium class microprocessors [13].
2.5
Software Radios in Academia
Software radio research is being pursued not only in industry and the military, but also in academia.
Two such software radio programs are at the Georgia Institute of Technology (Georgia Tech), and the
Massachusetts Institute of Technology (MIT).
The software radio laboratory at Georgia Tech features low-IF front ends with bandwidths of 40 MHz.
Signal processing is done by quad-TMS320C6701 floating point DSP modules. IF signal processing is
done by a combination of wideband ADCs and FPGAs.
Figure 2.7 – GA Tech.’s software radio platform [31]
Georgia Tech’s software radio has the capability of demodulating OFDM, BPSK, QPSK, and QAM
(quadrature amplitude modulation) signals, thus it has the capability of supporting all of the IEEE 802.11
standards.
25
The Handy 21 (H21) handheld software radio by MIT’s Laboratory for Computer Science is a powerful
handheld computer that combines the functions of a cellular phone, a wireless connection to the Internet, a
pager, an AM/FM radio and a television set. At the heart of the H21 device, shown in Figure 2.8, is the
RAW (reconfigurable architecture workstation) microprocessor, an MIT research project that seeks to
minimize wire delay in conventional microprocessors.
Figure 2.8 – Handy 21 handheld software radio from MIT
It does this by using a tiled architecture where several simpler processors and their essential peripherals are
distributed across the chip. The aim is to confine the delay of data from any point on the chip to another, to
one clock cycle. RAW opens the microprocessor components to be routed by the software compiler to
maximize performance for any application. These processors are expected to see use in future software
radio architectures due to their potential superior processing power, and reconfigurability.
CHAPTER 3
SYSTEM FEATURES AND PARAMETERS
In this chapter we discuss the software radio designed as part of this thesis, and its theoretical
capabilities. The RF Micro Devices (RFMD) WLAN chipset that forms the backbone of the RF front end
is discussed in detail. This is followed by a discussion of the Texas Instruments digital signal processors
and their role in this system. The chapter will conclude with an overall system assessment. Testing and
measurement results are presented in the following chapter.
3.1
RF Front End Architecture
The RF front end is based on the super-heterodyne architecture with two upconversion and
downconversion stages, as shown in Figure 3.1. RFMD’s WLAN chipset is geared toward the IEEE
802.11b direct sequence spread spectrum market. Thus many of the front end components have fairly wide
bandwidths. The chipset includes the RF2948b QPSK (quadrature phase-shift keying) modem, the RF5117
RF power amplifier, the RF2494 LNA/mixer, and the RF3000 baseband processor, which is not utilized at
this stage of the project. We will analyze the front end with a step-by-step description of the modulation,
transmission, and demodulation of the in-phase (I) and quadrature (Q) input data signals. These signals are
usually the outputs of a digital to analog converter with proper peak-to-peak amplitude and DC bias.
The RF front end was assembled using evaluation boards of the various front end components, as
shown in the system schematic in Appendix A. The manufacturers of each of the components have
provided the circuit schematics and bill of materials for their evaluation boards. These evaluation boards
are reference designs that are intended to assist system designers with proper board layout and component
interfacing.
26
1/2 wave
2.4 GHz
dipole
antenna
RF2436
PCBA
2.442 GHz Tx / Rx
Switch
BPF
2.442 GHz
PA
RF5117 PCBA
SI4136 EVM
RF
Dual PLL
LO
Frequncy
Synthesizer IF
LO
LNA
BPF
748 MHz
2.068 GHz
Rx
BPF
Tx
Tx
Rx
2.442 GHz
PA
driver
374 MHz
SAW
BPF
IF
Amp
IF
Amp
Tx VGC
RF2948b PCBA
Figure 3.1 - RF front-end design using the RFMD WLAN chipset
Gain
Select
RF2494 PCBA
Rx VGC
LPF
LPF
Baseband
Amp / LPF
Q
in
I
in
Q
out
I
out
27
28
Nonlinearities in RF front end components such as amplifiers and mixers can cause strong frequency
harmonics to appear which in turn leads to gain compression, where small signal gain characteristics are
altered. Gain compression can lead to desensitization, where a weak received signal experiences reduced
gain in the presence of a strong interfere. Another result of a strong interferer in the presence of a small
desired signal is cross modulation, where noise from the interferer modulates the desired signal. Another
problem caused by nonlinearities is intermodulation. In intermodulation, when two out-of-band interfering
signals with different frequencies are applied to a nonlinear system, interfering components that are not
necessarily harmonics of the interferers result in the passband of the desired signal. The derivation of these
and other RF front end design parameters is presented in detail by [42]. In this thesis we will focus on the
calculation of system parameters rather than the derivation of component parameters.
3.1.1
RF2948b 2.4 GHz Spread Spectrum Transceiver
The RF2948B is an ASIC designed for QPSK systems operating in the 2.4-2.483 GHz license-free ISM
band. The transmitter has two inputs, one for the I-channel, and another for the Q-channel. The baseband
data streams that enter through here are band limited and pulse shaped by 5-pole low-pass Bessel filters.
From Figure 3.1 it can be seen that the IF signal is phase-shifted ±45°, prior to modulation. Thus the IF
signal that mixes with the data from the I-channel is 90° out of phase with the IF signal that mixes with the
data signal from the Q-channel. Therefore according to [28] the modulated signal
π

 A cos(2πf IF t + 4 )

3π
 A cos(2πf IF t + )

4
S IF (t ) = 
5π
 A cos(2πf IF t + )
4

π
7

 A cos(2πf IF t + 4 )
S IF (t ) is defined by:
for binary 10
for binary 11
for binary 01
for binary 00
(3.1)
29
Two binary bits can be packed into one symbol, thus the efficiency of QPSK is twice that of binary phaseshift keying (BPSK). Furthermore, in an additive white Gaussian noise (AWGN) channel, the average
probability of error for QPSK and BPSK are identical [32]. Thus QPSK and its variations have gained
popularity in wireless standards such as CDMA.
The RF2948b’s modulator accepts a wide range of IF frequencies (45 MHz to 500 MHz) but the
nominal value is 374 MHz. After upconversion to the IF frequency, the two channels are combined and
their sum is filtered by a surface acoustic wave (SAW) band-pass filter centered at 374 MHz, with a 3-dB
bandwidth of 20 MHz. The off-chip SAW filter performs the image rejection and band limiting on the
modulated IF signal. SAW filters have steeper skirts than do ceramic filters, and thus are desirable.
Automatic gain control on the transmitter can be performed through the transmit voltage gain control (Tx
VGC) setting. The gain of the IF amplifier can be as high as a nominal value of 17 dB.
Upon amplification, the IF message carrying signal is upconverted to the ISM band by mixing with an
RF carrier. At operation at nominal values, the RF signal is -6 dBm of power. It is then sent through an
off-chip bandpass filter for image rejection. This filter has an insertion loss as high as 4 dB, thus its output
power is –10 dBm. A power amplifier with a gain of 10 dB is then used to amplify the signal before it is
output. For low-power applications, this power amplifier can be used to drive an antenna with 50 ohms of
input impedance. In such a case, the RF2948b’s power amplifier output power can be as high as 6 dBm.
The receiver circuitry reuses the SAW filter of the transmitter to filter the signal directly after
downconversion to IF. This modulated IF signal is then amplified by a variable gain IF amplifier, which
can be controlled by an AGC circuit. The IF carrier is then demodulated into its baseband I/Q components
by mixing with replicas of the IF signals used at the transmitter. The baseband signals are then filtered by
low-pass filters and amplified to 700 mV peak-to-peak before being output.
3.1.2
RF5117 1.8 GHz to 2.8 GHz Linear Power Amplifier
The RF5117 is a wideband linear RF power amplifier designed for operation in the PCS (personal
communication services) band of 1.85 GHz to 1.91 GHz and the ISM band. The maximum small signal
30
gain is specified as 26 dB in the ISM band. This part outputs a maximum of 27 dBm of power, which
translates into 501 mW according to:
PmW = 10PdBm /10
(3.2)
Under the FCC’s (Federal Communications Commission) Part 15 rules governing the operation of
unlicensed radios in the ISM band, spread spectrum systems can transmit up to 1 Watt of power [32].
Therefore the transmitter’s radiation emissions are well within the FCC guidelines.
3.1.3
RF2494 High Frequency Low-Noise Amplifier / Mixer
The RF2494 contains a low-noise amplifier (LNA) and mixer used in the ISM band receiver front end. The
LNA includes a common-emitter amplifier with a gain of 13 dB followed by an attenuator which has a
selectable insertion loss of 3 dB (high-gain mode) or 17 dB (low-gain mode).
The output of the attenuator is passed through a band-pass filter for band limiting, and then mixed down
to the IF frequency. The voltage conversion gain of the mixer is 25 dB. Considering the insertion loss of
the band-pass filter as 2 dB, and that of the SAW filter that follows the mixer as 10 dB, the received signal
is amplified by 23 dB (13 dB – 3 dB –2 dB + 25 dB – 10 dB) before being input to the RF2948b.
3.1.4
SI4136 ISM Band RF Synthesizer
The SI4136 is an IF and dual-band RF synthesizer from Silicon Laboratories. It includes three VCOs
(voltage-controlled oscillators) with dedicated PLLs (phase-locked loops) and programmable frequency
ranges. The three VCOs are dedicated to the 2.3 GHz to 2.5 GHz, 2.025 GHz to 2.3 GHz, and 62.5 MHz to
1 GHz bands, respectively. This device is used to provide the 748 MHz IF (which is divided by two in the
RF2948b) and the 2.068 GHz RF carrier signals to the RF front ends. Phase noise must be about equal or
better than the RF VCO to avoid degrading the receiver SNR, as the IF VCO output phase noise is
improved by 6dB when it is divided by two.
31
The center frequency of each VCO (
f VCO ) is set by the sum of the SI4136’s package inductance
( LPKG ) and external inductance ( LEXT ), which is in parallel with the respective VCOs’ nominal
capacitance ( C NOM ) according to:
f VCO =
1
2π ( LPKG + LEXT ) ⋅ C NOM
(3.3)
The PLL of the IF VCO can adjust the output frequency by ±5%. The RF1 and RF2 PLLs have fixed
operating ranges due to the inductance set by the internal bond wires. Inaccuracies in the value of the
external inductance are compensated for by the Si4136’s proprietary self-tuning algorithm. The self-tuning
algorithm tunes the center frequency of the VCO to within 1% of the desired value. After self-tuning, the
PLL maintains frequency lock.
Analyzing the software interface, shown in Figure 3.2, used to program the SI4136 on its evaluation
board can help explain the operation of this device:
Figure 3.2 – SI4136 Programmer interface
32
The RF output frequencies are determined by:
2N
f REF
R
f RF =
(3.4)
The IF output frequency is determined by:
N
f REF
R
f RF =
3.1.5
(3.5)
Linx Technologies λ/2 Dipole Antenna
The software radio uses two identical
λ /2 dipole antennas for transmission and reception.
Ref. [43]
includes a detailed theoretical overview of this and many other antenna types, however we will focus our
attention to the more practical parameters of these antennas as presented in ref. [32]. Most formulas
dealing with antenna parameters are based on the far-field free-space model. The far-field of an antenna is
determined by the Fraunhofer distance
D, and the wavelength,
df =
d f , which is related to largest physical dimension of the antenna,
λ , by:
2D 2
The wavelength for a given center frequency,
λ=
c
f
(3.6)
λ
f , is given by:
(3.7)
33
where c denotes the speed of light in free space. For a center frequency of 2.442 GHz, (3.7) gives a
wavelength of 12.3 cm. The Linx antennas are approximately 7 cm, a little longer than
according to (3.6)
λ /2.
Therefore
d f is approximately 8 cm.
RF signal power decays as a function of the distance, d, between transmitter and receiver. The Friis
free space equation gives the free-space power received ( Pr ) by a receiver antenna as:
Pr (d ) =
Where
Pt Gt Gr λ2
(4π ) 2 d 2 L
(3.8)
Pt is the transmitted power, Gt is the transmitter antenna gain, Gr is the receiver antenna gain,
λ is the wavelength of the operating frequency, L is the system’s non-propagation loss factor (L > 1) due
to attenuation and losses in transmission lines and components. According to ref. [32] the gain of a
λ /2
antenna is estimated at 1.64 (2.15 dB) in the direction of maximum radiation. Thus in a lossless system
operating at 2.442 GHz, where the transmitting
λ /2 dipole is 1 m away (in the far-field) from the receiving
λ /2 dipole antenna, if 500 mW is transmitted, 128 µW is received according to (3.8).
The path loss for the free-space model when antenna gains are included is given by:
PL = 10 log
Pt
Pr
(3.9)
For the above case, this gives a path loss of 35.9 dB (27 dBm +8.9 dBm).
3.2
System Parameters
The signal to noise ratio (SNR), and noise figure (NF) of a receiver are important performancedetermining parameters for any wireless transmission system. Noise comes from many sources, including
thermal noise, shot noise, and flicker noise. The noise figure of a component or system is defined as the
34
ratio of the input SNR to the output SNR. In other words NF describes the degree to which the SNR is
degraded as it passes through a system:
NF =
SNR IN
SNROUT
(3.10)
For cascaded systems, the noise figure is:
NFtotal = 1 + ( NF1 − 1) +
( NF2 − 1) ( NF3 − 1)
+
+ ......
G1
G1G2
(3.11)
The ideal NF is 1 (0 dB), but this isn’t attainable in practice because all components, be they transistors,
resistors, or transmission lines, add noise to a signal as it passes through.
3.2.1 Intermodulation
Nonlinearities in a device cause Intermodulation whereby in-band and out-of-band interference occurs
due to the mixing of interferers. Of special interest are the third-order modulation products because they lie
very close to the interference tones and thus have the potential of falling within the intended signal’s
passband, thereby degrading it’s signal to noise ratio. This process is illustrated in Figure 3.3, where a twotone interfering signal, x(t), is applied to an amplifier with small signal gain
α1
and large signal gain
α 1 +3 α 3 A3 /4.
x(t ) = A cos w1t + A cos w2t
(3.12)
9
9
y (t ) = {α 1 + α 3 A 2 ) A cos w1t + {α 1 + α 3 A 2 ) A cos w2 t
4
4
(3.13)
3
3
+ α 3 A 2 cos(2 w1 − w2 )t + α 3 A 2 cos(2 w2 − w1 )t + ...
4
4
35
BPF
x(t)
y(t)
Desired
Signal
Band
∆P
IM3
IM3
w1 w2
2 w1 - w2 w1 w2 2 w2 - w1
Interferers
Figure 3.3 – Third-order intermodulation product may fall within signal band
The third intercept point, IP3, is defined as the intersection of the first order gain line,
3
α 3 A3 .
4
IP3
Output power (dBm)
third order gain line,
20log( α 1 A)
3
20log( α 3 A3 )
4
input power (dBm)
Figure 3.4 – Third order intercept point
α 1 A, and the
36
The slope of the third order gain line is three times that of the fundamental gain line. IP3 occurs at the
following input (IIP3) and output (OIP3) values:
IIP3 =
4 α 1 ∆P(dB)
=
+ PIN (dB)
3 α3
2
(3.14)
OIP3 = α 1 ( IIP3)
(3.15)
Cascaded IP3 can be calculated as follows:
N
IP3cascaded = 10 log10 ([∑
i =1
1
ip3i +
] −1 )
N
∏G
(3.16)
j
j = i +1
Where
ip3i is the linear IP3 and G j are the linear gain of each stage, respectively. Table 3.1 summarizes
the system gain, NF, and IP3 values.
TABLE 3.1 – RF Front end parameters
RF2494 RF2948b Overall
LNA/Mixer modem
3.2.2
Maximum Cascaded Gain (dB)
38
75
113
Maximum Cascaded NF (dB)
4.1
35
5
Maximum Cascaded IP3 (dBm)
-29
8
-32
Sensitivity
According to [34] an RF receiver’s total input noise power, F, is related to the overall noise figure, NF,
and the channel bandwidth, B, by:
37
F = −174 + 10 log10 B + NF
(3.17)
Where –174 is the source resistance noise power in dBm/Hz, assuming room temperature and conjugate
matching at the system input. The sensitivity of a receiver is defined as the minimum signal level,
that it can detect with acceptable signal to noise ratio,
Pmin ,
SNR Acc . We can calculate Pmin as follows:
Pmin = F + SNR Acc
(3.18)
For a bandwidth of 83.5 MHz (entire ISM band), and a total receiver noise figure of 5 dB, the input noise
power is –89 dBm. If the required SNR is -10 (a typical value) dB, then the sensitivity is -99 dBm.
3.3
Digital Back-End Architecture
The digital back-end is where the software algorithms are processed in software radio systems. In this
design, the digital back-end consists of two digital signal processors (DSPs) from Texas Instruments.
Evaluation kits (DSP starter kits) for the TMS320C6711 and TMS320C5416 DSPs were incorporated into
the software radio design as shown in Figure 3.5.
I
I
RF
Receiver
Q
Data
Converter
Q
MCBSP
DSK
CODEC
CPU
HOST
INT.
MEMORY
RF
Analog
Baseband
Host computer
Digital
Baseband
Figure 3.5 – The DSK is connected to the transceiver unit through the MCBSPs
38
The Code Composer Studio code generation software platform provides a wide range of programming
options for the TI line of DSPs. In this section we will briefly discuss some of these.
3.3.1
DSP Starter Kits
The TMS320C611 (‘6711) DSP is a 32-bit, 150 MHz, floating point digital signal processor. It is based
on the very long instruction word (VLIW) architecture.
Each VLIW is composed of eight 32-bit
instructions, meant for processing by eight pipelined processing units, in parallel. The processing units
include four arithmetic/logic units (ALU) that perform both fixed-point and floating-point math, two ALUs
dedicated to fixed-point math, and two ALUs dedicated to floating-point or fixed-point multiplication. The
CPU delivers 1200 MFLOPS (million floating-point operations per second) and 600 MIPS (million
instructions per second) of processing power. On-chip memory consists of 32 Kbytes of program memory,
32 Kbytes of data memory, and 8 Kbytes of cache memory. The ‘6711 features two 32-bit timers, and two
multi-channel buffered serial ports (MCBSP), which can be used for high-speed communication with
external devices. This and other high-performance floating-point processors are extensively deployed in
cellular base station transceivers.
The DSP starter kit (DSK) for the ‘6711 is a low cost test-bed for TI’s high-end floating point DSPs.
As shown in Figure 3.6, this DSK has a parallel-port PC interface, two 80-pin input-output (IO) digital
connectors for interfacing with other external devices, and JTAG (joint test action group) connectors for
testing. The board also includes 128 Kbytes of flash ROM, and 16 Mbytes of RAM. The ‘C6711 DSK is
capable of transferring up to 35 Mb/s of data through each of its MCBSP ports [45].
39
3.3V
Power
Supply
8Mx16b
SDRAM
PC Parallel
Port
Inerface
128Kx8b
Flash
ROM
80-Pin IO
Connector
TMS320C6711
DSP
Power
Jack
Power
LED
80-Pin IO
Connector
DIP
Switches
1.8V
Power
Supply
JTAG
Header
Reset
Button
JTAG
Controller
AD535 Codec LEDs
IO Microphone
IO Speaker
Figure 3.6 – TMS320C6711 DSP starter kit from Texas Instruments
The AD535 16-bit codec includes an analog to digital converter with a sampling rate of 11 Ksamples/s,
and is suitable for basic audio processing. For applications requiring ADCs with higher sampling rates, TI
supplies a number of daughter-cards that plug into the 80-pin connectors, as shown in Figure 3.7 with the
THS10082. This is a parallel dual channel ADC having a maximum sampling rate of 8 MHz in each
channel.
Figure 3.7 – TMS320C5416 DSK board with THS10082 ADC daughter-card on top
40
The TMS320C5416 (‘C5416) 16-bit, 160 MHz, fixed-point processor was the other DSP evaluated in
this project. The CPU delivers 160 MIPS of processing power and features 128 Kwords of on-chip
program/data memory, and 16 Kwords of program memory. Other features include a timer, and three
MCBSPs. The ‘C5416 is a popular DSP for low-power applications such as cellular handsets.
The DSK for the ‘C5416 has a USB interface to the PC, and four analog IO ports. The on-board codec
features a 16-bit, 48 Ksamples/s ADC. The DSK also features 256 Kwords of flash ROM, and 64 Kwords
of RAM.
3.3.2
Code Composer Studio
Code Composer Studio (CCS) is an integrated development environment customized for the TI family
of DSPs. It includes an editor, debugger, project manager, compiler, assembler, linker, and simulator for
code generation and testing.
What sets it apart from other compiler software is its DSP/BIOS real-time
operating system.
DSP/BIOS provides a graphical interface for static system setup, such as initialization of system
peripherals. It also allows real time data exchange (RTDX) with the host computer. Interrupts and other
tasks can be scheduled through the DSP/BIOS interface. Furthermore, it allows the real-time monitoring
and analysis of system parameters through graphical tools such as spectrum and time-domain plots of
variables, or the timing diagrams.
The TMS320C6000 family of pipelined DSPs’ complex architecture limits the practicality of assembly
coding. Thus most programming is done in high-level languages such as C and C++. The CCS C compiler
is touted to be 80% as efficient as hand-coded assembly [26]. The popular signal processing software
package, MATLAB, now includes a TI DSP toolbox. This allows the compilation and interfacing of
MATLAB code directly to the DSP, by bypassing CCS.
One of the advantages of using TI DSPs is their popularity. There is a treasure trove of programming
resources and examples for download on the Internet. The TI website features optimized function libraries
free for download. Furthermore, there are archived newsgroups dedicated to each family of the TI line of
DSPs, where users from across the world discuss DSP related problems and anecdotes.
CHAPTER 4
EXPERIMENTAL TECHNIQUES AND RESULTS
The subject of this chapter is the design process, testing procedures, and measurement results of the
software radio system developed as part of this thesis. We will begin our discussion with a description of
the DSP algorithm design process, and parameters involved therein. This will be followed by an overview
of the RF front end assembly and testing procedure. The chapter will conclude with a display of the test
results performed.
4.1 DSP Algorithm Design
As described briefly in Chapter One, and more thoroughly in Appendix D, the basic function of a DSSS
transmitter at baseband is to spread the data stream with the PN sequence before transmission.
As
described in Appendix D, the most critical aspect of a DSSS system is PN code synchronization. The
DSSS baseband transceiver design outlined in Appendix E uses a matched filter based correlator and delaylocked loop (DLL) architecture to perform the code acquisition and tracking. The initial DSP algorithm
design, presented in Appendix B, uses the concept of synchronous DSSS. In a synchronous DSSS system
code synchronization information is transmitted with the data on a separate channel [5]. This concept is
used in practical CDMA systems where a separate sync channel operating at 1200 bits/s assists in code
synchronization. In GSM systems, frame timing information is sent to mobile units in order to synchronize
time slots [28].
As discussed in the previous chapter, the RF front end is a quadrature modulator/demodulator, thus it has
two channels for transmission and reception. These two channels can be used to transmit the data and
synchronization bit-streams from the transmitter DSP to the receiver DSP. TI’s DSPs feature multi-channel
buffered serial ports, or MCBSPs, which can be operated using a number of standards such as the T1/E1
41
42
standard, or Motorola’s serial port interface (SPI) standard. As mentioned in the previous chapter, the
MCBSPs can be operated at speeds in excess of 30 Mb/s. To aid in the code development process, Code
Composer Studio’s DSP/BIOS configuration utility was used to configure the MCBSPs. The interface
window used to perform this task is depicted in Figure 4.1. This utility generates the required initialization
code, which specifies parameters such as clock speed, frame sync pulse polarity, and data packet size.
Figure 4.1 – A screenshot of CCS’s DSP/BIOS configuration menu
Figure 4.1 also shows some of the other DSP parameters that can be configured by the DSP/BIOS
utility.
These include hardware and software interrupts, timers, clock generators, and the host-port
interface.
The transmitting MCBSP is configured as a serial port master; therefore it provides the clock and frame
sync pulses to the receiving MCBSP, which is configured as a slave. This arrangement is shown in Figure
4.2:
43
MCBSP Master
Transmitter
CLKX
MCBSP Slave
Receiver
CLKX
DX
DR
FSX
FSX
Figure 4.2 – Master/Slave SPI interface between a transmitter/receiver pair
where CLKX is the transfer clock IO port, DX is the output data port, DR is the input data port, and FSX is
the frame sync IO port. Figure 4.3 shows the actual output of the TMS320C5416 DSP’s MCBSP port as
observed on a logic analyzer:
Figure 4.3 – The MCBSP operating in SPI mode, as viewed on a logic analyzer
44
As discussed in ref. [43], the slave receiver’s clock can be internally generated. This clock can then be
synchronized to the transmitter’s clock by the transitions of the received sync pulse (FSX). Thus the
MCBSP’s provide a high speed and efficient way to implement a synchronous DSSS system.
Flowcharts of the transmit and receive algorithms are presented in Figures 4.4 and 4.5, respectively.
The data bits to be transmitted, d(x), are read from a file and over-sampled by a factor equal to the length of
the PN code. The over-sampled data is then spread by the PN sequence. The spread data is then placed in
the data transmit register (DXR) of the MCBSP and transmitted through the DX output port.
Over
Sample
Data File
Bits d(0)....d(n)
d(m)
XOR
PN Length
x(m)
MCBSP
Data
Transmit
Register
PN
Figure 4.4 – Data processing at the transmitter
MCBSP
Data
Receive
Register
Down
Sample
y(m)
XOR
PN
Data File
d'(m)
Bits d'(0)....d'(n)
PN Length
Figure 4.5 – Data processing at the receiver
At the receiver, the MCBSP receives the spread data and puts it into the data receive register (DRR).
The contents of the buffer are then despread and down-sampled to recover the initial transmitted bits.
Two different programming methods were used for the respective DSPs. The C program written for the
‘C5416 uses polling to constantly monitor the status of the transmitter ready (XRDY) and receiver ready
(RRDY) bits in the serial port control register (SPCR). The XRDY bit indicates that the data in the DXR
has been copied into the transmit shift register (XSR), and new data can now be placed in the DXR. The
45
RRDY indicates that the data in the receive buffer register has been written to the DRR and is ready to be
read by the CPU.
An alternative to polling is event-triggered interrupts. This method is used in the C program written for
the ‘C6711. The receive interrupt (RINT) and the transmit interrupt (XINT) are set to be triggered by the
status of the XRDY and RRDY signals, respectively. Appendix B contains the documented C code written
for each DSP.
The MCBSPs provide digital communication ports having very wide bandwidths, thus they show much
potential in any software radio system. The next challenge in the design is a high bandwidth digital to
analog converter (DAC) circuit.
4.2 Digital to Analog Converter
The RF2948B modulator requires a peak-to-peak input voltage of 100 mV with 1.6 V dc bias.
digital output of the DSP is 0 – 3.3 V as shown in Figure 4.6, thus it must be conditioned by the DAC.
Figure 4.6 – Digital output from the DSP
The
46
The plot shown in Figure 4.6 shows a square wave with an approximate frequency of 40 KHz. The
DAC circuit, shown in Appendix A, is a dual-channel buffer circuit with fairly wide bandwidth. The
output of the DAC for the input shown in Figure 4.6, is shown in Figure 4.7:
Figure 4.7 – DAC output when the input is a 40 KHz square wave
The DAC performance begins to degrade when the signal frequency approaches 5 MHz. Thus the
bandwidth is fairly wide, and suitable for high speed data rates.
4.3 RF Front End Assembly and Testing Methods
The RF front end was assembled using the evaluation boards of the various chips. The boards’ inputs
were all matched to 50 Ohms, according to specs. Most of the boards’ RF connections were through
female SMA connectors. To minimize stub lengths, most connections were bridged with SMA-to-SMA
adaptors. As shown in Figures 4.8 and 4.9, the boards were all shielded to minimize unwanted in-bound or
out-bound radiation.
47
Antenna
2.4 - 2.43 GHz
BPF
RF2948B
SI4136
RF5117
Figure 4.8 – RF transmitter unit
2.4 - 2.483 GHz
BPF
Antenna
RF2948B
RF2494
Figure 4.9 – RF receiver unit
SI4136
48
The boards that held the RF boards were wrapped with copper foil, the same material as the shields. The
large ground plane helps provide electric shielding to the circuit as a whole [29].
Where possible, the
ground and power lines were twisted together to reduce noise.
4.4 RF Measurements
A valuable tool in the analysis of the RF front end’s operation was the HP 8561A spectrum analyzer,
which has a measurement range up to 6 GHz. The RF measurements presented here are mostly centered on
the transmitter unit. The spectrum analyzer has a 50 Ohm matched input port, which was connected to the
circuits under test with the shortest interconnection possible. Usually this consisted of an N-type to SMA
adaptor. Received power measurements were done by substituting the RF receiver with the spectrum
analyzer fitted with the half-wavelength dipole antenna.
The first RF test carried out was to verify that the DSSS transmitter was indeed spreading the
bandwidth of the data. Figure 4.10 shows the spectrum of a 2.44 GHz carrier, modulated with a 31.25 KHz
square wave using QPSK modulation.
The examined signal is the output of the RF2948B’s power
amplifier driver port.
Figure 4.10 – Spectrum of a narrowband QPSK signal
49
Figure 4.11 depicts the spectrum of the same signal as Figure 4.10, spread by a 16 bit PN code. A
visual observation shows that the power spectral density has been spread out, and the signal bandwidth
increased.
Figure 4.11 – The signal of Figure 4.11 spread by a 16-bit PN sequence
A comparison of the peak power spectral densities shows a processing gain of 7.83 dB (17.33 - 9.5).
Equation (1.1) can be used along with the spread chip rate and the encoded data rate to calculate the
theoretical processing gain:
 16 
PG = 10 ⋅ log 10   = 9.03dB
2
Figures 4.12 and 4.13 compare the transmitted power out of the RF5117 to the received power at a distance
of 30 cm.
50
Figure 4.12 – Transmitted power spectrum for TxVGC=1.54V (upconverter gain = 2 dB)
Figure 4.12 shows a transmitted power of 14.17 dBm or 26.1 mW. From equation (3.8) the theoretical
received power at a distance of 30 cm can be calculated as follows:
Pr (30cm) =
26.1mW * 1.64 2 0.123 2
= 74.7uW
(4π ) 2 0.3 21
The assumptions made here are that the antenna gains of the half-wavelength dipole antennas are 1.64,
and that the non-propogational loss of the system is equal to one. Figure 4.13 shows the received signal
spectrum at a distance of 30 cm from the transmitter.
51
Figure 4.13 – Received power at ½ meter away
The actual received power according to Figure 4.13 is –16 dBm 25.1 uW. Thus the actual path loss of
the system according to equation (3.9) is calculated as follows:
PL(30cm) = 10 log
26.1
= 30.17 dB
0.0251
An important parameter in the assessment of transmitters is carrier to noise ratio (CNR). This is usually the
measure of the power of the carrier, to the power of the main side-lobe. Figure 4.14 displays the CNR at
the output of the RF transmitter. Thus the carrier is roughly 42 dB stronger than the next highest side-lobe.
52
Figure 4.14 – Carrier power to that of the main side lobe
Further measurements show that the carrier is roughly 58 dBm above the system noise floor.
In conclusion, the transmitter and receiver sections of a software radio were designed and tested in
conjunction with a DSP. Thus the essential elements of a software radio were implemented.
The
performance was compared to theory and it was found that the components peformed satisfactorily at 2.44
GHz.
CHAPTER 5
SOFTWARE RADIO DEVELOPMENT STATUS AND FUTURE OUTLOOK
This chapter will begin with a summary of the software radio concept and its assessment in a university
environment.
Next, a progress report on the development of the software radio project at Auburn
University will be presented. Since this initiative is in its infancy, this thesis serves as a basis for future
development. Thus an effort will be made to highlight some of the lessons learned from the design
approach thus far. The chapter will conclude with a set of recommendations on future investment and
design in this project.
5.1
Progress Report
In this section we seek to describe the present status of each of the software radio components. This
will serve as an assessment of the overall system, and a roadmap for future work.
The synchronous DSSS algorithm was designed and tested on each DSK board in wired mode. These
tests were performed at speeds in excess of the bandwidth of the DAC board. It was found that the DSKs
are valuable tools in this application due to their ease of use and online programming resources. The
Tektronix 1225 logic analyzer used to test the digital outputs of the DSK’s was found to be a useful
evaluation tool. Figure 5.1 depicts the DSK test setup.
53
54
Figure 5.1 – DSP testing with the Tektronix 1225 logic analyzer
The C programs generated for the two DSPs are good basis for any future algorithm enhancement.
The DAC circuit designed to interface the DSKs’ serial port outputs to the RF transmitter is a success.
This two-channel device supports data rates as high as 5 MHz, which is sufficient for a wideband DSSS
system.
The RF front end was successfully built and tested. Figure 5.2 shows the transmission of two sinusoids
through the I and Q channels of the front end during testing. Shielding of the RF boards significantly
improved the performance of the system. Another possible performance improving factor may have been
the use of batteries rather than DC power supplies.
Further receiver measurements were not possible
because during final data collection for this thesis, the RF2494 LNA/mixer chip failed. The most likely
55
causes for this include electrostatic discharge (despite precautions) or voltage spikes introduced during
testing. This highlights the fragility of the evaluation board-based design.
Figure 5.2 – Signals received through the RF link are displayed on the oscilloscope
At the time of this writing, a dual-channel ADC circuit has been designed and awaits testing. With the
replacement of the RF2494 chip, and the addition of the ADC circuit, the wireless loop will be complete.
Serial data and synchronization information can then be transmitted from one serial port to another, on
different DSKs, or on the same DSK, since the two serial ports can be used to run a full-duplex link.
5.2 System Enhancements
One of the options available in the design of the software radio system was the use of ADC and DAC
daughtercards on the DSKs for high-speed data conversion.
This option was postponed due to the
development time needed to design the interface code for the daughtercards. The ‘C5416 and ‘C6711
DSPs use dynamic memory access (DMA), and extended DMA (EDMA), respectively, to read and write
data to and from the daughtercards. These data transfer modes can be used for high-speed high-resolution
data.
56
The main flaw in the current design concept is that analog to digital conversion is done with one-bit
resolution. The analog outputs of the RF2948 are amplified in voltage, and then passed through bus driver
chips to generate the digital signals necessary for input to the DSPs’ serial ports. This lack of resolution
leads to a higher bit error rate (BER), thus the data-rates must be lowered in order to achieve reliable
communication. The use of the daughtercards significantly increases bit-resolution thus system versatility
and performance are improved.
An important feature to incorporate into the system is automatic gain control (AGC) to achieve
maximum signal to noise ratio at the receiver. Currently, gain control on the RF front end is done
manually. An ADC daughtercard, or perhaps the onboard audio output of the DSK, can be used to perform
AGC.
The motivation behind choosing the evaluation board based RF front end was that this setup provided
RF testing capabilities that a packaged system would not. The numerous RF IO ports on each of the front
end evaluation boards provided the means to measure a signal at the various stages of transmission, or to
measure other parameters by inserting test signals. Although the motivation behind this approach was a
noble one, it does not work well in practice.
The RF front end chips are extremely sensitive to electrostatic discharge, and thus they are too fragile to
be manually tested on a long-term basis.
Even when proper anti-static precautions are taken, the
probability of accidents is likely. This lesson was learned time and again, especially with the RF2948B and
RF2494 chips. It is also worth mentioning that the debugging of the front end circuitry was a laborious
task that took up most of the time spent on this project, thus limiting the time spent on DSP algorithm
development.
An alternative to using the evaluation boards is to construct an enclosed front end, incorporating all of
the chipset components onto one board. This may entail some cost, but may be worth the investment
because there are few commercially available RF front end modules on the market, to the best of the
author’s knowledge. If this approach is taken, it may be more prudent to use a more compact chipset such
as Maxim Semiconductor’s Max2822 single-chip direct conversion transceiver [23]. This chip includes all
the necessary front end components with the exception of the RF band-pass filter and antenna.
57
The remaining option is to sacrifice signal processing flexibility and purchase original equipment
manufacturer (OEM) modules such as Agere Systems’ Wavelan WL1141 single component 802.11b
physical layer module [72]. This module performs all the RF and digital modulation and demodulation for
a wireless modem. Such modules are available for most of the popular wireless standards.
As discussed in Chapter Three, one of the limitations to software radio performance is processing
power.
Thus high-speed ASICs or FPGAs are used to perform static functions so as to reduce the
processing load of the DSPs. In Appendix E, the design of a DSSS baseband transceiver in Verilog HDL is
discussed. This design is centered around a digital matched filter, which is a static function and ideally
implemented on an FPGA device.
5.3 Concluding Remarks
In Chapters One and Two, we discussed the growing popularity of the software radio concept in
industry, academia, and the military.
With constant enhancements in digital signal processing, data
conversion, and RF technology, the proliferation of software radio systems will accelerate.
Thus a
research/education laboratory dedicated to this technology is highly attractive, if not essential for academic
institutions that have wireless communications programs, such as Auburn University.
Most undergraduate wireless communications laboratories fall into two categories, based on the
emphasis of their content. Some emphasize digital signal processing algorithm design and testing [38, 20],
while others emphasize RF circuit design and testing [47,19,14]. A software-radio-based laboratory would
consist of digital signal processing algorithm design and its performance measurement in a real RF
environment. Thus some of the emphasis would be taken away from RF circuit design, and placed on the
RF system design, where optimized modules are assembled to achieve optimum results.
It is the hope of the author that the software radio project undertaken as part of this thesis will be
continued and expanded.
One of the main goals of the Wireless Engineering Initiative at Auburn
University is to create a program that will be at the cutting edge of wireless education and technology. The
software radio project, if continued, has the potential to contribute a great deal toward this goal.
APPENDIX A
SYSTEM SCHEMATICS
A.1
RF Transmitter
Referring to Figure. A.1, the transmitter inputs I and Q are the data and synchronization signals from
the DSK’s serial port, respectively. These signals are pulses which transition from a low value of 0 V to a
high value of 3.3 V, with duty cycles of 50%. The frequency range of the input signals is up to 5 MHz.
Each channel (I and Q) is magnitude scaled and level-shifted by a circuit consisting of a voltage divider
and four wideband (unity gain bandwidth of 100 MHz) op-amps, LM6172. The voltage divider (1kΩ, 27
Ω) attenuates the signal by a factor of 37. The first op-amp stage is a unity-gain buffer which serves to
isolate the attenuated signal. The second op-amp stage adds a bias (dc offset) to the signal according to the
following expression:
VOut 2 = −(VIn 2 + VBias )
(A.1)
This stage incorporates a dc bias produced by a separate op-amp circuit as shown. The value of dc bias is
given by the expression:
VBias = 9(
225
) = 1.65V
225 + 1K
(A.2)
The third stage has a gain of –1 to compensate for the inversion introduced by the second stage. It should
be noted that the low values of resistance used are necessary, since, as stated on the data sheet, the feedback
resistance is required to be less than 1 kΩ for the wideband op-amps used. Thus the overall transfer
function for the voltage divider and op-amps is:
58
59
JIF1
5V
+5V
Gnd
+3V
BPF2450
Band-pass filter
Telectronics Internaitonal Inc.
SI4133BT-EVB Rev 3.0
JRF1
Ext
J8
3.3V
Gnd
Vref1 Buff
J1
IF Out
J9
J8
P1
PS_Ref
PWR_Sense
Gnd
VREG1
VREG2
J2
TxI Data
I Out
Tx VGC
Vcc
J3
Gnd
P1
Q Out
PA In
J2
J1
J11
RF LO
J5
RF Out
J4
Rx VGC
Pd
Rx En
Gnd
P2
1.4-1.9V
3.3V
RF2948B PCBA
Evaluation Board
2948B410(A)
TxQ Data
PA Out
RF Out
RF In
IF LO
J10
RF5117 PCBA
Evaluation Board
5117410(-)
Rx/Tx IF In
P2
Vcc
Gnd
Gnd
J6
P3
J7
3V
3V
+9V
I in 1K
27Ω
Bias
820 Ω
820 Ω
+
-
820 Ω
820 Ω
820 Ω
+
9V
-
1K
+
-9V
-
+9V
Q in 1K
27Ω
Bias
+
-
Bias
+
820 Ω
820 Ω
820 Ω
-
820 Ω
820 Ω
-
+
+
-9V
225 Ω
All op-amps:
LM6172
Figure A.1 - RF Transmitter front end
VOut = (attenuation ⋅ Vin + VBias ) = (
1
Vin + 1.65V )
37
(A.3)
60
Consequently the input signals to the RF2948B Evaluation Board are pulses with low
value of 1.65 V and high value of 1.74 V. The amplitude is 90 mV peak-to-peak and the
dc offset is 1.65. The RF2948 requires the analog baseband inputs to be 100 mV peak-topeak with 1.6 V to 1.8 V of dc bias. Thus the output of the converter circuit meets these
specifications.
A.2
RF Receiver
The outputs of the RF2948 receive circuitry are baseband analog square pulses with a peak-to-peak
voltage of 700 mV, and 1.7 V of dc bias. At the time of this writing, the ADC circuit to interface these
outputs to the DSK’s serial port was in the design stages.
JIF1
5V
+5V
Gnd
+3V
BPF2450
Band-pass filter
Telectronics Internaitonal Inc.
SI4133BT-EVB Rev 3.0
JRF1
Ext
J8
3V
Gnd
Vref1 Buff
J1
3.3 V
J9
RF2948B PCBA
Evaluation Board
2948B410(A)
J11
RF LO
3.3V
J8
Tx VGC
Vcc
J3
Gnd
P1
J2
J5
RF Out
J4
Rx VGC
Pd
Rx En
Gnd
P2
PA In
TxQ Data
Gnd
Vcc
P3
J4
LO In
I Out
RF2494 PCBA
Evaluation Board
RF2494410(A)
IF LO
PA Out
TxI Data
LNA In
IF Out
J10
J3
Mixer In
IF Out
J5
J6
J2
LNA Out
Q Out
J1
P1
Gnd
Rx En
Pd
Rx/Tx IF In
Gnd
GS
3V
P3
J7
1.2-1.9V
To Dual Channel
ADC
Figure A.2 - RF receiver front end
3V
APPENDIX B
DSP CODE
In this appendix we present the C programs written for the TMS320C5416 and TMS320C6711 DSPs.
The input data file that was used for testing will follow. The DSP/BIOS configuration file/s were too long
to include, but a brief but straightforward method of generating them will be given.
B.1
TMS320C5416 Main Program
/* This program will take binary data out of an input file, data.cof, and spread each element by the specified
PN code. The spread data will then be placed into a buffer and transmitted through MCBSP0. Reception is
made through MCBSP1, which either has to be wired up or connected through a wireless link to the
transmitting MCBSP. The received data is then despread and placed into an array. The main program loop
uses polling to monitor the status of the serial ports’ receive ready and transmit ready signals, before
initiating transfers /*
#include <std.h>
#include <log.h>
#include <math.h>
#include <csl.h>
#include <csl_mcbsp.h>
#include <csl_irq.h>
#include "mcbspcfg.h"
//Configuration file generated byDSP/BIOS
#include "data.cof"
//File containing bits to be transmitted
61
62
/* Different PN sequences used for testing */
//#define PN 183270610
//32 bit m-sequence 0
//#define PN 157796075
//32 bit m-sequence 1
//#define PN 0xffffffff
// 32 ones
#define PN 4111695058
#define PN_LENGTH 32
//#define PN_LENGTH 8
/* Create transmit and receive data buffers for transfer of data file*/
Uint32 xmt0[DATA_LENGTH], rcv1[DATA_LENGTH];
void main() {
Uint16 i;
// Initilize data buffers. xmt will be 32 bit value equal to the spread data
for(i=0;i<=DATA_LENGTH-1;i++) {
xmt0[i]=(0xffffffff*DATA[i])^PN;
//Each data bit is oversampled and
//then spread by the PN code
rcv1[i] = 0;
}
}
void taskFunc() {
Uint16 i;
/* Start the MCBSP and Sample Rate Generator.
The MCBSP_Handle object, hMcbsp0 has been
//Initialize the receive buffer to zeros
63
predefined in code generated by DSPBIOS/CSL
GUI configuration.*/
/* Take MCBSP receive and transmit out of reset */
MCBSP_start(hMcbsp0,
MCBSP_RCV_START | MCBSP_XMIT_START,
0
);
MCBSP_start(hMcbsp1,
MCBSP_RCV_START | MCBSP_XMIT_START,
0
);
/* Prime MCBSP DXR */
while (!MCBSP_xrdy(hMcbsp0)) {
;
}
/* When MCBSP0 is ready to transmit, send the first element of the transmit buffer to transmit register */
MCBSP_write32(hMcbsp0, xmt0[0]);
/* Start the MCBSPs and Sample Rate Generators */
MCBSP_start(hMcbsp0,
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
0x200
);
MCBSP_start(hMcbsp1,
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
64
0x200
);
/* Get First Element */
while (!MCBSP_rrdy(hMcbsp1)) {
;
}
/* Read 32 bit value from DRR */
rcv1[0] = (MCBSP_read32(hMcbsp1)^PN) >> (PN_LENGTH-1);
/* Begin data transfer loop. We will loop thru to transmit and receive the data. The XRDY and RRDY
signals are polled and, and data transfers are initiated accordingly. In this program, the file is transferred
from MCBSP0 to MCBSP1 of the ‘C5416. */
for (i=1; i<= DATA_LENGTH; i++) {
/* Wait for XRDY signal before writing data to DXR */
while (!MCBSP_xrdy(hMcbsp0));
/* Write 32 bit data value to DXR */
MCBSP_write32(hMcbsp0, xmt0[i]);
/* Wait for RRDY signal to read data from DRR */
while (!MCBSP_rrdy(hMcbsp1));
/* Read 32 bit value from DRR, despread it, undersample it, place it in receive array. This has only been
tested in wired mode, where errors are seldom. In wireless mode, all 32 bits may have to be averaged out
and the best estimage placed in the buffer */
65
rcv1[i] = (MCBSP_read32(hMcbsp1)^PN) >> (PN_LENGTH-1);
}
/* We are done with MCBSP, so close it */
MCBSP_close(hMcbsp0);
MCBSP_close(hMcbsp1);
}
B.2 TMS320C6711 Main Program
/* This program uses interrupts to initiate data transfers through the serial ports. Interrupt events are
triggered by the receive ready and transmit ready signals of the serial ports. This is a somewhat more
efficient way of operating because system resources are not in waiting while nothing is being transferred. */
#define CHIP_6711
/* Chip number */
/* Include files */
#include <c6x.h>
#include <csl.h>
/* CSL library */
#include <csl_dma.h>
/* DMA_SUPPORT */
#include <csl_edma.h>
/* EDMA_SUPPORT */
#include <csl_irq.h>
/* IRQ_SUPPORT */
#include <csl_mcbsp.h>
/* MCBSP_SUPPORT */
#include <c6x11dsk.h>
#include <stdio.h>
#include "data.cof"
/* data file */
#include "spicfg.h"
/* DSP/BIOS configuration file */
66
/* PN sequence properties */
Uint32 PN = 170;
Uint32 PN_LENGTH = 8;
/* Global variables used in interrupt ISRs */
volatile int recv0_done = FALSE;
volatile int xmit0_done = FALSE;
/* External functions and function prototypes */
void enab_mcbsp0_int(void);
void enab_mcbsp1_int(void);
/* Create input and output buffers. */
Uint32 Inbuff[DATA_LENGTH];
Uint32 Outbuff[DATA_LENGTH];
void main(void)
{
/* Declaration of local variables */
Uint32 wait = 0;
Uint32 y;
/* initialize the CSL library */
CSL_init();
/* enable the McBSP TX/RX INTs*/
enab_mcbsp0_int();
enab_mcbsp1_int();
/* Counter to initialize buffers */
67
/* Enable sample rate generator - GRST=1 */
MCBSP_enableSrgr(hMcbsp0);
MCBSP_enableSrgr(hMcbsp1);
for (wait=0; wait<0x10; wait++);
/* Wait states after SRG starts */
#if (EDMA_SUPPORT)
/* for EDMA supporting devices */
EDMA_clearPram(0x00000000);
/* Clear PaRAM RAM of the EDMA */
set_interrupts_edma();
#endif
/* EDMA channels 12 and 13 config structures */
#if (EDMA_SUPPORT) /* for EDMA supporting devices */
for (y=0;y<DATA_LENGTH;y++) {
/* Initialize the Outbuff */
Outbuff[y]=255*DATA[y]^PN;
/* spread the data */
Inbuff[y]=0;
/* initialize the input buffer to zeros */
}
#endif
MCBSP_enableRcv(hMcbsp0);
/* Enable McBSP port 0 as the receiver */
MCBSP_enableXmt(hMcbsp0);
/* Enable McBSP port 0 as the transmitter */
MCBSP_enableRcv(hMcbsp1);
/* Enable McBSP port 0 as the receiver */
MCBSP_enableXmt(hMcbsp1);
/* Enable McBSP port 0 as the transmitter */
MCBSP_enableFsync(hMcbsp0);
MCBSP_enableFsync(hMcbsp1);
while (!xmit0_done || !recv0_done);
68
MCBSP_close(hMcbsp0); /* close McBSP port */
#if(EDMA_SUPPORT)
#endif
}
/* end main */
/* enab_mcbsp0_int(void)
*/
void enab_mcbsp0_int(void)
{
// added by weilin: enable McBSP0 trans. int.
IRQ_reset(IRQ_EVT_XINT0);
IRQ_disable(IRQ_EVT_XINT0);
IRQ_clear(IRQ_EVT_XINT0);
IRQ_enable(IRQ_EVT_XINT0);
// added by weilin: enable McBSP0 recv. int.
IRQ_reset(IRQ_EVT_RINT0);
IRQ_disable(IRQ_EVT_RINT0);
IRQ_clear(IRQ_EVT_RINT0);
IRQ_enable(IRQ_EVT_RINT0);
}
void enab_mcbsp1_int(void)
{
69
// added by weilin: enable McBSP0 trans. int.
IRQ_reset(IRQ_EVT_XINT1);
IRQ_disable(IRQ_EVT_XINT1);
IRQ_clear(IRQ_EVT_XINT1);
IRQ_enable(IRQ_EVT_XINT1);
// added by weilin: enable McBSP0 recv. int.
IRQ_reset(IRQ_EVT_RINT1);
IRQ_disable(IRQ_EVT_RINT1);
IRQ_clear(IRQ_EVT_RINT1);
IRQ_enable(IRQ_EVT_RINT1);
}
/* set_interrupts_edma() */
#if (EDMA_SUPPORT)
void
/* Set the interrupts */
set_interrupts_edma(void)
/* if the device supports EDMA */
{
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_reset(IRQ_EVT_EDMAINT);
IRQ_disable(IRQ_EVT_EDMAINT);
EDMA_intDisable(12);
/* ch 12 for McBSP transmit event XEVT0 */
EDMA_intDisable(13);
/* ch 13 for McBSP receive event REVT0 */
IRQ_clear(IRQ_EVT_EDMAINT);
EDMA_intClear(12);
70
EDMA_intClear(13);
IRQ_enable(IRQ_EVT_EDMAINT);
EDMA_intEnable(12);
EDMA_intEnable(13);
return;
}
#endif
interrupt void
/* vecs.asm hooks this up to IRQ 08 */
c_int08(void)
/* for the EDMA */
{
#if (EDMA_SUPPORT)
if (EDMA_intTest(12))
{
xmit0_done = TRUE;
puts("EDMA 12 int.");
EDMA_intClear(12);
/* clear CIPR bit so future interrupts can be recognized */
}
else if (EDMA_intTest(13))
{
recv0_done = TRUE;
puts("EDMA 13 int.");
EDMA_intClear(13);
}
#endif
return;
}
/* clear CIPR bit so future interrupts can be recognized */
71
/* IRQ 09: McBSP0 transmit */
interrupt void
c_int09(void)
{
static int tcnt = 0;
int *m0 = (int *)MCBSP_ADDRH(hMcbsp0, DXR);
// transmit data
if (tcnt < DATA_LENGTH) {
m0[0] = Outbuff[tcnt] ;
tcnt++;
return;
}
return;
}
/* IRQ 12: McBSP1 transmit */
interrupt void
c_int12(void)
{
/* We are only receiving out of MCBSP1 in this instant */
return;
}
// IRQ 11: McBSP0 receive
interrupt void
72
c_int11(void)
{
/* We are only transmitting out of MCBSP0 in this instant */
return;
}
// IRQ 13: McBSP1 receive
interrupt void
c_int13(void)
{
static int rcnt1 = 0;
int *m1 = (int *)MCBSP_ADDRH(hMcbsp1, DRR);
/* receive, undersample, and despread the data before putting it in the input buffer */
Inbuff[rcnt1++] = (m1[0]^PN) >> (PN_LENGTH-1);
puts("rx");
return;
}
B.3 Input Data File Format
The data.cof file contains test data used for algorithm testing. The random binary data were generated in
Matlab. The following is the format of the file.
73
#define DATA_LENGTH 1024
Uint32 DATA[DATA_LENGTH]={
1, 1, 0, 0, 1, 1, 0, 0, 0, 1, …….,0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1};
B.4 DSP/BIOS Configuration Procedure
Chapter 12 of TI’s TMS320C6000 Peripherals Reference Guide technical document (SPRU190D) has a
detailed explanation of the various MCBSP parameters that have to be set up to achieve the desired results.
The DSP/BIOS GUI utility can be used to quickly set all the necessary system parameters. In interruptdriven operation, the hardware interrupts should be defined in the GUI. The .cdb file generated by
DSP/BIOS should then be saved and added to the project before program execution.
APPENDIX C
SOFTWARE RADIO BILL OF MATERIALS AND TOTAL COST ESTIMATE
Table C.1 – Software radio bill of materials and project costs
QTY PART #
MANUFACURER
DESCRIPTION
PRICE
5
RF2948B-PCBA
RFMD
2.4 GHz QPSK modem eval board
$450.00
3
RF2494-PCBA
RFMD
High frequency LNA/Mixer eval board
$300.00
1
RF5117-PCBA
RFMD
Linear power amplifier eval baord
$150.00
2
RF3000-PCBA
RFMD
802.11b baseband processor
$300.00
2
SI4136-EVB
SI Labs
Dual frequency synthesizer eval board
$300.00
2
ANT-2.4-RCT-55
Linx Technologies
2.4 GHz 1/4 wave dipole antennas
$13.00
2
RFW-5040-12
Microwave Dist. Co.
12'' double shielded coax assembly
$47.74
2
RFW-5170-12
Microwave Dist. Co.
12'' double shielded coax assembly
$43.28
2
RFW-5170-24
Microwave Dist. Co.
24'' double shielded coax assembly
$52.14
2
RFW-5369-12
Microwave Dist. Co.
12'' double shielded coax assembly
2
BP-FTL-2400
Teletronics International
2.4 GHz 3 pole bandpass filter
$43.84
$119.90
1
THS10082EVM
Texas Instruments
Dual channel, 8 Msps, ADC eval board
$99.00
1
TLV5619-5639EVM
Texas Instruments
Dual channel, DAC eval board
$99.00
1
MULTI-CNVTR-EVM
Texas Instruments
Dual channel, DAC/ADC eval board
1
TMS320C5416DSK
Texas Instruments
TMS320C5416, DSP starter kit
$295.00
1
TMDS320C6711DSK
Texas Instruments
TMDS320C670, DSP starter kit
$395.00
$99.00
2
RSA-3477
HD Comm. Corp.
SMA f/Type N F adapter
$15.00
2
RSA-3453
HD Comm. Corp.
SMA mALE to N male adapter
$15.00
6
PE-3385-6
Pasternack
6"" double shielded coax assembly
2
23-448
Radio Shack
Rechargable 9V NiCd battery
2
275-625A
Radio Shack
Toggle switch, single pole double throw
2
271-282
Radio Shack
10K microsize potentiometer
$2.38
2
42-2444
Radio Shack
6' 1/8'' phono plug cable
$7.98
1
23-422
Radio Shack
Battery charger for NiCd and NiMh batteries
$194.40
$21.98
$6.98
$34.99
2
278-254
Radio Shack
RCA to BNC adaptor
10
RFI-RSA-3403-1
Hutton Comm.
SMA male to SMA male adaptor
$50.10
$9.98
2
RFI-RSA-3458
Hutton Comm.
SA male to BNC female adaptor
$9.98
10
LM6172
National Semiconductor
dual op-amp chips
$38.00
TOTAL =
74
$3,213.67
APPENDIX D
DIRECT SEQUENCE SPREAD SPECTRUM
D.1
DSSS Basics
Direct sequence (DS) spread spectrum was first developed during World War II by the US military as a
secure method of wireless communication. It was declassified in 1985 and since then has fostered a series
of revolutionary technologies such as IEEE 802.11b, and CDMA.
The basic concept of DS can be seen in Figure D.1, where the data symbols to be transmitted are
modulo-two added (XORed) to the pseudo-noise (PN) sequence at the transmitting end. The desired
receiver has an exact replica of the transmitter’s PN sequence, and if it is able to align the PN code
correctly, a second modulo-two addition with the PN sequence will lead to the recovery of the data
symbols.
State
TS
TC
1
Data Symbols
-1
1
PN Sequence
-1
1
Spread Sequence
-1
1
Copy of PN Sequence
-1
1
Recovered Data
-1
Time
Figure D.1 – The basis of DS spreading with XOR operations
75
76
A basic DS transmitter, shown in Figure D.2, multiplies each outgoing data symbol by a high
frequency PN sequence.
Spread
Symbols
Symbols to be
transmitted
DAC
Chip Clock
PN
Generator
Figure D.2 - Basic DS transmitter architecture
The transmitted signal, s(t), can therefore be characterized by the following equation:
s (t ) = A d (t )c(t ) cos 2πft
(D.1)
Where d(t) denotes the transmitted data symbols, c(t) denotes the PN sequence, and the amplitude and
frequency of the carrier are denoted by A and f, respectively. This process, known as spreading, increases
the bandwidth of the symbol sequence by a factor known as the processing gain, PG. PG is calculated by
the ratio of the symbol period,
T
PG = 10 ⋅ log10  S
 TC
TS , to the chip period of the PN sequence, TC : where TS >> TC .



(D.2)
As illustrated in Figure D.3, an additional property of spread spectrum is the lowering of the peak power
spectral density by the processing gain.
77
U n s p re a d
S p re a d
− fC
− fS
fS
fC
Figure D.3 - Signal power spectral density before and after spreading
The transmitted spread spectrum signal is thus a wideband signal that can hardly be differentiated from
channel noise, if the processing gain is high enough. The amount of degradation faced by the signal in the
transmission channel is dependent on the degree and characteristics of interference sources present in the
channel. One obvious advantage of spread spectrum its resistance to narrowband noise. As demonstrated
in Figure D.4, since the spectrum of the signal is so much wider than that of the narrowband interferer,
most of the signal power can still be received.
S p e c tra l
d e n s ity
In te r fe r e r
S ig n a l
F re q u e n c y
Figure D.4 - Narrowband interference rejection
78
Wideband interference can be caused by the cross correlation of different spreading codes during
transmission in the same channel. In multiple access systems such as CDMA, orthogonal spreading codes
are used such that simultaneous users’ spreading codes do not interfere with each other. Coding theory
provides different sets of codes such as Gold codes, Walsh codes, and maximum length (ML) codes, all of
which have different cross-correlation and autocorrelation properties, as discussed in detail in ref. [50].
Since the study of spreading codes is outside the focus of this paper, we will conclude by stating that codes
with high autocorrelation values and low cross-correlation values are favorable.
A basic spread spectrum receiver, depicted in Figure D.5, multiplies the received signal r(t), with a local
replica of the transmitter’s PN sequence, c(t), to despread the signal and recover the original data symbols.
The local oscillator (LO) at the receiver is assumed to be synchronized to the LO at the transmitter. In an
actual system the receiver would use a phase-locked loop (PLL) to acquire the phase and frequency of the
carrier so that the dispreading process would commence at the maximum signal to noise ratio (SNR).
S p re a d
S y m b o ls
R e c e iv e d
S y m b o ls
ADC
C h ip C lo c k
PN
G e n e ra to r
Figure D.5 - Basic DS receiver architecture
r (t )c(t ) = d (t ) + i (t )c(t )
(D.3)
As (3) demonstrates, the interference, i(t), added by the channel, is spread by the receiver as the data is
being despread. Figure D.6 illustrates the effect of despreading on narrowband interference:
79
S p e c tra l
d e n s ity
S ig n a l
In te r fe r e r
F re q u e n c y
Figure D.6. Narrowband interference spreading
DS spread spectrum systems have many other attractive features other than interference rejection.
These include security, which was the reason for their invention. This stems from the fact that to an
unwanted listener (preferably without knowledge of the spreading code) the transmitted signal is hard to
differentiate from noise. Also, it has been shown that higher data rates and higher user capacity are
possible with DS-based systems. For that reason CDMA has bean steadily gaining popularity over its
competitor, GSM (Global System for Mobile Communication).
D.2 PN Sequences
Zero-mean White Gaussian Noise (WGN) has the same power density
GWGN ( f ) for all frequencies.
The adjective “white” is used in the sense that white light contains equal amounts of all frequencies within
the visible band of electromagnetic radiation. The autocorrelation function of WGN is given by the inverse
Fourier transform of the noise power spectral density
Ra WGN (τ ) =
∞
∫ WGN (t ).WGN (t + τ ).dt
−∞
GWGN ( f ) :
= F −1{GWGN ( t )} =
N0
δ (τ )
2
(D.4)
80
The autocorrelation function
RaWGN (τ ) is zero for τ = 0. This means that any two different samples
of WGN, no matter how close together in time they are taken, are uncorrelated. The noise signal WGN( τ )
is totally decorrelated from its time-shifted version for any τ = 0.
The amplitude of “integrated” (bandlimited) WGN has a Gaussian probability density distribution
p(WGN):
p (WGN ) =
1
1 n
exp( ( ) 2 )
2 σ
σ 2π
(D.5)
A PN code sequence acts as a noise-like but deterministic carrier used for bandwidth spreading of the
signal energy. The selection of a good code is important, because type and length of the code sets bounds
on the system capability. The PN code sequence is a pseudo-noise or pseudo-random sequence of 1’s and
0’s, but not a real random sequence due to its periodicity. Random signals cannot be predicted. The
autocorrelation of a PN code has properties similar to those of white noise.
The PN sequence is therefore not random, but it looks random for the user who has no intelligence of
the code. The PN sequence is deterministic, thus it is known to both the receiver and transmitter. The
longer the period of the PN sequence, the closer will the transmitted signal be to a truly random binary
wave and the harder it is to detect.
Direct sequence spreading can be done with short or long PN sequences. A short PN sequence,
N C . chips long, has a period equal to that of the symbol TS . Therefore, N C .TC = TS where TC is the
chip period. A long code on the other hand has a length several symbols long,
N C .TC >> TS therefore
each symbol is spread by a seemingly different chip pattern.
In each period of a PN sequence, the number of binary ones differs from the number of binary zeros by
at most one digit (for odd
N C . ). When modulating a carrier with a PN sequence, one-zero balanced (DC
component) can limit the degree of carrier suppression obtainable because carrier suppression is dependent
on the symmetry of the modulating signal.
81
The autocorrelation function for a periodic sequence pn, is defined as the number of agreements less the
number of disagreements in a term by term comparison of one full period of the sequence with a cyclic
shift (position
Ra(τ ) =
τ ) of the sequence itself.
N C TC / 2
∫ pn(t ). pn(t + τ ).dt
(D.6)
− N C TC / 2
It is best if Ra( τ ) is not longer than one count if not synchronized ( τ =0). For PN sequences the
autocorrelation has a large peaked maximum only for perfect synchronization of two identical sequences.
This property is used to synchronize the receiver’s PN sequence to that of the transmitter in direct sequence
systems.
Cross-correlation describes the interference between sequences
Rc(τ ) =
N C TC / 2
∫ pn (t ). pn
i
j
pni . and pn j . :
(t + τ ).dt
(D.7)
− N C TC / 2
When the cross-correlation Rc( τ ) is zero for all
τ , the sequences are called orthogonal.
In CDMA users
occupy the same RF bandwidth and transmit simultaneously. When the user spreading sequences are
orthogonal, there is no interference between the users after dispreading and the privacy of the
communication of each user is protected.
In practice the sequences are not perfectly orthogonal, hence the cross-correlation between user
sequences introduces performance degredation (increased noise power after despreading). This limits the
maximum number of simultaneous users in the system.
There are many types of spreading sequences and methods of producing them. The first type that we
will explore is the m-sequence generated by a simple shift register, such as the one in Figure D.7:
82
f ( x1 , x2 ,..., xn ) = c1 x1 + c2 x2 + ... + cn xn
out
1 2
n
Figure D.7 – shift register m-sequence generator
This m-sequence generator is linear if the feedback function can be expressed as a modulo-2 sum (xor).
The feedback function
cells with
f ( x1 + x 2 + ... + x n ) is a modulo-2 sum of the contents xi of the shift register
ci being the feedback connection coefficients. A simple shift register generator with L flip-
flops produces sequences that depend upon register length L, feedback tap connections and initial
conditions. When the period (length) of the sequence is exactly N C = 2 − 1 the PN sequence is called a
L
maximum-length sequence or simply an m-sequence. An m-sequence generated from a linear SSRG has an
even number of taps.
The autocorrelation peak increases with increasing length,
N C , of the m-sequence and approximates
the autocorrelation function of white noise. Other codes can do no better than equal this performance of msequences. However m-sequences have major drawbacks that limit their utility. Their linearity means that
they are easily decipherable once a short sequential set of chips (2L-1) from the sequence is known. This
could be overlooked in some applications where the data is encrypted, or where eavesdropping is not a
concern, if not for the poor cross-correlation properties of m-sequences. Poor cross-correlation leads to
multiple user interference (MUI) in multiple access environments such as CDMA.
The autocorrelation properties of the m-sequence cannot be bettered. But, a multi-user environment
such as CDMA needs a set of codes with the same length and with good cross-correlation properties. Gold
code sequences are useful because a large number of sequences with the same length and with controlled
cross-correlation can be generated, although they require only one pair of feedback tap sets. Gold codes are
product codes achieved by the exclusive or-ing (modulo-2 adding) of two maximum-length sequences with
83
the same length (factor codes). The code sequences are added chip by chip by synchronous clocking.
Because the m-sequences are of the same length, the two code generators maintain the same phase
relationship, and the codes generated are of the same length as the two base codes which are added
together, but are non-maximal (so the autocorrelation function will be worse than that of m-sequences).
Every change in phase position between the two generated m-sequences causes a new sequence to be
generated.
m-sequence 1 (τ = 0)
Gold Sequence
CLK
m-sequence 2 (τ = kTC )
Figure D.8 – Gold code sequence generator
Any 2-register Gold code generator of length L can generate
two base m-sequences, giving a total of
2 L − 1 sequences of length 2 L − 1 plus the
2 L + 1 sequences. In addition to their advantage in generating
large numbers of codes, the Gold codes may be chosen so that over a set of codes available from a given
generator the autocorrelation and cross-correlation between the codes is uniform and bounded.
Another set of important PN sequences are the Hadamard-Walsh codes. These are generated in a set of
N=
2 n codes with length N = 2 n . The generating algorithm is simple:
HN
=
H N /2 H N /2
H N / 2 H −N / 2
With
The rows or columns of the matrix
H0
=
1
H N are the Hadamard-Walsh codes. In each case the first row of
the matrix consists entirely of 1s and each of the other rows contains N/2 0s and N/2 1s. Row N/2 starts
with N/2 1s and ends with N/2 0s. The distance (number of different elements) between any pair of rows is
exactly N/2. For example for
H 8 the distance between any two rows is 4, so the Haming distance of the
84
Hadamard code is 4. The Hadamard-Walsh code can be used as a block code in a channel encoder: each
sequence of n bits identifies one row of the matrix (there are N =
2 n possible rows. All rows are mutually
orthogonal:
N −1
∑h
k =0
ik
.h jk = 0
(D.8)
for all rows I and j. The cross-correlation between any two Hadamard-Walsh codes of the same matrix is
zero when perfectly synchronized.
In a synchronous CDMA system, this ensures that there is no
interference among signals transmitted by the same station.
good orthogonal properties.
Only when synchronized, these codes have
The codes are periodic, which results in less spreading efficiency and
problems with synchronization based on autocorrelation.
In general, m-sequences are useful in systems where there are few users because of their good
autocorrelation, and poor cross-correlation properties. Gold codes and Walsh codes are useful in multi-user
environments because they exhibit much better cross-correlation properties.
D.3
PN Synchronization
The most sensitive aspect of a DS system is the synchronization of the transmitter’s PN sequence to that of
the receiver. This can easily be inferred from Figure 1, where an offset of even one PN chip can result in
noise rather than a despread symbol sequence. Synchronization is composed of two elements: namely
acquisition and tracking. These can be viewed as the alignment of the PN sequences, and the maintenance
of this aligned state.
Synchronization systems use correlators to determine the correlation of the received signal to the local
replica of the transmitted PN sequence. When a high correlation value is detected, acquisition has been
achieved.
As indicated on Figure D.7, the point at which this decision is made (A) depends on a
predetermined threshold value.
85
C o r r e la t io n
V a lu e
B
A
T h re s h o ld
T im e
Figure D.9 - Correlation of received signal to PN
If no tracking system were present, the receiver would sample the correlation value at symbol intervals
of point A on Figure D.9. However, channel delay can cause the correlation value to drop bellow the
threshold at these sampling instances, and cause the system to fall out of acquisition. Therefore acquisition
is often referred to as “coarse synchronization.” A tracking loop modifies the sample timing so that
sampling of the correlation value occurs at the waveform’s peak (B). Thus tracking is often referred to as
“fine synchronization.”
Correlator architectures are often categorized as either serial (active) or parallel (passive). Serial
correlators multiply the received signal with the local PN sequence and accumulate the result on a chip-bychip basis for the duration of a symbol. If the required threshold is not met by the correlation value, a new
correlation process is initiated. Thus for a PN sequence of length
seconds, it could take up to
N C chips, and a symbol duration of TS
N C TS seconds to achieve acquisition. Parallel correlator architectures are
based on matched filters. These devices are based on an FIR structure with the PN sequence serving as the
filter tap coefficients. As the received spread chip sequence slides through the input buffer, the chip-bychip multiplications are done in parallel. Thus it takes at most one symbol duration
acquisition.
TS to achieve
86
The main advantage of the serial correlator is its small circuitry. Such devices can be implemented in a
fraction of the size of a matched filter structure. However steady miniaturization of VLSI technology has
reduced the importance of this advantage. Therefore it is not uncommon today to find a 512-tap matched
filter correlator (WCDMA). Speed and flexibility lend the DMF obvious superiority.
D.3.1
The Digital Matched Filter
Matched filters were initially implemented in analog technologies such as surface acoustic wave (SAW)
devices or charge-coupled devices (CCD). More recently advances in VLSI technology have made digital
matched filters (DMF) most attractive. Figure D.10 depicts a typical matched filter structure.
T ap ped D elay Line
r(n )
O u tp ut
c(n )
PN co de co efficien ts
Figure D.10. Typical digital matched filter
This finite impulse response (FIR) structure convolves the tap coefficient sequence c(n), with the spread
received sequence r(n) according to (D.9):
y ( n) =
m
∑ r ( k )c ( n − k )
k = −∞
(D.9)
87
As the r(n) sequence slides through the tapped delay line, the asynchronous multiply and accumulate
process calculates the correlation value. Thus a new correlation value is calculated at each chip interval.
The polarity of the correlation peak, determines the polarity of the despread data symbol.
D.3.2
Delay-Locked Loop
A time varying transmission channel can cause delays in the received DS spread spectrum signal. This in
turn causes the previously acquired PN sequence to fall out of acquisition if no sampling time correction
mechanism is used. This mechanism is the tracking circuitry.
The delay-locked loop (DLL), sometimes called the “early-late gate”, is a common device used for
tracking in DS systems. As shown in Figure D.11, it consists of two branches, each very much similar to
the acquisition circuitry.
Tim ing
E rror
Input sequence
D M FE
() 2
+
D M FL
LF
() 2
NC O
Figure D.11. Delay-locked loop
The upper branch in Figure D.11, called the “early branch” employs a replica of the DMF used in the
acquisition circuit, except that its PN sequence is advanced by a fraction of one chip period. This fraction
depends on the over-sampling rate of the PN. In this project, an over-sampling rate of 16 was used. The
DMF used by the bottom branch, called the “late branch” contains the same PN sequence, however
retarded by a fraction of a chip period.
We can intuitively see that if the incoming signal is on time, the acquisition branch of Figure 10 will
sample at the peak correlation value and the two DLL branches’ outputs will be equal, causing no error. If
88
however, the incoming signal is delayed, one of the two branches of the DLL will output a higher value
than the other. The difference of the two outputs, known as the timing error, is averaged out by the loop
filter to produce the dc value. The sign and magnitude of this dc value then determines how much the
phase of the NCO must be corrected to eliminate the timing error.
The timing error sometimes exhibits erroneous jitter that can mislead the NCO’s timing circuitry. The
FIR filter shown in Figure 12, is used to average out the timing error, e(n), so that a more accurate delay
measurements, z(n), reaches the NCO.
D.4
The RAKE Receiver
One of the major problems faced by wireless receivers is multipath. When a signal is transmitted it takes
multiple paths to reach the receiver. As shown in Figure D.12, it takes the direct path (if there is one) as
well as other paths by reflecting off of objects. This leads several copies of the signal arriving at the
receiver with small time delays in between.
Diffraction
Scattering
Tree
Reflection
Figure D.12 – A typical multipath environment
89
The strength of the transmitted signal is thus divided into the multipath components arriving at the
receiver with variable time delays. A simple receiver would sense a low signal to noise ratio and be
confused by the incoming multipath components. The RAKE receiver on the other hand, uses a clever
method to take advantage of the multipath rather than to suffer from it. As shown in Figure D.13, the
RAKE is composed of many branches, called “fingers”, each comprising of a correlator for acquisition and
an additional two correlators for tracking.
w1
delay
d1
Synchronization
w2
Multipath signal
delay
d2
output
Synchronization
wn
delay
dn
Synchronization
Figure D.12 – RAKE receiver
The RAKE fingers are separated from each other by estimated channel delays. The correlation value
produced by the correlators is then weighed according to their likelihood. These values are then added to
produce a maximum SNR.
APPENDIX E
DSSS BASEBAND TRANSCEIVER DESIGN IN VERILOG HDL
E.1 DSSS Transceiver Architecture
As discussed in Appendix D, the most important issue in DSSS systems is PN code synchronization at the
receiver. In this appendix, the design and implementation of a code synchronization system based on
digital matched filters (DMFs) will be presented.
The receiver design consists code acquisition and
tracking mechanisms based on DMFs. The acquisition circuitry serves the additional role of spectrum
spreading at the receiver, and can be reused at the transmitter for spectrum dispreading. The tracking
circuitry at the receiver is based on a delay-locked loop architecture.
E.2 Digital Matched Filter implementation in Verilog HDL
In the digital implementation of the matched filter, the input sequence is a stream of zeros and ones. Thus
the proposed design uses XOR operations in the place of multiplications. Further, as illustrated by Figure
E.1, the accumulate process is altered so as to reproduce the bipolar correlation output that would result if
±1 inputs were used.
90
91
T a p p e d D e la y L in e
r(n )
XO R
XOR
XOR
XO R
c (n )
1
+1
0
-1
O u tp u t
P N c o d e c o e ffic ie n ts
Figure E.1 - Implementation of DMF
The symbol-length PN code used was a 16 bit random sequence generated by Matlab. Given a nominal
data over-sampling rate of 16, a 256-tap DMF was needed. This was accomplished with the use of a 256bit static register that holds over-sampled PN sequence, a 256 bit shift register to hold the data, 256 XOR
gates, and a 256 bit parallel adder. The shift register used to shift in the input data could be reused in all of
the DMF instantiations.
The output range of the 256- tap DMF is {-256, 256}. Large positive or negative correlation values
signify the reception of a valid symbol. Thus it can be intuitively justified to state that if a random
sequence uncorrelated with the PN sequence were input to the DMF, the correlation value would be around
zero. Since the input is random, it is fair to guess that half of the 256 XOR operations would result in high
outputs and the rest in low outputs. An equal number of zeros and ones result in a zero output according to
the scheme of Figure E.1.
E.3 DMF Based Acquisition System
The DMF serves as the critical element in the PN acquisition system shown in Figure E.2, as it
performs the crucial task of correlating the spread received sequence with the local replica of the PN
sequence. The bipolar output of the DMF is squared to create a unipolar sequence with an increased range
(from {-256,256} to {0,65536}). This increased range helps the detector’s decision-making.
92
Despread
Detector
1
output
Threshold
Input sequence
DMF
() 2
0
NCO
ACQ
Figure E.2 - DMF based PN acquisition system
Many different thresholds were used in the experimentation. For example, to prove the functionality of
the DMF, a threshold of 256 x 256 = 65,536 was used. When noise and channel delay were considered,
this threshold was lowered to around 25,000. As stated earlier, proper threshold design falls outside the
scope of this project, thus it was left for later work.
Before acquiring the PN sequence, the threshold constantly compares the received signal to its
threshold. Once this threshold has been met (acquisition has been achieved) the detector sends a signal to
the tracking circuit to start the tracking process. From this point on, the threshold comparison is done at
symbol intervals. This is where the numerically controlled oscillator (NCO) comes in. It pulses the
detector at every symbol period so that the detector can do its threshold comparison and output the
despread data if still in acquisition.
In this design, the NCO is modeled as a counter that counts at the chip rate up to its maximum value of
255. When this expires, it activates the detector. The period of the NCO can be altered by the tracking
circuitry, which will be our next topic of discussion.
E.4 Delay-Locked Loop Based Tracking System
A time varying transmission channel can cause delays in the received DSSS signal. This in turn causes
the previously acquired PN sequence to fall out of acquisition if no sampling time correction mechanism is
used. This mechanism is the tracking circuitry.
93
The delay-locked loop (DLL), sometimes called the “early-late gate”, is a common device used for tracking
in DS systems. As shown in Figure E.3, it consists of two branches, each very much similar to the
acquisition circuitry.
Tim ing
E rror
Input sequence
D M FE
() 2
+
D M FL
LF
() 2
NC O
Figure E.3 - Delay-locked loop
The upper branch of the DLL, called the “early branch” employs a replica of the DMF used in the
acquisition circuit, except that its PN sequence is advanced by a fraction of one chip period. This fraction
depends on the over-sampling rate of the PN. In this project, an over-sampling rate of 16 was used. The
DMF used by the bottom branch, called the “late branch” contains the same PN sequence, however
retarded by a fraction of a chip period.
We can intuitively see that if the incoming signal is on time, the acquisition branch in Figure E.2 will
sample at the peak correlation value and the two DLL branches’ outputs will equal, causing no error.
If
however, the incoming signal is delayed, one of the two branches of the DLL will output a higher value
than the other. The difference of the two outputs, known as the timing error, is averaged out by the loop
filter to produce the dc value. The sign and magnitude of this dc value then determines how much the
phase of the NCO must be corrected to eliminate the timing error.
94
E.5 Loop Filter
The timing error sometimes exhibits erroneous jitter that can mislead the NCO’s timing circuitry. The
FIR filter shown in Figure E.4, is used to average out the timing error, e(n), so that a more accurate delay
measurements, z(n), reaches the NCO.
Tapped Delay Line
e(n)
z(n)
h(n)
Tap coefficients
Figure E.4 - Loop filter implementation
z (n) = e(n)h(0) + e(n − 1)h(1)
(E.1)
The loop filter used in this project was designed to be a compromise between practicality and
performance. The two-tap structure shown in Figure E.4, was expected to exhibit the impulse response of
Figure E.5, according to Matlab simulations. This shows that frequencies less than 5KHz or so, pass
through unharmed. However high frequency components, especially those above 30 KHz or more, suffer
more than 10 dB of attenuation.
95
Figure E.5 - Impulse response of loop filter
The ease of design of this filter in Verilog is worth mentioning. Since tap coefficients are sub-multiples
of 2 (1/2 and 1/2), the two multiplications can be replaced by shifting. That reduces the filtering operation
down to one major task, addition.
E.6
Overall System
The overall system block diagram is shown in Figure E.6. The incoming bit-stream would usually come
from an ADC. The acquisition branch of the circuit would be used to acquire the incoming PN code, and
once this is accomplished, the detector outputs the despread data sequence. This branch can be reused in
transmit mode to spread the data stream before transmission.
96
Acq u is itio n
D ete cto r
1
T h re sh o ld
() 2
DMF
0
T ra c k in g
In p u t s eq u e n ce
NCO
AC Q
() 2
D M FE
DLL
D M FL
+
()
LF
2
Figure E.6 - Complete synchronization system
This system is based on a single user, dual-phase system such as binary phase shift keying (BPSK). In
CDMA, RAKE receivers are used for synchronization of quad-phase signals using quadrature phase shift
keying (QPSK) modulation. These receivers vary in complexity with increasing number of branches or
“fingers.” A basic RAKE finger is usually very much similar to the system designed in this project. To
take advantage of multi-path effects in a white-Gaussian noisy channel, each finger is separated from the
next by a delay element. The outputs of all individual fingers are given weights, and then summed up to
produce an output signal with maximum SNR.
E.7
Simulation Results
In this section, we provide simulation results to verify our designs discussed in the above sections. We
not only implemented the whole code synchronization system using Verilog hardware description
language, but also implemented it using Matlab in order to verify our hardware design. We start with
addressing the digital matched filter simulation. We then present the Cadence and Verilogger simulation
results for the delay-locked loop circuit as well as the Matlab simulation results. Analytical comparisons
between software and hardware simulation results are also provided. Finally, we present the S-curve
performance of the DLL circuits and noise performance of the whole system.
97
All results given in this section are for a DS-CDMA system with a randomly generated PN code of
length 16 chips. In order to focus on the code synchronization function, we only considered the single user
BPSK scenario and ignored any multi-path or other channel fading. The received signal was spread with a
processing gain of 16 and over-sampled by a factor of 16. For the sake of simplicity, we did not consider
pulse shaping. Additive white Gaussian noise (AWGN) was added to the received signal only when noise
performance was investigated.
E.7.1
DMF Performance
First, the performance of the DMF design was verified via Cadence and Matlab simulation. Altogether
10 symbols were used with a spreading factor of 16 and over-sampling rate of 16. We can see from Figure
E.7 that the simulation results of Matlab and those of Cadence are almost identical.
Figure E.7 - Comparison of simulation results of the DMF on Matlab (top) and Cadence (bottom)
98
The actual symbols we received are [1, –1, 1, 1, –1, –1, 1, –1, 1, –1]. We can see that the positive and
negative peaks of the matched filter output exactly represent the actually received symbols, which verified
our DMF design.
E.7.2
Performance of the DLL
The DLL is the heart of the tracking circuitry. The following simulation results show that our design of
DLL works well, both in Verilog and Matlab. Figure E.8 shows the instance when acquisition was obtained
at time 5.38us and the ACQ signal went high; detector outputted S0 = 1, S1 = 0, indicating a symbol “0”
was received.
5.37us
5.38us
5.39us
5.40us
5.41us
5.42us
5
testsynch.CLK
testsynch.S0
testsynch.S1
testsynch.ACQ
testsynch.counter[8:0
1FF
0
8E81
B139
testsynch.delay[1:0]
testsynch.Y2[16:0]
6F91
testsynch.Y2e[16:0]
5221
6CF1
8B89
testsynch.Y2l[16:0]
8B89
ADE9
D411
estsynch.filterout[17:0
35A0
testsynch.filterin[17:0
3968
3968
3D30
40F8
40F8
44C0
4888
4888
Figure E.8 - First instance of acquisition
For this particular simulation, the threshold of 61A8 hex (25,000) was surpassed by a squared
correlation (Y2) value of 6F91 (28,561), thus acquisition was achieved. However the peak correlation
value is 10000 hex (65,536 = 256 x 256). In the following figures, we will witness the operation of the
DLL. Before we move on to the next timing diagram, notice the difference in the values of Y2e and Y2l,
which are the outputs of the early and late branches of the DLL, respectively. In this case, the late branch
surpasses the early branch, thus the received PN is late. Thus the next NCO period will be longer to
compensate for this. This can be seen from the fact that the counter (fifth signal from the top) starts
counting from –1 (1FF) rather than 0.
99
10.51us
10.52us
10.53us
10.54us
10.55us
10.56us
1
testsynch.CLK
testsynch.S0
testsynch.S1
testsynch.ACQ
testsynch.counter[8:0]
FF
1FF
0
testsynch.Y2[16:0]
8D04
AF90
D5E4
testsynch.Y2e[16:0]
6BA4
8A10
AC44
testsynch.Y2l[16:0]
AC44
D240
FC04
testsynch.delay[1:0]
estsynch.filterout[17:0
3CD8
testsynch.filterin[17:0]
40A0
4468
40A0
4830
4BF8
4830
4FC0
4FC0
Figure E.9 - One symbol period after Figure E.9
One symbol period later, the ACQ signal is still high; the detector output flops, S0 = 0, S1 = 1,
indicating a symbol “1” was received.
Notice that at the sampling instant (when count = FF), the
correlation value is now 8D04 (36,100). The late branch still dominates, thus we once again lengthen the
NCO’s period. We continue this process until we reach the state of Figure E.10.
25.93us
25.94us
25.95us
25.96us
25.97us
25.98us
testsynch.CLK
testsynch.S0
testsynch.S1
testsynch.ACQ
testsynch.counter[8:0]
FF
testsynch.delay[1:0]
0
1
0
testsynch.Y2[16:0]
10000
D240
A900
testsynch.Y2e[16:0]
D240
10000
D240
testsynch.Y2l[16:0]
D240
A900
8440
estsynch.filterout[17:0
testsynch.filterin[17:0]
27E0
0
0
22B80
3A900
25700
25280
24E00
3B200
Figure E.10 - dll locks when early and late branches output same correlation value
2
100
In Figure E.10 we can see that the DLL “locks” on to the incoming PN sequence, and from this point
on, sampling occurs at the peak correlation value of 10000 (65,536). Also notice the bottom two signals in
Figure E.10 Filterin and Filterout, respectively. The input and output to the loop filter at the point that the
DLL locks, are both zero. The DLL lock time for this particular simulation was four symbol periods.
Figure E.11 - Matlab simulation of the DLL
It is seen from Figure E.11 that the Matlab implementation of the DLL circuit works well, similar to the
Verilog implementation. The first four peaks didn’t reach the maximal score because of the timing offset.
Thus the “delay” signal becomes “one” indicating this timing offset. After four symbols, all the peaks
reached the maximal score, indicating DLL had finished its job and the PN codes were lined up. Thus the
DLL works well, adjusting the delay one chip per symbol period. Experimentation with quantizers at the
output of the loop filter lead to lock times of one symbol period for some specialized cases.
The S-curve is an important performance indicator for the DLL. It displays the maximum range of the
DLL, and how much delay it can adjust. Figure E.12 shows the S-curves of the Matlab, and Cadence
simulated DLL circuits. Both curves display reasonable S-curve characteristics. When there exists positive
delay (late), the DLL outputs a positive number; when there exists negative delay (early), the DLL outputs
a negative number.
101
Figure E.12 - S-curve derived from the Matlab (top) and Cadence (bottom) simulations
Once the delay surpasses a certain limit, and the DLL cannot keep up, acquisition may be lost. When
acquisition is lost during the tracking process, the entire acquisition process is restarted.
E.7.3
Overall System Performance
The overall system of Figure 14 worked beautifully in both the Matlab and Cadence implementations. The
acquisition system successfully acquired the PN sequence and recovered the data symbols, and the DLL
adjusted for delay and tracked the incoming PN code.
Figure E.13 displays a simulation window of the
Signalscan simulator showing the recovered symbols.
The same simulation was done in Veriloger, as
displayed in Figure E.14.
102
Figure E.13 - System simulation on Cadence/Signalscan
0us
5us
10us
15us
synch.threshold[16:0
20us
25us
30us
35us
40u
4000
testsynch.S0
testsynch.S1
testsynch.ACQ
estsynch.counter[8:0
0
0
testsynch.delay[2:0]0 0 01 1 1 1 1
1 1 1
1 1 1
1 1 1
1 1 1 1 1 11 0 0
0
testsynch.Y2[16:0]
441
testsynch.Y2e[16:0]
441
testsynch.Y2l[16:0]
441
Figure E.14 - System simulation on Veriloger
Veriloger and Cadence/Signalscan offer different advantages to the beginning Verilog designer. The
Cadence/Signalscan combination provides an industry standard product that can be used to analyze some of
the real world aspects of application specific integrated circuit (ASIC) design. Veriloger on the other hand
103
is more suited for beginners in the field and thus is ideal as a classroom tool. It is much more user-friendly
than its competitor because it is Windows based.
E.8
System Performance In The Presence Of Noise
We also investigated the noise performance of the whole system by introducing additive white Gaussian
noise (AWGN) into the received signals. Figure E.15 shows that the bigger the noise variance, the worse
the system performance will be. Please note that noise combat is not the main purpose of our code
synchronization system, which should be the job of Error Correction Code (ECC) and equalization.
However, it is seen that our system has a fairly decent noise performance. For example, at a noise variance
of 2 that translates to a SNR of about 8 dB, we have a bit error rate (BER) less than 0.02. It is not bad as a
French function for a code synchronization system. Assuming noise-free situation, we achieved a BER of
0, which shows that the code synchronization function did its job very perfectly.
Figure E.15 - System noise performance
104
E.9
Conclusion
In this project, we implemented the DS/CDMA code synchronization system including the matched
filter, detector, loop filter, DLL, and NCO. The whole system was implemented in both Verilog and
Matlab. Computer simulations using Cadence and Matlab were provided to verify our design. Logic
diagrams and performance analysis show that the design is successful in all its functions and also achieves
decent performance under a noisy environment.
One possible area of improvement is the design of the loop filter. Improvement of this device will lead
to the accurate translation of filter output to multi-step delay adjustment using a lookup table based NCO.
In that case, we would be able to achieve DLL locking after just one symbol period. With the present
design, the DLL adjusts delay one chip per symbol period.
The present design in Verilog is mostly limited to the behavioral level; future work can be done to
further implement it in structural level. For the time being, we don’t take care of the pulse shaping and
multi-path fading elements of the receiver design. Future work can be done to implement root-raised
cosine pulse shaping and Error Correction Coding in order to obtain a more complete receiver system.
E.10 Verilog HDL Code
`timescale 1ns/1ns
`define clk 10
//chip clock
`define fclk 5
//filter clock --> frequency = 2 x chip clock
///////////////////////////////////////////////////////////
module sreg(X, CLK, RES, XREG);
//shift register that holds last 256 chips
parameter length = 256;
input X;
//serial overshampled input chips
input CLK;
//chip clock
input RES;
//reset signal used to initialize register
output [length-1:0] XREG;
//parallel contents of shift register are output
105
reg [length-1:0] XREG;
always @(posedge CLK or posedge RES)begin //execute at chip rate
if (RES)
XREG = 0;
else
XREG = {X , XREG[length-1:1]};
//shift new chip as MSB, shift out LSB
end
endmodule
//////////////////////////////////////////////////////////
module macc(XREG, HREG, Y, result);
//multiply and accumulate module determins the
//degree of correlation between PN and input data
parameter length = 256;
input [length-1:0] XREG;
input [length-1:0] HREG;
//holds PN sequence
output [9:0] Y;
//output correlation value -256 to +256
output [8:0] result;
//temperary variable 0 to 256
reg [length-1:0] product;
//temperary variable holds xor values 256 bits
reg [8:0] result;
reg [9:0] Y;
initial result=0;
always@(XREG or HREG)begin
//execute correlation when inputs change
product = XREG ^ HREG;
result =
product[length-1]+product[length-2]+product[length-3]+product[length-4]+
product[length-5]+product[length-6]+product[length-7]+product[length-8]+
product[length-9]+product[length-10]+product[length-11]+product[length-12]+
product[length-13]+product[length-14]+product[length-15]+product[length-16]+
106
product[length-17]+product[length-18]+product[length-19]+product[length-20]+
product[length-21]+product[length-22]+product[length-23]+product[length-24]+
product[length-25]+product[length-26]+product[length-27]+product[length-28]+
product[length-29]+product[length-30]+product[length-31]+product[length-32]+
product[length-33]+product[length-34]+product[length-35]+product[length-36]+
product[length-37]+product[length-38]+product[length-39]+product[length-40]+
product[length-41]+product[length-42]+product[length-43]+product[length-44]+
product[length-45]+product[length-46]+product[length-47]+product[length-48]+
product[length-49]+product[length-50]+product[length-51]+product[length-52]+
product[length-53]+product[length-54]+product[length-55]+product[length-56]+
product[length-57]+product[length-58]+product[length-59]+product[length-60]+
product[length-61]+product[length-62]+product[length-63]+product[length-64]+
product[length-65]+product[length-66]+product[length-67]+product[length-68]+
product[length-69]+product[length-70]+product[length-71]+product[length-72]+
product[length-73]+product[length-74]+product[length-75]+product[length-76]+
product[length-77]+product[length-78]+product[length-79]+product[length-80]+
product[length-81]+product[length-82]+product[length-83]+product[length-84]+
product[length-85]+product[length-86]+product[length-87]+product[length-88]+
product[length-89]+product[length-90]+product[length-91]+product[length-92]+
product[length-93]+product[length-94]+product[length-95]+product[length-96]+
product[length-97]+product[length-98]+product[length-99]+product[length-100]+
product[length-101]+product[length-102]+product[length-103]+product[length-104]+
product[length-105]+product[length-106]+product[length-107]+product[length-108]+
product[length-109]+product[length-110]+product[length-111]+product[length-112]+
product[length-113]+product[length-114]+product[length-115]+product[length-116]+
product[length-117]+product[length-118]+product[length-119]+product[length-120]+
product[length-121]+product[length-122]+product[length-123]+product[length-124]+
product[length-125]+product[length-126]+product[length-127]+product[length-128]+
107
product[length-129]+product[length-130]+product[length-131]+product[length-132]+
product[length-133]+product[length-134]+product[length-135]+product[length-136]+
product[length-137]+product[length-138]+product[length-139]+product[length-140]+
product[length-141]+product[length-142]+product[length-143]+product[length-144]+
product[length-145]+product[length-146]+product[length-147]+product[length-148]+
product[length-149]+product[length-150]+product[length-151]+product[length-152]+
product[length-153]+product[length-154]+product[length-155]+product[length-156]+
product[length-157]+product[length-158]+product[length-159]+product[length-160]+
product[length-161]+product[length-162]+product[length-163]+product[length-164]+
product[length-165]+product[length-166]+product[length-167]+product[length-168]+
product[length-169]+product[length-170]+product[length-171]+product[length-172]+
product[length-173]+product[length-174]+product[length-175]+product[length-176]+
product[length-177]+product[length-178]+product[length-179]+product[length-180]+
product[length-181]+product[length-182]+product[length-183]+product[length-184]+
product[length-185]+product[length-186]+product[length-187]+product[length-188]+
product[length-189]+product[length-190]+product[length-191]+product[length-192]+
product[length-193]+product[length-194]+product[length-195]+product[length-196]+
product[length-197]+product[length-198]+product[length-199]+product[length-200]+
product[length-201]+product[length-202]+product[length-203]+product[length-204]+
product[length-205]+product[length-206]+product[length-207]+product[length-208]+
product[length-209]+product[length-210]+product[length-211]+product[length-212]+
product[length-213]+product[length-214]+product[length-215]+product[length-216]+
product[length-217]+product[length-218]+product[length-219]+product[length-220]+
product[length-221]+product[length-222]+product[length-223]+product[length-224]+
product[length-225]+product[length-226]+product[length-227]+product[length-228]+
product[length-229]+product[length-230]+product[length-231]+product[length-232]+
product[length-233]+product[length-234]+product[length-235]+product[length-236]+
product[length-237]+product[length-238]+product[length-239]+product[length-240]+
108
product[length-241]+product[length-242]+product[length-243]+product[length-244]+
product[length-245]+product[length-246]+product[length-247]+product[length-248]+
product[length-249]+product[length-250]+product[length-251]+product[length-252]+
product[length-253]+product[length-254]+product[length-255]+product[length-256];
Y = 2*result-length; //matches add to result, misses subtract from it
end
//this way we get a correlation range of -256 to +256
endmodule
//////////////////////////////////////////////////////////////
module squarer(Y2,Y);
//squares output of macc module, so dynamic range
//increases, matches are more easily detectable
parameter InputLen1 = 10;
parameter InputLen2 = 17;
input [InputLen1-1:0] Y;
output [InputLen2-1:0] Y2;
reg
[InputLen2-1:0] Y2;
reg
[InputLen1-1:0] Yreg;
reg
sbit;
//10 bit signed input
//17 bit unsigned output --> max value is 256 x 256
//temperary variable, 10 bits unsigned
//sign bit of input
always @(Y[InputLen1-2:0]) begin //execute if Y changes
sbit=Y[InputLen1-1];
if (sbit)
Yreg = -Y;
else
Yreg = Y;
Y2 = Yreg*Yreg;
//output equals input squared
end
endmodule
/////////////////////////////////////////////////////////
module detector(CLK,RES,Y2,Y,threshold,ACQ,S0,S1, counter, delay); //determines if and when
109
parameter length = 256;
//acquisition is acheived
parameter InputLen2 = 17;
parameter InputLen1 = 10;
input [InputLen2-1:0] Y2;
input [InputLen1-1:0] Y;
input CLK, RES;
//clocked at the chip rate
input [1:0] delay;
input [InputLen2-1:0] threshold;
//threshold used to determine if acquisition acheived
output ACQ, S0, S1;
//acquisition, S0(0 received), and S1(1 received) outputs
output [8:0] counter;
//counter used for sample timing
reg ACQ, S0, S1;
reg [8:0] counter;
always @(posedge CLK or posedge RES)begin //execute at chip rate
if(RES)begin
//initialize counter, output signals
counter = 0;
ACQ = 0;
S1=0;
S0=0;
end
else if(!ACQ)begin
if(Y2 >= threshold)begin
ACQ = 1;
//if not in acquisition check for threshold crossing
//if crossed threshold
//go into acquisition
if(delay == 0)
//input delay values determine next sampling instant
counter = 0;
//this way we mimic the NCO
else if (delay == 1)
counter = 1;
else if (delay == 3)
//counter counts up to 255 before sampling, delays
//add or subtract from this number
110
counter = 511;
end
S1 = ACQ && ~Y[InputLen1-1] && ~S0;
//if acquisition acheived, S0 and S1
S0 = ACQ && Y[InputLen1-1] && ~S1;
//depend on polarity of correlation
end
else if(ACQ)begin
if(counter == 255)begin
if(Y2 < threshold)
ACQ = 0;
S1 = ACQ && !Y[InputLen1-1];
//if in acquisition execute
//execute at symbol intervals
//if under threshold
//go out of acquisition
//reevaluate S0 and S1
S0 = ACQ && Y[InputLen1-1];
if(delay == 0)
counter = 511;
else if (delay == 1)
//these are offset from the previous adjustments by 1
//because they will be immediately incremented once
//we exit the 'if' statement
counter = 0;
else if (delay == 3)
counter = 510;
end
counter <= counter+1;
end
end
endmodule
///////////////////////////////////////////////
module subtracter(Y2e, Y2l, filterin);
//subtracter module used in DLL
//subtracts early branch from late branch
parameter InputLen2 = 17;
//17 bit unsigned inputs
111
input [InputLen2-1:0] Y2e, Y2l;
output [InputLen2:0] filterin;
//output is fead to the filter
reg [InputLen2:0] filterin;
always@(Y2e || Y2l)
filterin = Y2l - Y2e;
//execute when inputs change
//output is the difference
endmodule
///////////////////////////////////////////////////
module LF(CLK, filterin, delay, RES, filterout); //loop filter used
// in DLL
parameter InputLen2 = 17;
//loop filter is a two tap FIR with taps 1/2 and 1/2
parameter RegLen = 35;
//impulse response is low pass
input [InputLen2:0] filterin;
input CLK, RES;
output [1:0] delay;
output [InputLen2:0] filterout;
reg [InputLen2:0] filin;
reg [3:0] delay;
reg [RegLen:0] inreg;
reg [InputLen2:0] filterout;
always@(CLK or posedge RES)begin
//execute on both edges of filter clock, thus sampling
//frequency of filter is 4 x chip rate
if (RES)begin
delay = 0;
inreg = 0;
filterout = 0;
filin = 0;
112
end
if (!RES) begin
if(filterin[InputLen2])
//begin filtering
//modify numbering system to aid in negative number arithmatic
filin={filterin[InputLen2],~filterin[InputLen2-1:0]+1};
else
filin=filterin;
inreg = {filin[InputLen2], 1'b0, filin[InputLen2-1:1], inreg[RegLen:InputLen2+1]};
//input data register holding the last two samples
if (inreg[RegLen] && inreg[InputLen2] )
//start filtering
filterout = {1'b1,inreg[RegLen-1:InputLen2+1]+inreg[InputLen2-1:0]} ;
else if (inreg[RegLen] && !inreg[InputLen2])begin
if (inreg[RegLen-1:InputLen2+1] > inreg[InputLen2-1:0])
filterout = {1'b1,inreg[RegLen-1:InputLen2+1] - inreg[InputLen2-1:0]};
else if (inreg[RegLen-1:InputLen2+1] < inreg[InputLen2-1:0])
filterout = {1'b0,inreg[InputLen2-1:0]- inreg[RegLen-1:InputLen2+1]};
end
else if (!inreg[RegLen] && inreg[InputLen2])begin
if (inreg[RegLen-1:InputLen2+1] > inreg[InputLen2-1:0])
filterout = {1'b0,inreg[RegLen-1:InputLen2+1] - inreg[InputLen2-1:0]};
else if (inreg[RegLen-1:InputLen2+1] < inreg[InputLen2-1:0])
filterout = {1'b1,inreg[InputLen2-1:0] - inreg[RegLen-1:InputLen2+1]};
end
else if (!inreg[RegLen] && !inreg[InputLen2])
filterout = {1'b0,inreg[RegLen-1:InputLen2+1]+inreg[InputLen2-1:0]} ;
if (filterout == 0)
delay = 0;
//in the absence of a nonlinear quantizer, we adjust
//the delay one chip per symbol
113
else if (filterout[InputLen2])
delay = 1;
else if(!filterout[InputLen2])
delay = 3;
end
end
endmodule
///////////////////////////////////////////////////
module synchronization(Y, X, RES,fCLK,CLK, PN, threshold, xbus, S0, S1, ACQ, delay, Y2, Y2e, Y2l,
filterin, filterout, counter, result);
//DS/CDMA synchronization system
parameter length = 256;
parameter InputLen2 = 17;
//Acquisition uses an sreg, a macc, a squarer, and the detector
//tracking part (DLL) uses two maccs, two squarers, the
//subtractor, the LF, and reuses the sreg
parameter InputLen1 = 10;
input X,RES,fCLK,CLK;
input [length-1:0] PN;
input [InputLen2-1:0] threshold;
output [InputLen2:0] filterin;
output [InputLen2:0] filterout;
output [InputLen2-1:0] Y2,Y2e, Y2l;
output [InputLen1-2:0] counter;
output [InputLen1-2:0] result;
output [InputLen1-1:0] Y;
output S0, S1, ACQ;
output [length-1:0] xbus;
output [3:0] delay;
wire ACQ, S0, S1;
114
wire [InputLen1-1:0] Ye, Yl;
sreg datain(.X(X), .CLK(CLK), .RES(RES), .XREG(xbus));
macc macca(.XREG(xbus), .HREG(PN), .Y(Y), .result(result));
macc macce(.XREG(xbus), .HREG({PN[0], PN[length-1:1]}), .Y(Ye), .result());
macc maccl(.XREG(xbus), .HREG({PN[length-2:0], PN[length-1]}), .Y(Yl), .result());
squarer sqa(.Y2(Y2),.Y(Y));
squarer sqe(.Y2(Y2e),.Y(Ye));
squarer sql(.Y2(Y2l),.Y(Yl));
detector det(.CLK(CLK),.RES(RES),.Y2(Y2),.Y(Y),.threshold(threshold),.ACQ(ACQ),.S0(S0),.S1(S1),
.counter(counter), .delay(delay));
subtracter subtract(.Y2e(Y2e), .Y2l(Y2l), .filterin(filterin));
LF filter(.CLK(fCLK),.filterin(filterin), .delay(delay), .RES(RES), .filterout(filterout));
Endmodule
//////////////////////////////////////////////////////////////////
module testsynch();
reg fCLK,CLK, RES, X;
reg [255:0] PN;
reg [16:0] threshold;
wire S0, S1, ACQ;
wire [8:0] counter;
wire [1:0] delay;
wire [255:0] xbus;
wire [16:0] Y2,Y2e, Y2l;
wire [17:0] filterout;
wire [17:0] filterin;
wire [8:0] result;
wire [9:0] Y;
integer f1;
115
synchronization test(Y,X, RES,fCLK,CLK, PN, threshold, xbus, S0, S1, ACQ, delay, Y2, Y2e, Y2l,
filterin, filterout, counter, result);
initial
begin
//f1 = $fopen("./in1.txt");
//$log("./in1.txt");
f1 = $fopen("./out1.txt");
$log("./out1.txt");
end
initial begin
//$monitor ($time,, "Y=%b, X=%b, RES=%b, fCLK = %b, CLK=%b, PN=%b, threshold=%b, xbus=%b,
S0=%b, S1=%b, delay=%b, //Y2=%b, Y2e=%b, Y2l=%b, filterin=%b, filterout=%b, counter=%b,
result=%b",
// Y, X, RES, fCLK, CLK, PN, threshold, xbus, S0, S1, ACQ, delay, Y2, Y2e, Y2l, filterin, filterout,
counter, //result);
//$monitorh("%h",filterin);
$monitorh("%h",filterout);
fCLK = 0; CLK=0; RES=1;
threshold=25000;
//threshold= 65536;
PN=256'hffff0000ffff0000ffff0000ffffffff0000ffffffff0000ffffffff00000000;
X=0;
#12 RES=0;
#320 X=0;
116
#320 X=0;
#320 X=1;
// Add more test data here if you want
#320 X=1;
#320 X=1;
#10000 $finish;
end
initial forever #`fclk fCLK <= ~fCLK;
initial forever #`clk CLK <= ~CLK;
endmodule
BIBLIOGRAPHY
[1]
Vincent J. Arkesteijn, Eric A.M. Klumperink and Bram Nauta, “An Analogue Front-End Test-Bed
For Software Defined Rradio,” http://icd.el.utwente.nl/.
[2]
Rupert Baines and Doug Pulley, “A Total Cost Approach to Evaluating Different Reconfigurable
Architectures for Baseband Processing in Wireless Receivers,” IEEE Communications Magazine,
Volume: 41 Issue: 1: January 2003, Page(s): 105 - 113.
[3]
Roc Berengeur, Andres Garcia-Alonso, Guillermo Bistue, Antonio Priego, Frank Oeuler, Gunter
Rohmer, and Javier Hernandez de Miguel, “A Low –Power, CMOS Subharmonic Sampler for a
Direct Digitization GPS Receiver,” Applied Microwave & Wireless, December 2001, Page(s): 24
– 35.
[4]
Brad Brannon, and Chris Cloninger, “Redefining the Role of ADCs in Wireless,” Applied
Microwave & Wireless, March 2001, Page(s): 95-105.
[5]
Chi-Kin Cha and Wong-Hing Lam, “ Efficient use of pseudo-noise sequences in synchronous
direct-sequence spread-spectrum multiple-access communication systems,” In proceedings of the
44th IEEE Conference on Vehicular Technology Conference, Volume: 1, 8-10 June 1994, Page(s):
540 –544.
[6]
David B. Chester and John McCardle, “Delay-Insensitive Logic in Software-Defined Radio
Applications,” IEEE Communications Magazine, Volume.41 Number: 1, January 2003, Page(s)
114-119.
[7]
Peter Clark, “TI plans for a “single-chip” cell phone in 2004,” September 4 2002,
http://www.commsdesign.com/design_center/3gwireless/news/OEG20020904S0030.
[8]
P.G. Cook, and W. Bonser, ”Architectural overview of the SPEAKeasy system,” IEEE Journal on
Selected Areas in Communications, Volume: 17 Issue: 4 April 1999, Page(s): 650 –661.
[9]
M. Cummings, and S. Haruyama ,” FPGA in the software radio,” IEEE Communications
Magazine, Volume: 37 Issue: 2 , February 1999, Page(s): 108 – 112.
[10]
J.P. Dodley, R.H. Erving, and C.W. Rice, “ In-building software radio architecture, design and
analysis, Personal, Indoor and Mobile Radio Communications,” In proceedings of the 11th IEEE
International Symposium on PIMRC, Volume: 1 Issue: 1, 18-21 September 2000, Page(s): 479 –
483.
[11]
Andy Dornan. The Essential Guide to Wireless Communications Applications, Prentice Hall, New
Jersey, 2001.
[12]
Fred Daneshgaran and Massimiliano Laddomada, “Transceiver Front-End Technology for
softwareRadio Implementation of Wideband Satellite Communication Systems,”
http://web.tiscali.it/no-redirect-tiscali/laddomada/downloadFile/frontend.pdf.
117
118
[13]
P.A. Eyermann, “ Joint tactical radio systems-a solution to avionics modernization,”
Proceedings of the 18th Digital Avionics Systems Conference, Volume: 2, 24-29 October 1999
Page(s): 9.A.5-1 -9.A.5-8.
[14]
C.D. Ferris, “Development of a practice-oriented radio-frequency design course,” IEEE
transactions on Education, Volume: 34 Issue: 1, February 1991, Page(s): 118 –122.
[15]
P.J. Green, and D.P. Taylor, “ Smart antenna software radio test system,” In Proceedings of the
First IEEE International Workshop on Electronic Design, Test, and Applications, 29-31
January 2002, Page(s): 68 – 72.
[16]
Allison Haines, “Gartner says frequent users of wireless LANs will total 4.2 million in 2003,”
March 2003, http://www.gartner.com/5_about/press_releases/pr26mar2003a.jsp.
[17]
Gary Hilson, “Smartphone Penetration drives requirements for improved customer support as
more than 1.3 billion people worldwide communicate wirelessly,” August 2003,
http://www.mobilediagnostix.com/archive/20030814-1.shtml.
[18]
X.H. Huang, K.L. Du ,A.K.Y. Lai, and K.K.M. Cheng, “A unified software radio architecture,”
IEEE Third Workshop on Signal Processing Advances in Wireless Communications, 20-23
March 2001, Page(s): 330 –333.
[19]
M.A. Jensen, R.H. Selfridge, and K.F. Warnick, “ System-level microwave design projects,”
IEEE Antennas and Propagation Magazine, Volume: 43 Issue: 5, October 2001 Page(s): 138 –
142.
[20]
B. Kamali, “ Development of an undergraduate structured laboratory to support classical and
new base technology experiments in communications,” IEEE Transactions on Education,
Volume: 37 Issue: 1, February 1994, Page(s): 97 – 100.
[21]
Richard A. Killoy, “Design and Implementation of a Link Level Software Radio,” Degree of
Masters of Science, Engineering, University of Kansas, 1997.
[22]
“Latest Global, Handset, Base Station, & Regional Cellular Statistics,” August 2003,
http://www.cellular.co.za/stats/stats-main.htm.
[23]
MAX2822, 2.4GHz 802.11b Zero-IF Transceiver with Integrated PA and Tx/Rx Switch,
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3938.
[24]
H.C. Miranda, P.C. Pinto, and S.B. Silva, “ A self-reconfigurable receiver architecture for
software radio systems, Radio and Wireless Conference,” In Proceedings of the 2003 IEEE
Radio and Wireless Conference, 10-13 August 2003, Page(s): 241 – 244.
[25]
Joe Mitola, “ Software Radio - Cognitive Radio, Wireless Architectures for the 21st Century,”
http://www.ourworld.compuserve.com/homepages/jmitola.
[26]
“New TI DSP Triples Low-Cost Floating-Point Performance,”
http://www.chipcenter.com/dsp/DSP000921F1.html.
[27]
E. Newman, and D.M. Climek, “Multiband multimode radio (MBMMR) technology
applications in the military, civil, and commercial sectors,” In Proceedings of the 1997 Military
Communications Conference, Volume: 3, 2-5 November 1997, Page(s): 1192 –1196.
[28]
P. Nicopolitidis, M. S. Obaidat, G. I. Papadimitriou, and A. S. Pomportsis, Wireless Networks,
John Wiley and Sons, West Sussex, England, 2003.
119
[29]
Henry W. Ott, Noise Reduction Techniques in Electronic Systems, John Wiley & Sons, New
York, 1976.
[30]
Richard Perry, “Overlooking 3G,” IEEE Potentials, October/November 2002, Page(s): 6-9.
[31]
Thomas G. Pratt, “Georgia Tech Software Radio Laboratory,”
http://www.broadband.gatech.edu/facilities/softwarelab/softwarelab.html.
[32]
Theodore S. Rappaport, Wireless Communications, Principles & Practice, Prentice Hall, PTR,
New Jersey, 1996.
[33]
“RAYTHEON - RADIOS AND TERMINALS,”
http://www.army-technology.com/contractors/navigation/raytheon3/.
[34]
Behzad Razavi, RF Microelectronics, Prentice Hall, New Jersey, 1998.
[35]
“RDA012V1 12 Bit 1 GS/s DAC (GaAs),”
http://www.rsc.rockwell.com/highspeed/products_RDA012.html.
[36]
S.P. Reichhart, B. Youmans, and R. Dygert, R, “ The software radio development system,”
IEEE Personal Communications, Volume: 6 Issue: 4, Aug. 1999, Page(s): 20 – 24.
[37]
“Sandblaster DSP,” Sandbridge Technologies,
http://www.sandbridgetech.com/images/sandblaster_overview.pdf.
[38]
P.M. Shankar, and B.A. Eisenstein, “ Project-based instruction in wireless communications at
the junior level,” IEEE Transactions on Education, Volume: 43 Issue: 3, August 2000, Page(s):
245 –249.
[39]
K.S. Shanmugan, “Estimating the power spectral density of ultra wideband signals,” In
Proceedings Of the 2002 IEEE Conference on Personal Wireless Communications, 15-17
December 2002, Page(s): 124 –128.
[40]
T. Shono, H. Shiba, Y. Shirato, K. Uehara, K. Araki , and M. Umehira, “ Performance of IEEE
802.11 wireless LAN implemented on software defined radio with hybrid programmable
architecture, Communications,” In Proceedings of the 2003 IEEE International Conference on
Communications, Volume: 3, 11-15 May 2003, Page(s): 2035 – 2040.
[41]
“SPEAKeasy Radio Communications,”
http://www.rl.af.mil/div/IFB/techtrans/datasheets/SPEAK-PIX.html.
[42]
Warren L. Stutzman, Gary A. Thiele, Antenna Theory and Design, 2nd edition, John Wily and
Sons Inc., 1998.
[43]
“TMS320C6000 Paripherals Reference Guide,” Texas Instruments technical document
SPRU190D, February 2001.
[44]
“TMS320C6416 Fixed-Point Digital Signal Processor,”
http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=TMS320C6416.
[45]
“Using the TMS320C6000 McBSP as a High Speed Communication Port,”
http://focus.ti.com/lit/an/spra455a/spra455a.pdf.
[46]
TS83102G0 ADC 10-bit 2-Gsps Converter, Atmel,
http://www.atmel.ru/Atmel/acrobat/ts83102g0fs.pdf.
120
[47]
T.M. Weller, P.G. Flikkema, L.P. Dunleavy, H.C. Gordon, and R.E. Henning, “ Educating
tomorrow's RF/microwave engineer: a new undergraduate laboratory uniting circuit and system
concepts,” 1998 IEEE International Microwave Symposium Digest, Volume: 2, 7-12 June 1998,
Page(s): 563 –566.
[48]
“World's Fastest CMOS DAC for 3G,” http://www.3g.co.uk/PR/Feb2003/4825.htm.
[49]
H. Yoshida, H. Tsurumi, and Y. Suzuki, “ Broadband RF front-end and software execution
procedure in software-defined radio,” In Proceedings of the 50th IEEE Vehicular Technology
Conference, Volume: 4, 19-22 September 1999, Page(s): 2133 – 2137.
[50]
Rodger E. Zeiemer, Roger L. Peterson, Digital Communications and Spread Spectrum Systems,
Macmillan Publishing Company, New York, 1985.