ECE 546 - VLSI Systems Design
Lecture 3: Energy, Power,
and Quality Metrics
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikolić
© W. Rhett Davis
NC State University
Slide 1
ECE 546
Fall 2012
Announcements

HW#1 Due Tuesday

Office Hours
» Jay Narasihman (starting today)
– Thursday 10-11am
– Friday 4-5pm
» Zhao Wang (starting Sep. 7)
– Friday 2-3pm
© W. Rhett Davis
NC State University
Slide 2
ECE 546
Fall 2012
Summary of Last Lecture

How do we define VOL,VOH,VM, VIL,
and VIH?

What effect does transistor width have
on VM?

Explain in simple terms how to calculate
Req and propagation delay (tp)
© W. Rhett Davis
NC State University
Slide 3
ECE 546
Fall 2012
Today’s Lecture

Propagation Delay, Rise & Fall Times (5.4.2)

Dynamic Power (5.5.1)

Quality Measures (PDP & EDP) (5.5.3)

Short-Circuit Power (5.5.1)

Static Power (5.5.2)
© W. Rhett Davis
NC State University
Slide 4
ECE 546
Fall 2012
Inverter Transient Response
3
2.5
2
V
out
(V)
1.5
tpLH
tpHL
1
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
© W. Rhett Davis
NC State University
2
2.5
x 10
Slide 5
-10
ECE 546
Fall 2012
The Transistor as a Switch
VGS  VT
Ron
ID
S
V GS = VD D
D
Rmid
R0
V DS
VDD/2
VDD

1
VDD
VDD / 2


RON  Req  
2  I D VDS  VDD , VGS  VDD  I D VDS  VDD / 2, VGS  VDD  
© W. Rhett Davis
NC State University
Slide 6
ECE 546
Fall 2012
Propagation Delay
Vout
Reqn
CL
Vout (t )  VDD e
t
Reqn C L
 VDD / 2
1
2
 ln(2) Reqn C L  0.69 Reqn C L
e
t pHL
t
Reqn C L

t pLH 

1
t p  t pHL  t pLH
2
© W. Rhett Davis
NC State University
Slide 7

ECE 546
Fall 2012
Rise and Fall Times

Usually measured as
the 10%-90% times
» Why?
» Why do we not
recalculate Req?
t 2
VDD e
 t1
VDD e
Reqn C L
 0.1VDD
Reqn C L
 0.9VDD
t f  t 2  t1 
tr 
© W. Rhett Davis
NC State University
Slide 8
ECE 546
Fall 2012
How to Make A Gate Faster?

1
VDD
VDD / 2


RON  Req  
2  I D VDS  VDD , VGS  VDD  I D VDS  VDD / 2, VGS  VDD  
W
ID  k
L
2

Vmin 
VGS  VT Vmin 
 1   VDS 
2 

Vmin  min VGS  VT ,VDS ,VDSAT 
t pHL  0.69 Reqn C L
© W. Rhett Davis
NC State University
Slide 9
ECE 546
Fall 2012
Today’s Lecture

Propagation Delay, Rise & Fall Times (5.4.2)

Dynamic Power (5.5.1)

Quality Measures (PDP & EDP) (5.5.3)

Short-Circuit Power (5.5.1)

Static Power (5.5.2)
© W. Rhett Davis
NC State University
Slide 10
ECE 546
Fall 2012
Energy and Power

How to find the Energy dissipated in an
inverter?
All Power comes from the supply voltage
How much energy comes from supply?
E
P  VI 
T
E   VIdt
(EQ 5.40)
© W. Rhett Davis
NC State University
Slide 11
ECE 546
Fall 2012
Energy & Power
How much energy is stored on capacitor?
VDD
iVDD(t)
Vout
CL
(EQ 5.41)

Half of energy delivered is stored on capacitor
» Where did the rest go?
» What happens on
HL transition?
» What is the energy per switching event? E =
SW
© W. Rhett Davis
NC State University
Slide 12
ECE 546
Fall 2012
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes
 How to reduce power of a gate?

© W. Rhett Davis
NC State University
Slide 13
ECE 546
Fall 2012
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
= C  V 2  n N 
N
L
dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN
2
n N 
=  lim -----------C V
= lim --------  f
P

 f clk
dd
clk
avg N


N
N
N
L

0
P
© W. Rhett Davis
avg
1
=
n N 
lim -----------N N
= 
C
V 2 f
0  1  L  dd  clk
NC State University
Slide 14
ECE 546
Fall 2012
Today’s Lecture

Propagation Delay, Rise & Fall Times (5.4.2)

Dynamic Power (5.5.1)

Quality Measures (PDP & EDP) (5.5.3)

Short-Circuit Power (5.5.1)

Static Power (5.5.2)
© W. Rhett Davis
NC State University
Slide 15
ECE 546
Fall 2012
Quality Measures

Power Delay Product
» PDP = Pavgtp
» in general, assume 0-1=0.5 and fclk=1/tp
– PDP = CLVDD2/2 = ESW/2
– Lower PDP means lower-power technology
» How to lower PDP?
» What happens to delay as PDP is lowered?
© W. Rhett Davis
NC State University
Slide 16
ECE 546
Fall 2012
Quality Measures

Energy Delay Product
» EDP = PDP*tp
» A measure that shows
when supply scaling
no longer pays off
EDP
tp
PDP
~ 1.1 V
in 0.25 m
VDD (V)
» Best to think of EDP
as the optimum point
on a set of energydelay indifference
curves
© W. Rhett Davis
NC State University
Slide 17
ECE 546
Fall 2012
Today’s Lecture

Propagation Delay, Rise & Fall Times (5.4.2)

Dynamic Power (5.5.1)

Quality Measures (PDP & EDP) (5.5.3)

Short-Circuit Power (5.5.1)

Static Power (5.5.2)
© W. Rhett Davis
NC State University
Slide 18
ECE 546
Fall 2012
Power: The Whole Story

Dynamic Power Consumption
» Charging and Discharging Capacitors

Short Circuit (Direct Path) Currents
» Short Circuit Path between Supply Rails
during Switching

Leakage
» Leaking diodes and transistors
© W. Rhett Davis
NC State University
Slide 19
ECE 546
Fall 2012
Short Circuit (Direct Path) Current
•Vdd
•Vin
•Vout

•C•L

•0.15
Ipeak
•0.10
IVDD(mA)

•0.05
•0.0
•1.0
•2.0
•3.0
•4.0
•5.0
Caused by nonzero rise/fall time
of input
Power goes
directly from
supply to ground,
getting wasted
Does Ipeak depend
on the transition
time?
Vin(V)
© W. Rhett Davis
NC State University
Slide 20
ECE 546
Fall 2012
Predicting ESC from tr & tf

If you know Ipeak, you can predict ESC for any
transition time
ESC  VDD
I peak t SC
2
for either HL or
LH transition
where t SC 
VDD  2VT t r / f

0 .8
VDD
For a larger transition time, is ESC larger or smaller?
© W. Rhett Davis
NC State University
Slide 21
ECE 546
Fall 2012
What affects Ipeak?
W/L ratios of transistors
 Load Capacitance / Output rise/fall time

(Fig. 5-31)
» why?
© W. Rhett Davis
NC State University
Slide 22
ECE 546
Fall 2012
How to keep direct-path current low?



Short circuit current
goes to zero if tf >> tr
Plot shows how total
power dissipation
asymptotically
approaches dynamic
power as CL increases
Can’t do this for
cascade logic
© W. Rhett Davis
NC State University
Slide 23
ECE 546
Fall 2012
Minimizing Short Circuit Current
8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
Vdd =1.5
0
0
1
2
3
4
5
tsin/tsout
© W. Rhett Davis
NC State University
Slide 24
ECE 546
Fall 2012
Today’s Lecture

Propagation Delay, Rise & Fall Times (5.4.2)

Dynamic Power (5.5.1)

Quality Measures (PDP & EDP) (5.5.3)

Short-Circuit Power (5.5.1)

Static Power (5.5.2)
© W. Rhett Davis
NC State University
Slide 25
ECE 546
Fall 2012
Leakage
Vdd
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
in low-energy circuit design!
© W. Rhett Davis
NC State University
Slide 26
ECE 546
Fall 2012
Reverse-Bias Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
JS = 10-100 pA/m2 at 25 deg C
for 0.25 m CMOS
 JS doubles for every 9 deg C!

© W. Rhett Davis
NC State University
Slide 27
ECE 546
Fall 2012
Subthreshold Leakage

Most technology
vendors offer two
or more
thresholds
» high-speed (HS)
» low-power (LP)
S


Which is which
on plot?
S=Subthreshold
Slope – similar
for all devices on
the same chip
» ~100 mV/decade
in our technology
© W. Rhett Davis
NC State University
Slide 28
ECE 546
Fall 2012
Subthreshold Example (5-14)

Given a device with a certain leakage:
» VT = 0.5 V
» Ioff = 10-11 A
» S = 100 mV/decade

Find Ioff for VT = 0.3 V

What can you do to reduce leakage
power?
© W. Rhett Davis
NC State University
Slide 29
ECE 546
Fall 2012
Controling Threshold Voltage
VT  VT 0  
SB



 2 F  VSB   2 F
T

T0
Body-Effect
Altering VSB can be used to
» reduce leakage (negative) “Back-Body Bias” or
“Reverse Body Bias”
» increase speed (positive) “Forward-Body Bias”
© W. Rhett Davis
NC State University
Slide 30
ECE 546
Fall 2012
Static Power Consumption
•Vdd
•I•stat
•V•out
•V•in•=5V




© W. Rhett Davis
•C•L
Pstat(in=1) = VDD Istat(in=1)
Pstat(in=0) = VDD Istat(in=0)
Pstat = ½[Pstat(in=1)+ Pstat(in=0)]
Wasted Energy (should be avoided)
NC State University
Slide 31
ECE 546
Fall 2012
Summary

Putting it all together
» Ptot = Pdyn + Psc + Pstat
» Ptot = (CLVDD2 + VDDIpeaktSC)f0-1+VDDIleak

PDP = Ptottp
» for HW1 ignore Psc and Pstat

EDP = Ptottp2
© W. Rhett Davis
NC State University
Slide 32
ECE 546
Fall 2012