Datasheet
Synopsys PrimeTime SI
®
The Signal Integrity Sign-off Solution
Overview
With the advent of shrinking process geometries and rising clock frequencies for nanometer
designs, signal integrity (SI) effects such as crosstalk delay and noise (or glitch) propagation
can cause functional failures or failed timing. It is essential for designers to address these SI
problems to ensure that their designs are delivered to market correctly in the shortest amount
of time. Time-to-market pressure, chip complexity, and control of SI effects are all factors requiring
an accurate, fast, and trusted analysis and sign-off solution. The Synopsys PrimeTime SI solution
builds upon the trusted PrimeTime solution to accurately and quickly analyze signal integrity effects.
The Challenge
At 130-nanometers (nm) and below signal integrity effects, such
NEW
PrimeTime
STA and Delay Calculation
as crosstalk between signals caused by capacitive coupling,
have become mainstream design challenges. Without adequate
attention, these effects can result in performance degradation,
functional failure, or reliability problems. Signal integrity effects
are interdependent with timing and need to be analyzed in the
context of timing. This tight loop and interdependency requires
an integrated approach for signal integrity and timing analysis.
The PrimeTime SI solution delivers an efficient, accurate and
unified environment to analyze signal integrity effects.
Binary SPEF
Star-RCXT
Variation-aware
Variation-aware (VX)
Parasitic
Extraction
PrimeTime SI
Integrated Xtalk delay and noise analysis
PrimeTime PX
NEW
Peak Power
Integrated gate-level power analysis
IR Drop
PrimeTime VX
PrimeRail
Rail Analysis
NEW
NEW
Integrated variation-aware STA
Model Generation
NanoTime
SDC
Transistor-level
STA and SI
Liberty CCS
Unified timing, SI, power
and variation models
Figure 1: Galaxy Sign-off Solutions
PrimeTime SI
Aggressor
Start
Cs
Cw
Read and Setup Design
Victim
STA
+
Crosstalk Delay Analysis
+
Noise Analysis
Timing Impact
Slow-down
Effect
Timing and
Noise Report Generation
Speed-up
Effect
End
Figure 2: PrimeTime SI Flow—Easy to Use and Adopt
Time
Figure 3: Crosstalk Delay Analysis Pinpoints Crosstalk Timing Failures
The Solution
Accurate crosstalk delay, noise (glitch) and IR drop analysis
The Synopsys PrimeTime SI solution is a full-chip, gate-
Signal integrity effects are interdependent and need to be
level signal integrity analysis and sign-off tool integrated
analyzed in the context of timing. PrimeTime SI uses an
within the Synopsys Galaxy™ Design Platform. It accurately
integrated golden delay calculation engine with the proven and
analyzes crosstalk delay, noise (glitch) and IR drop within the
trusted PrimeTime static timing analysis engine to accurately
tape-out proven PrimeTime static timing analysis and sign-
model and compute timing deviations due to crosstalk and IR
off environment. Combined with industry-leading runtime
drop. PrimeTime SI also performs accurate noise calculation,
performance and capacity, the PrimeTime SI solution enables
detection, and propagation on large designs.
designers to achieve first-pass silicon success and fast time-tomarket on their multimillion-gate designs.
Ease of adoption and use
Key Features and Benefits
(STA), is easy to use and adopt. It utilizes the familiar PrimeTime
Comprehensive and efficient SI analysis built-into
flow and environment, with the same commands, user interface,
the PrimeTime environment
reports, and attributes.
PrimeTime SI, an extension of PrimeTime Static Timing Analysis
The unified approach of signal integrity and timing analysis
delivers a comprehensive and time-efficient method to concurrently analyze noise and crosstalk delay effects on timing.
Additionally, the concurrent analysis in a single tool enables
faster results while improving designer productivity.
Industry-leading performance and capacity
PrimeTime SI is based on the proven Synopsys static timing
analysis technology. It provides the capacity required to analyze
multimillion gate designs and the performance needed to
minimize run times at the full-chip level.
PrimeTime SI
Aggressor
Functional
Failure?
0
Victim
Generated
Glitch
Propagated
Glitch
Figure 4: Crosstalk Noise Analysis Pinpoints Functional Crosstalk Failures
Additional Features
About Galaxy Design Platform
• Reduces false violations by considering slew propagation,
The Galaxy Design Platform is an open, integrated design
timing windows, and logical correlation of signals
implementation platform with best-in class tools and IP,
• Hierarchical SI analysis capabilities using ILMs with crosstalk
enabling advanced semiconductor design. Anchored by
• What-if analysis
Synopsys’ industry-leading semiconductor design tools and
• Distributed multi-scenario analysis
the open Milkyway™ database, the Galaxy Design Platform
• Path-specific analysis
incorporates consistent timing, SI analysis, common libraries,
• Save and restore
delay calculation, constraints, testability, and physical verifi-
• Supports industry-standard Non-Linear Delay Model (NLDM)
cation to provide a convergent flow from RTL all the way to
and Composite Current source (CCS) noise libraries
• Integrated within the Synopsys Galaxy Design Platform,
enabling rapid SI closure
silicon. The Galaxy Design Platform helps reduce design time,
decrease integration costs and minimize the risks inherent in
advanced, complex semiconductor design.
Synopsys, Inc.
700 East Middlefield Road
Mountain View, CA 94043
www.synopsys.com
©2007 Synopsys, Inc. Synopsys, the Synopsys logo, and PrimeTime are registered trademarks and Galaxy is a trademark of Synopsys. All other products or service names mentioned herein are
trademarks of their respective holders and should be treated as such. Printed in the U.S.A. 01/07.KF.WO.07-15192