AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
REVISION HISTORY
Revision
Rev. 1.0
Description
Initial Issued
Issue Date
Oct. 26. 2012
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
0
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
FEATURES
GENERAL DESCRIPTION
 Fast access time : 10ns
 low power consumption:
Operating current:
90mA (Icc1 typical)
Standby current:
4mA(Typical)
 Single 3.3V power supply
 All inputs and outputs TTL compatible
 Fully static operation
 Tri-state output
 Data retention voltage : 1.5V (MIN.)
 Green package available
 Package : 48-pin 12mm x 20mm TSOP-I
The AS7C316096A is a 16M-bit high speed CMOS
static random access memory organized as 2048K
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS7C316096A operates from a single power
supply of 3.3V and all inputs and outputs are fully
TTL compatible
PRODUCT FAMILY
Product
Operating
Family
Temperature
AS7C316096A(I) -40 ~ 85℃
Vcc Range
Speed
2.7 ~ 3.6V
10
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A20
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc1,TYP.)
4mA
90mA
2048Kx8
MEMORY ARRAY
COLUMN I/O
SYMBOL
DESCRIPTION
A0 - A20
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
1
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
PIN CONFIGURATION
NC
NC
NC
A4
A3
A2
A1
A0
CE#
DQ0
DQ1
Vcc
Vss
DQ2
DQ3
WE#
A20
A19
A18
A17
A16
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AS7C316096A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
A5
A6
A7
A8
A9
OE#
DQ7
DQ6
Vss
Vcc
DQ5
DQ4
A10
A11
A12
A13
A14
A15
NC
NC
NC
TSOP-I
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on Vcc relative to VSS
Voltage on any other pin relative to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
SYMBOL
VT1
VT2
TA
TSTG
PD
IOUT
RATING
-0.5 to 4.6
-0.5 to Vcc+0.5
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
2
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
SUPPLY CURRENT
ISB, ISB1
ICC, ICC1
ICC, ICC1
ICC, ICC1
I/O OPERATION
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
SYMBOL
TEST CONDITION
VCC
*1
VIH
*2
VIL
ILI
VCC ≧ VIN ≧ VSS
VCC ≧ VOUT ≧ VSS,
ILO
Output Disabled
MIN.
2.7
2.2
- 0.3
-1
TYP.
3.3
-
*4
MAX.
3.6
VCC+0.3
0.8
1
UNIT
V
V
V
µA
-1
-
1
µA
Output High Voltage
VOH
IOH = -8mA
2.4
-
-
V
Output Low Voltage
VOL
IOL =4mA
-
-
0.4
V
-
110
160
mA
90
120
mA
-
-
80
mA
-
4
40
mA
AverageOperating
Power supply
Current
Standby Power
Supply Current
Standby Power
Supply Current
Icc
Icc1
Isb
ISB1
CE# = VIL , II/O = 0mA
-10
;f=max
CE# ≦0.2, Other
pin is at 0.2V or Vcc-0.2V -10
II/O = 0mA;f=max
CE# ≧Vih
Other pin is at Vil or Vih
CE# ≧VCC - 0.2V;
Other pin is at 0.2V or Vcc-0.2V
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
3
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
MAX
8
10
-
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
speed
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
10ns
0.2V to Vcc-0.2V
3ns
Vcc/2
CL = 30pF + 1TTL,
IOH/IOL = -8mA/4mA
Output Load
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
AS7C316096A -10
SYM.
MIN.
10
2
0
2
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
MAX.
10
10
4.5
4
4
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
SYM.
AS7C316096A -10
MIN.
10
2
0
2
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
MAX.
10
10
4.5
4
4
-
*These parameters are guaranteed by device characterization, but not production tested.
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
5
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
6
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR
CE# ≧ VCC - 0.2V
VCC = 1.5V
CE# ≧VCC - 0.2V;
IDR
Other pin is at 0.2V or
Vcc-0.2V
See Data Retention
tCDR
Waveforms (below)
tR
MIN.
1.5
TYP.
-
MAX.
3.6
UNIT
V
-
4
40
mA
0
-
-
ns
tRC*
-
-
ns
DATA RETENTION WAVEFORM
VDR ¡Ù 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ¡Ù Vcc-0.2V
VIH
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
7
AS7C316096A
Rev. 1.0
2048K X 8 BIT HIGH SPEED CMOS SRAM
PACKAGE OUTLINE DIMENSION
48-pin 12mm x 20mm TSOP-I Package Outline Dimension
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
8
AS7C316096A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
ORDERING INFORMATION
Package Type
48-pin(12mmx20mm)
TSOP-I
Access Time
(Speed)(ns)
10
Temperature
Range(℃)
-40℃~85℃
Packing
Type
Tray
Tape Reel
Alliance Memory Item No.
AS7C316096A -10TIN
AS7C316096A -10TINTR
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
9
AS7C316096A
Rev. 1.0
2048K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
551 Taylor Way, San Carlos, CA 94070
TEL: 650-610-6800
FAX: 650-620-9211
10