Virtex-II Pro™ FF1152 Development Board
User’s Guide
Version 1.3
October 2004
PN# DS-MANUAL-2VPx-FF1152
Table of Contents
1
OVERVIEW............................................................................................................................... 1
2
THE VIRTEX-II PRO FF1152 SYSTEM BOARD ..................................................................... 2
3
FUNCTIONAL DESCRIPTION................................................................................................. 2
3.1
3.2
XILINX VIRTEX-II PRO FPGA (XC2VP20/P30/P40/P50-FF1152) ........................................ 5
MGT INTERFACE ................................................................................................................. 5
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
LVDS INTERFACE .............................................................................................................. 14
3.3.1
3.3.2
3.3.3
3.4
4
10/100 Ethernet..................................................................................................................... 34
IDE/General-Purpose 40-Pin Header .................................................................................... 35
LCD Panel............................................................................................................................. 37
RS232 ................................................................................................................................... 37
User DIP and PB Switches.................................................................................................... 38
User LEDs............................................................................................................................. 38
CONFIGURATION AND DEBUG PORTS .................................................................................. 39
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.8
3.9
3.10
FPGA_GCLK0 Clock Source ................................................................................................ 25
Programmable LVDS Clock Sources .................................................................................... 26
ICS8442 Programmable LVDS Clock Synthesizer ................................................................ 26
ICS8442 Clock Generation.................................................................................................... 28
ICS8442 Programming Modes .............................................................................................. 28
ICS8442 M and N Settings.................................................................................................... 28
MISCELLANEOUS I/O INTERFACE ........................................................................................ 34
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7
Two Blocks of x32 Memory Configuration ............................................................................. 18
Single Block of x64 Memory Configuration............................................................................ 19
SDRAM Interfaces................................................................................................................. 19
CLOCK SOURCES ............................................................................................................... 22
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6
SPI-4.2 Interface ................................................................................................................... 14
SPI-4.2 Pin Assignments....................................................................................................... 15
LVDS Connector ................................................................................................................... 17
MEMORY ........................................................................................................................... 18
3.4.1
3.4.2
3.4.3
3.5
MGT Reference Clock Inputs ................................................................................................ 10
MGT SMA Connectors .......................................................................................................... 10
GbE Interface ........................................................................................................................ 11
Infineon iSFP Gb Module ...................................................................................................... 11
Host Board Connector........................................................................................................... 12
JTAG Chain........................................................................................................................... 39
System ACE Module Connector............................................................................................ 40
Serial Flash ........................................................................................................................... 42
JTAG Port (PC4) ................................................................................................................... 46
CPU JTAG Port ..................................................................................................................... 46
CPU Debug Port.................................................................................................................... 47
CPU Trace Port ..................................................................................................................... 48
Configuration Modes ............................................................................................................. 49
SUPPLY VOLTAGES ............................................................................................................ 49
BANK I/O VOLTAGE ............................................................................................................ 50
P160 EXPANSION MODULE SIGNAL ASSIGNMENTS .......................................................... 51
REVISIONS ............................................................................................................................ 53
October 27, 2004
i
Figures
FIGURE 1 - VIRTEX-II PRO FF1152 DEVELOPMENT PLATFORM BLOCK DIAGRAM .................................. 4
FIGURE 2 - MGT PORTS ON THE FF1152 SYSTEM BOARD .................................................................. 6
FIGURE 3 - GBE INTERFACE USING ISFP MODULES .......................................................................... 11
FIGURE 4 - ISFP MODULE (PHOTO TAKEN FROM INFINEON W EB PAGE)............................................... 11
FIGURE 5 - HOST BOARD CONNECTOR AMP 1367073-1 (PHOTO TAKEN FROM AMP W EB PAGE) ....... 12
FIGURE 6 – ISFP MODULE INTERFACE TO THE VIRTEX-II PRO FPGA ................................................. 13
FIGURE 7 - SPI-4.2 INTERFACE ........................................................................................................ 15
FIGURE 8 – SAMTEC QSE TYPE CONNECTOR FOR THE SPI-4.2 INTERFACE .................................... 17
FIGURE 9 – 32-BIT SDRAM INTERFACE ............................................................................................ 18
FIGURE 10 - 64-BIT SDRAM INTERFACE ........................................................................................... 19
FIGURE 11 - SDRAM INTERFACE ..................................................................................................... 19
FIGURE 12 - CLOCK SOURCES ON THE FF1152 BOARD ..................................................................... 23
FIGURE 13 – FPGA_GCLK0 CLOCK SOURCE JUMPER SETTINGS ..................................................... 25
FIGURE 14 – ICS8442 CLOCK SYNTHESIZER .................................................................................... 26
FIGURE 15 – ICS8442 CLOCK SYNTHESIZER INTERFACE TO THE FPGA ............................................ 29
FIGURE 16 – ICS8442 CLOCK SYNTHESIZER M AND N DIP SWITCHES .............................................. 30
FIGURE 17 – M AND N DIP SWITCHES FOR THE SYNTHESIZERS ......................................................... 31
FIGURE 18 – 10/100 ETHERNET INTERFACE...................................................................................... 34
FIGURE 19 - 40-PIN USER HEADER W ITH IDE PINOUT ...................................................................... 35
FIGURE 20 – IDE INTERFACE............................................................................................................ 36
FIGURE 21 – RS232 INTERFACE ...................................................................................................... 37
FIGURE 22 – JTAG CHAIN ............................................................................................................... 39
FIGURE 23 – FF1152 DEVELOPMENT BOARD CONFIGURATION INTERFACE......................................... 42
FIGURE 24 – FF1152 DEVELOPMENT BOARD JTAG CHAIN ............................................................... 43
FIGURE 25 – SERIAL FLASH CONFIGURATION INTERFACE ................................................................... 44
FIGURE 26 – PC4 JTAG PORT CONNECTOR .................................................................................... 46
FIGURE 27 - CPU JTAG PORT CONNECTOR..................................................................................... 47
FIGURE 28 - CPU DEBUG PORT CONNECTOR ................................................................................... 47
FIGURE 29 – CPU TRACE PORT CONNECTOR ................................................................................... 48
FIGURE 30 - VOLTAGE REGULATORS ................................................................................................ 50
October 27, 2004
ii
Tables
TABLE 1 - DIFFERENCES BETWEEN 2VP20 AND 2VP30 DEVICES ......................................................... 5
TABLE 2 - COMMUNICATIONS STANDARDS SUPPORTED BY ROCKETIO TRANSCEIVER ............................ 5
TABLE 3 – VIRTEX-II PRO BOARD TOP MGT4 AND 6 ........................................................................... 7
TABLE 4 – VIRTEX-II PRO BOARD TOP MGT7 AND 9 ........................................................................... 7
TABLE 5 – VIRTEX-II PRO BOARD BOTTOM MGT16 AND 18 ................................................................. 8
TABLE 6 – VIRTEX-II PRO BOARD BOTTOM MGT19 AND 21 .................................................................. 9
TABLE 7 – ISFP HOST CONNECTOR PIN DESCRIPTION ...................................................................... 12
TABLE 8 – ISFP PIN ASSIGNMENTS .................................................................................................. 14
TABLE 9 – SPI-4.2 TRANSMIT PIN ASSIGNMENTS .............................................................................. 15
TABLE 10 – SPI-4.2 RECEIVE PIN ASSIGNMENTS .............................................................................. 16
TABLE 11 – SDRAM1 INTERFACE PIN ASSIGNMENTS ........................................................................ 19
TABLE 12 – SDRAM2 INTERFACE PIN ASSIGNMENTS ........................................................................ 21
TABLE 13 - CLOCK SOURCES............................................................................................................ 24
TABLE 14 – JP25 JUMPER SETTINGS................................................................................................ 25
TABLE 15 – JUMPER SETTINGS FOR ROUTING THE P160 CLOCK TO FPGA I/O PIN ............................ 25
TABLE 16 – ICS8442 CLOCK SYNTHESIZER PIN DESCRIPTION........................................................... 27
TABLE 17 – INPUT CLOCK SELECT SIGNAL DESCRIPTION ................................................................... 27
TABLE 18 – ICS8442 N SETTINGS ................................................................................................... 28
TABLE 19 – EXAMPLES OF THE ICS8442 M AND N SETTINGS ............................................................ 28
TABLE 20 – DIP SWITCH SETTING FOR M[8:0] .................................................................................. 31
TABLE 21 – DIP SWITCH SETTING FOR N[1:0]................................................................................... 31
TABLE 22 – SYNTHESIZER CLOCK OUTPUTS FOR M AND N VALUES ................................................... 32
TABLE 23 – FPGA PIN ASSIGNMENTS FOR THE SYNTHESIZER INTERFACE .......................................... 33
TABLE 24 – ETHERNET PIN ASSIGNMENTS ........................................................................................ 34
TABLE 25 – IDE CONNECTOR PIN ASSIGNMENTS .............................................................................. 36
TABLE 26 – LCD INTERFACE SIGNALS .............................................................................................. 37
TABLE 27 – RS232 SIGNALS ............................................................................................................ 38
TABLE 28 – PUSH SWITCH PIN ASSIGNMENTS ................................................................................... 38
TABLE 29 – DIP SWITCH PIN ASSIGNMENTS ..................................................................................... 38
TABLE 30 – LED PIN ASSIGNMENTS ................................................................................................. 39
TABLE 31 – SYSTEM ACE CLOCK SOURCE ....................................................................................... 41
TABLE 32 - SAM INTERFACE SIGNALS .............................................................................................. 41
TABLE 33 – JTAG CHAIN JUMPER SETTINGS .................................................................................... 43
TABLE 34 – FILES IN THE FLASH_UTILITIES FOLDER .......................................................................... 45
TABLE 35 – PLATFORM FLASH SELECTION ....................................................................................... 45
TABLE 36 – CPU DEBUG INTERFACE SIGNALS .................................................................................. 48
TABLE 37 – TRACE PORT PIN ASSIGNMENTS ..................................................................................... 49
TABLE 38 - FPGA CONFIGURATION MODE JUMPER SETTINGS ........................................................... 49
TABLE 39 – CURRENT PROVIDED FOR EACH VOLTAGE SOURCE ON THE BOARD .................................. 50
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iii
TABLE 40 – I/O BANK VOLTAGES ...................................................................................................... 50
TABLE 41 – P160 CONNECTOR PIN ASSIGNMENTS ............................................................................ 51
TABLE 42 - P160 CONNECTOR PIN ASSIGNMENTS............................................................................. 52
October 27, 2004
iv
1
Overview
The Memec Design Virtex-II Pro™ FF1152 Development Kit provides a complete development
platform for designing and verifying applications based on the Xilinx Virtex-II Pro FPGA family.
This kit enables designers to implement embedded processor based applications with extreme
flexibility using IP cores and customized modules. The Virtex-II Pro FPGA with its integrated
PowerPC™ processor and powerful RocketIO™ Multi-Gigabit Transceivers (MGT) makes it
possible to develop highly flexible and high-speed serial transceiver applications.
The kit bundles the Xilinx Embedded Development Kit (EDK) with an advanced Virtex-II Pro
hardware platform, power supply, and reference designs. Xilinx ISE software and a JTAG cable
are also required and available as kit options. The EDK includes standard peripherals, GNUbased software tools, and system configuration tools. The GNU-based development tools are
composed of a C compiler, assembler, linker and debugger.
The Virtex-II Pro FF1152 system board utilizes the Xilinx XC2VP20-6FF1152C, XC2VP306FF1152C, XC2VP40-6FF1152C, or XC2VP50-6FF1152C FPGA. These FPGA devices contain
two PowerPC processors and eight/twelve/sixteen RocketIO transceivers supporting data transfer
rates of up to 3.125 Gbps/port (P40/P50 have eight/sixteen MGT ports). The Virtex-II Pro system
board is designed to provide eight RocketIO transceivers, hence, when the board is populated
with the XC2VP40 or XC2VP50 FPGA, four/eight out of the twelve/sixteen RocketIO transceivers
on the XC2VP40/P50 FPGA will not be available to the users.
The Virtex-II Pro FF1152 system board includes two memory blocks of 8Mx32 SDRAM memory
each, five clock sources, two RS-232 ports, high-speed 16-bit LVDS interface supporting SPI-4.2,
two iSFP GbE optical interfaces, 10/100 Ethernet PHY, IDE connector, and additional user
support circuitry to develop a complete system. The board also supports the Memec Design P160
expansion module standard, allowing application specific expansion modules to be easily added.
A System ACE™ interface on the Virtex-II Pro system board gives software designers the ability
to run real-time operating systems (RTOS) from removable CompactFlash cards.
The Virtex-II Pro FPGA family has the advanced features needed to fit demanding and highperformance applications. The Virtex-II Pro FF1152 Development Kit provides an excellent
platform to explore these features so that you can quickly and effectively meet your time-tomarket requirements.
The Virtex-II Pro FF1152 Development Kit includes the following:
-
Virtex-II Pro FF1152 development board with 2VP20, P30, P40, or P50 FPGA (Rev 1
Board)
70W switching power supply
RS-232 serial cable
Two coax loop back cables for MGT testing
Documentation CD
Optional items that support development efforts:
-
Xilinx Embedded Development Kit CDs (EDK)
Xilinx ISE software
JTAG cable
iSFP transceiver modules and fiber loop back cable
System ACE Module (included with P40 and P50 kits)
October 27, 2004
1
-
Additional coax loop back cables
Wind River visionPROBE-II and visionICE-II tools
Contact your local Memec distributor for assistance with any of these items.
2
The Virtex-II Pro FF1152 System Board
3
Functional Description
A high-level block diagram of the Virtex-II Pro FF1152 development platform is shown below
followed by a brief description of each sub-section. A list of features for this board is shown
below:
•
•
•
•
•
•
•
•
•
•
Xilinx XC2VP20/P30/P40/P50-FF1152C FPGA
Support for 10G Optical Module
High-speed LVDS Interface Supporting SPI-4.2
Six Rocket I/O™ Ports Supporting up to 3.125Gbits/port
Two Optical GbE Ports
Support for GbE Optical Module
Three Programmable LVDS Clock Sources (25 – 700MHz)
On-board LVTTL 100MHz Oscillators
On-board LVTTL Oscillator Socket (4/8-Pin Oscillators)
Two User LVDS Clock Inputs via Differential SMA Connectors
October 27, 2004
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three User LVDS Clock Outputs via Differential SMA Connectors
Two SDRAM Memory Blocks (32MB each, x32 memory configuration)
SDRAM Memory Blocks can be used as a single x64 Memory
P160 Connectors
10/100 PHY
A 40-Pin User Header to be used as General-Purpose I/O or IDE interface
LCD Panel
16/32Mb Atmel Data Flash for FPAG configuration
JTAG Programming/Configuration Port
CPU JTAG/Debug Ports
CPU TRACE Port
SystemACE™ Module Connector
Two RS232 Port
User LEDs
User DIP and Push-Button Switches
October 27, 2004
3
RocketIO SMA
Connectors
(6 MGT ports)
iSFP GbE Module
Connectors
(2 MGT ports)
80-Pin Connector
80-Pin Connector
MGT Interface
P160 Module
Configuration and Debug Ports
System ACE
Connector
LVDS Interface
LVDS
connectors
CPU
JTAG Port
Memory Interface
32MB
SDRAM (x32)
32MB
SDRAM (x32)
Virtex-II Pro
FPGA
XC2VP20/P30
(FF1152)
XC9536XV
Parallel Cable IV
JTAG Port
Atmel Flash
Parallel Cable IV
Flash Prog.
CPU
Debug Port
CPU
TRACE Port
Miscellaneous I/O
10/100
PHY
40-Pin Header
(IDE Pinout)
RS232 Ports
(2)
Clock Sources
Programmable
LVDS Clock Source
(3)
SMA Clock Outputs
(3 clock sources)
LCD Panel
LVTTL Clock
@100MHz
User Switches
LVTTL OSC Socket
(4/8-Pin)
User LEDs
SMA Clock Inputs
(2 clock sources)
Voltage Regulators
2.5V
Regulator
1.5V
Regulator
2.5V RocketIO
Supply
Regulated Voltages
3.3V, 5.0V, +12, -12,
and -5.0V
Figure 1 - Virtex-II Pro FF1152 Development Platform Block Diagram
October 27, 2004
4
3.1
Xilinx Virtex-II Pro FPGA (XC2VP20/P30/P40/P50-FF1152)
The P20/P30/P40/P50 Virtex-II Pro FPGA devices have two PowerPC processors and 8 DCMs.
The following table shows the differences among these devices in the FF1152-pin package.
Table 1 - Differences between 2VP20 and 2VP30 devices
Device
XC2VP20
XC2VP30
XC2VP40
XC2VP50
Number of
Slices
9,280
13,696
19,392
23,616
BlockRAM
(Kb)
1,584
2,448
3.456
4,176
Available
User I/O
564
644
804
852
Multipliers
88
136
192
232
RocketIO
Transceivers
8
8
12
16
Configuration
PROM
2 x XCF04S
3 x XCF04S
2 x XCF08
3 x XCF08
In order to have a common PCB design for the P20/P30/P40/P50 devices, the board will be
designed to utilize the user I/O pins that are common among these devices. Hence, the maximum
available user I/O pins on the P20/P30/P40/P50 development board will be 564.
3.2
MGT Interface
The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Up to 16 transceiver
modules are available on a single Virtex-II Pro FPGA, depending on the part being used. The
transceiver module is designed to operate at any serial bit rate in the range of 500 Mb/s to 3.125
Gb/s per channel, including the specific bit rates used by the communications standards listed in
the following table. The serial bit rate need not be configured in the transceiver, as the received
data, the applied reference clock, and the SERDES_10B attribute imply the operating frequency
of the transceiver.
Table 2 - Communications Standards Supported by RocketIO Transceiver
Mode
Channels (# of
I/O Bit Rate (Gb/s)
Internal Clock Rate
transceivers)
(REFCLK Mhz)
Fibre Channel
1
1.06
53
2.12
106
Gbit Ethernet
1
1.25
62.5
XAUI (10-Gbit Ethernet)
4
3.125
62.5
Infiniband
1, 4, 12
2.5
62.5
Aurora (Xilinx protocol)
1, 2, 4
0.840 – 3.125
62.5
Custom Mode
1, 2, 4, 8, …
up to 3.125
62.5
The following figure shows the four RocketIO transceiver ports used on the Virtex-II Pro
development board. These transceivers are physically located at the top and the lower side of the
Virtex-II Pro FPGA. The Virtex-II Pro development board is designed to provide programmable
reference clock inputs to the top and bottom RocketIO transceivers (refer to the Clock Sources
section for more information on the MGT reference clock inputs).
October 27, 2004
5
RocketIO
Port0
RocketIO
Port1
RocketIO
Port2
RXN
RXP
TXN
SMA
Connectors
TXP
RXN
RXP
TXN
SMA
Connectors
TXP
RXN
RXP
TXN
SMA
Connectors
TXP
RXN
RXP
TXN
TXP
SMA
Connectors
RocketIO
Port3
Programmable
LVDS Clock
Source
Virtex-II Pro
XC2VP20/P30-FF1152
RocketIO
Ref Clock (Bot)
SMA Connectors
Programmable
LVDS Clock
Source
RocketIO
Ref Clock (Top)
Top MGTs
Bottom MGTs
iSFP GbE
Module
Connector
iSFP GbE
Module
Connector
SMA
Connectors
TXP
TXN
RXP
RXN
RocketIO
Port4
TXP
TXN
RXP
RXN
RocketIO
Port5
RXN
RXP
TXN
TXP
RocketIO
Port6
RXN
RXP
TXN
TXP
RocketIO
Port7
SMA
Connectors
Figure 2 - MGT Ports on the FF1152 System Board
October 27, 2004
6
Table 3 – Virtex-II Pro Board Top MGT4 and 6
RocketIO
Port #
Signal Name
AVCCAUXRX4
Virtex-II Pro
Pin #
B26
VTRXPAD4
B27
RXNPAD4
A26
RXPPAD4
A27
GNDA4
C27
TXNPAD4
A29
TXPPAD4
A28
AVCCAUXTX4
B28
VTTXPAD4
B29
AVCCAUXRX6
B18
VTRXPAD6
B19
RXNPAD6
A18
RXPPAD6
A19
GNDA6
C20
TXNPAD6
A21
TXPPAD6
A20
AVCCAUXTX6
B20
VTTXPAD6
B21
0
1
Description
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
Negative differential transmit port of the multi
gigabit transceiver.
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
Negative differential transmit port of the multi
gigabit transceiver.
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Table 4 – Virtex-II Pro Board Top MGT7 and 9
RocketIO
Port #
2
October 27, 2004
Signal Name
AVCCAUXRX7
Virtex-II Pro
Pin #
B14
VTRXPAD7
B15
RXNPAD7
A14
RXPPAD7
A15
GNDA7
C15
TXNPAD7
A17
Description
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
Negative differential transmit port of the multi
gigabit transceiver.
7
3
TXPPAD7
A16
AVCCAUXTX7
B16
VTTXPAD7
B17
AVCCAUXRX9
B6
VTRXPAD9
B7
RXNPAD9
A6
RXPPAD9
A7
GNDA9
C8
TXNPAD9
A9
TXPPAD9
A8
AVCCAUXTX9
B8
VTTXPAD9
B9
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
Negative differential transmit port of the multi
gigabit transceiver.
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Table 5 – Virtex-II Pro Board Bottom MGT16 and 18
RocketIO
Port #
Signal Name
AVCCAUXRX16
Virtex-II Pro
Pin #
AN6
VTRXPAD16
AN7
RXNPAD16
AP6
RXPPAD16
AP7
GNDA16
AM8
TXNPAD16
AP9
TXPPAD16
AP8
AVCCAUXTX16
AN8
VTTXPAD16
AN9
AVCCAUXRX18
AN14
VTRXPAD18
AN15
RXNPAD18
AP14
RXPPAD18
AP15
GNDA18
AM15
4
5
October 27, 2004
Description
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
Negative differential transmit port of the multi
gigabit transceiver.
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Negative differential receive port of the multi
gigabit transceiver.
Positive differential receive port of the multi
gigabit transceiver.
Ground for the analog circuitry of the multi
gigabit transceiver.
8
RocketIO
Port #
6
7
TXNPAD18
AP17
TXPPAD18
AP16
AVCCAUXTX18
AN16
VTTXPAD18
AN17
Negative differential transmit port of the multi
gigabit transceiver.
Positive differential transmit port of the multi
gigabit transceiver.
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
Table 6 – Virtex-II Pro Board Bottom MGT19 and 21
Signal Name
Virtex-II Pro
Description
Pin #
AVCCAUXRX19
AN18
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
VTRXPAD19
AN19
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
RXNPAD19
AP18
Negative differential receive port of the multi
gigabit transceiver.
RXPPAD19
AP19
Positive differential receive port of the multi
gigabit transceiver.
GNDA19
AM20
Ground for the analog circuitry of the multi
gigabit transceiver.
TXNPAD19
AP21
Negative differential transmit port of the multi
gigabit transceiver.
TXPPAD19
AP20
Positive differential transmit port of the multi
gigabit transceiver.
AVCCAUXTX19
AN20
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
VTTXPAD19
AN21
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
AVCCAUXRX21
AN26
Analog power supply for receive circuitry of
the multi gigabit transceiver (2.5V).
VTRXPAD21
AN27
Receive termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
RXNPAD21
AP26
Negative differential receive port of the multi
gigabit transceiver.
RXPPAD21
AP27
Positive differential receive port of the multi
gigabit transceiver.
GNDA21
AM27
Ground for the analog circuitry of the multi
gigabit transceiver.
TXNPAD21
AP29
Negative differential transmit port of the multi
gigabit transceiver.
TXPPAD21
AP28
Positive differential transmit port of the multi
gigabit transceiver.
AVCCAUXTX21
AN28
Analog power supply for transmit circuitry of
the multi gigabit transceiver (2.5V).
VTTXPAD21
AN29
Transmit termination supply for the multi
gigabit transceiver (1.8V to 2.8V).
October 27, 2004
9
3.2.1 MGT Reference Clock Inputs
The top and bottom MGT ports have two sources for the reference clock input. A dedicated
programmable LVDS synthesizer is used to provide a variable clock source to the top and bottom
MGT ports to support up to 3.125Gbps data rate. The top and bottom MGT ports are also
provided with a dedicated pair of differential SMA connectors for user clock inputs. The following
figure shows the clock sources provided to the MGT ports.
SMA
Connectors
SMA
Connectors
Programmable
LVDS Clock
Source
BREFCLK Clock Inputs
(Bank 0)
Top MGTs
BREFCLK2 Clock Inputs
(Bank 1)
Virtex-II Pro™
XC2VP20/P30/P40/P50-FF1152
BREFCLK Clock Inputs
(Bank 5)
Bottom MGTs
BREFCLK2 Clock Inputs
(Bank 4)
Programmable
LVDS Clock
Source
SMA
Connectors
SMA
Connectors
The differential clock outputs of the Programmable LVDS Clock Source that are connected to the
SMA connectors, are the same as the clock outputs going to the BREFCLK clock inputs of the top
and bottom MGT ports. Hence, the clock outputs at the SMA connectors can be used to provide a
trigger input to the scope during MGT testing.
3.2.2 MGT SMA Connectors
The MGT SMA connectors on the board can be used as general-purpose high-speed serial links
to support data rates up to 3.125Gbps. The Virtex-II Pro development board uses four of these
MGT ports to support a 10GbE interface via using a 10GbE P160 module.
October 27, 2004
10
3.2.3 GbE Interface
The following figure shows a high-level block diagram of the GbE interface on the FF1152
development board. This interface utilizes two of the bottom MGT ports and a set of low-speed
control signals to interface to two Infineon iSFP modules. The programmable LVDS synthesizer
on the board is used to operate the MGT ports at 1.25Gbps to meet the GbE data rate.
MGT19
1.25Gbps
Control
Infineon
iSFP GbE
Module
GbE
Infineon
iSFP GbE
Module
GbE
Virtex-II Pro FPGA
P20/P30
(FF1152)
MGT21
1.25Gbps
Control
Figure 3 - GbE Interface Using iSFP Modules
3.2.4 Infineon iSFP Gb Module
The Gb interface is designed around the Intelligent Small Form-factor Pluggable (iSFP) and the
Small Form-factor Pluggable (SFP) modules from Infineon. Two Infineon tri-mode modules (part #
V23848-M305-C56) are included in the iSFP kit, although any SFP compatible module can be
used.
The Infineon iSFP family is based on the Physical Medium Depend (PMD) sub-layer and baseband medium compliant to SONET OC-48 SR-1 and SDH STM I-16. This transceiver supports
the LC™ connection concept that is compatible with RJ-45 style interconnect. The module is
designed to support data rates from 155Mbps to 2.67Gbps. The following figure shows the iSFP
module from Infineon. For more information, please refer to the Infineon iSFP module data sheet.
Figure 4 - iSFP Module (photo taken from Infineon Web Page)
October 27, 2004
11
3.2.5 Host Board Connector
The iSFP module connects to the FF1152 board via the Host Board Connector (the FF1152
board acts as the Host Board for the iSFP module). This 20-pin connector provides connections
for power, ground, high-speed serial link, and the low-speed control signals for controlling the
operation of the iSFP module.
Figure 5 - Host Board Connector AMP 1367073-1 (photo taken from AMP Web Page)
The following table shows the Host Board Connector pin assignments and provides a brief
description of each signal.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 7 – iSFP Host Connector Pin Description
Name
Function
VEET
Transmitter Ground
Tx Fault
Transmitter Fault Indication
Tx Disable
Transmitter Disable
MOD-DEF(2) Module Definition 2 (Serial Interface Data Line)
MOD-DEF(1) Module Definition 1 (Serial Interface Clock Line)
MOD-DEF(0) Module Definition 0 (Module Present Signals, active low)
Rate Select
Not Connected
LOS
Loss of Signal
VEER
Receiver Ground
VEER
Receiver Ground
VEER
Receiver Ground
RDInverse Received Data Out
RD+
Received Data Out
VEER
Receiver Ground
VCCR
Receiver Power
VCCT
Transmitter Power
VEET
Transmitter Ground
TD+
Transmitter Data In
TDInverse Transmitter Data In
VEET
Transmitter Ground
October 27, 2004
12
iSFP GbE
Module Connector
iSFP_TD1_P
iSFP_RD1_N
TD+
TDRD+
RD-
iSFP_TR1_TXDISABLE
iSFP_TR1_RATESELECT
iSFP_TR1_MODDEF2
iSFP_TR1_MODDEF1
iSFP_TR1_MODDEF0
iSFP_TR1_TXFAULT
iSFP_TR1_LOS
Tx Disable
Rate Select
MOD-DEF(2)
MOD-DEF(1)
System Interface
iSFP_TD1_N
iSFP_RD1_P
GbE
MOD-DEF(0)
Tx Fault
LOS
Virtex-II Pro FPGA
P20/P30/P40/P50FF1152
iSFP GbE
Module Connector
iSFP_TD2_P
iSFP_RD2_N
iSFP_TR2_TXDISABLE
iSFP_TR2_RATESELECT
iSFP_TR2_MODDEF2
iSFP_TR2_MODDEF1
iSFP_TR2_MODDEF0
iSFP_TR2_TXFAULT
iSFP_TR2_LOS
TD+
TDRD+
RD-
Tx Disable
Rate Select
MOD-DEF(2)
MOD-DEF(1)
System Interface
iSFP_TD2_N
iSFP_RD2_P
GbE
MOD-DEF(0)
Tx Fault
LOS
Figure 6 – iSFP Module Interface to the Virtex-II Pro FPGA
October 27, 2004
13
Table 8 – iSFP Pin Assignments
Signal Name
Virtex-II Pro Pin #
iSFP #1
iSFP_TD1_P
iSFP_TD1_N
iSFP_RD1_P
iSFP_RD1_N
iSFP_TR1_LOS
iSFP_TR1_MODDEF0
iSFP_TR1_MODDEF1
iSFP_TR1_MODDEF2
iSFP_TR1_RATESELECT
iSFP_TR1_TXDISABLE
iSFP_TR1_TXFAULT
AP28
AP29
AP27
AP26
AL29
AL24
AM24
AL27
AM28
AL28
AL30
iSFP #2
iSFP_TD2_P
iSFP_TD2_N
iSFP_RD2_P
iSFP_RD2_N
iSFP_TR2_LOS
iSFP_TR2_MODDEF0
iSFP_TR2_MODDEF1
iSFP_TR2_MODDEF2
iSFP_TR2_RATESELECT
iSFP_TR2_TXDISABLE
iSFP_TR2_TXFAULT
3.3
AP20
AP21
AP19
AP18
AM22
AL19
AL20
AL21
AL22
AM21
AL23
LVDS Interface
The FF1152 development board provides high-speed LVDS connectors supporting a SPI-4.2
interface. This interface consists of 36 LVDS signal pairs (72 FPGA signals) and 6 single-ended
signals. In addition to the SPI-4.2 interface, the LVDS interface is designed to support XSBI 16-bit
LVDS @644Mbps to support a 10GbE interface on the FF1152 development platform. The
following sections provide a brief description of the LVDS interface on this development board.
3.3.1 SPI-4.2 Interface
The FF1152 development board provides a SPI-4.2 via a 16-bit parallel LVDS electrical interface.
The following figure shows the SPI-4.2 interface on the board. The transmit and receive interface
of the SPI-4.2 are implemented using LVDS signals while the status flow control signals are
implemented using single-ended LVTTL signals.
October 27, 2004
14
LVDS Signals
SysClk_P
TDat[15:0]
TDat[15:0]
SysClk_N
TDClk
TDClk
TCtl
TCtl
Transmit
Link Layer
TStat[1:0]
TStat[1:0]
TSClk
TSClk
LVTTL Signals
LVDS
Connectors
Virtex-II Pro FPGA
P20/P30-FF1152
LVDS Signals
RDat[15:0]
RDat[15:0]
RDClk
RDClk
RCtl
RCtl
Receive
Link Layer
RStat[1:0]
RStat[1:0]
RSClk
RSClk
LVTTL Signals
Figure 7 - SPI-4.2 Interface
3.3.2 SPI-4.2 Pin Assignments
The following table shows the SPI-4.2 pin assignments for the 2VP20/P30/P40/P50 FPGA in the
FF1152-pin package. These pin assignments must be used in the board design in order to meet
the SPI-4.2 interface core requirements.
Table 9 – SPI-4.2 Transmit Pin Assignments
Virtex-II Pro
Pin #
E17
AK28
October 27, 2004
LVDS Signal
Name
5.0V
5.0V
GND
3.3V
3.3V
GND
2.5V
2.5V
GND
TSCLK
NC
GND
TSTAT0
J29 Connector Pin #
LVDS TX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LVDS Signal
Name
5.0V
5.0V
GND
3.3V
3.3V
GND
2.5V
2.5V
GND
NC
NC
GND
NC
Virtex-II Pro
Pin #
15
AK29
AA33
AB33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
AA25
AD34
AE34
AC29
AC28
AD30
AD29
AD28
AD27
TSTAT1
GND
TDat_N(15)
TDat_P(15)
GND
TDat_N(13)
TDat_P(13)
TDat_N(11)
TDat_P(11)
GND
TDat_N(9)
TDat_P(9)
GND
TDat_N(7)
TDat_P(7)
GND
TDat_N(5)
TDat_P(5)
GND
TDat_N(3)
TDat_P(3)
GND
TDat_N(1)
TDat_P(1)
GND
TCtl_N
TCtl_P
GND
GND
GND
GND
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
NC
GND
TDat_N(14)
TDat_P(14)
GND
TDat_N(12)
TDat_P(12)
TDat_N(10)
TDat_P(10)
GND
TDat_N(8)
TDat_P(8)
GND
TDat_N(6)
TDat_P(6)
GND
TDat_N(4)
TDat_P(4)
GND
TDat_N(2)
TDat_P(2)
GND
TDat_N(0)
TDat_P(0)
GND
TDCLK_N
TDCLK_P
GND
GND
GND
GND
W26
W25
Y26
Y25
AB32
AB31
AB30
AB29
AC32
AC31
AB28
AB27
AB26
AB25
AE33
AF33
AE31
AE30
Table 10 – SPI-4.2 Receive Pin Assignments
Virtex-II Pro
Pin #
AK22
AK24
AK27
H33
H34
K30
October 27, 2004
LVDS Signal
Name
5.0V
5.0V
GND
3.3V
3.3V
GND
2.5V
2.5V
GND
RSCLK
NC
GND
RSTAT0
RSTAT1
GND
RDat_N(15)
RDat_P(15)
GND
RDat_N(13)
J30 Connector Pin #
LVDS RX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LVDS Signal
Name
5.0V
5.0V
GND
3.3V
3.3V
GND
2.5V
2.5V
GND
NC
NC
GND
NC
NC
GND
RDat_N(14)
RDat_P(14)
GND
RDat_N(12)
Virtex-II Pro
Pin #
M25
M26
L27
16
K31
L29
L30
M28
M29
L31
L32
N29
N30
N31
N32
P29
P30
R28
R29
RDat_P(13)
RDat_N(11)
TDat_P(11)
GND
RDat_N(9)
RDat_P(9)
GND
RDat_N(7)
RDat_P(7)
GND
RDat_N(5)
RDat_P(5)
GND
RDat_N(3)
RDat_P(3)
GND
RDat_N(1)
RDat_P(1)
GND
RCtl_N
RCtl_P
GND
GND
GND
GND
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
RDat_P(12)
RDat_N(10)
RDat_P(10)
GND
RDat_N(8)
RDat_P(8)
GND
RDat_N(6)
RDat_P(6)
GND
RDat_N(4)
RDat_P(4)
GND
RDat_N(2)
RDat_P(2)
GND
RDat_N(0)
RDat_P(0)
GND
RDCLK_N
RDCLK_P
GND
GND
GND
GND
L28
N25
N26
N27
N28
P25
P26
P27
P28
R25
R26
T24
U24
E18
D18
3.3.3 LVDS Connector
The design of the SPI-4.2 interface requires use of a high-speed and high quality connector. The
FF1152 development board uses the SAMTEC QSE type connector for this interface. The QSE040-01-L-Dx-A connector from SAMTEC provides up to 28 LVDS signals connections in addition
to adequate number ground connections for improving the signal quality. Two of these connectors
are used on the FF1152 development board to implement the SPI-4.2 interface. In addition, a
mating LVDS cable is available from Samtec (part number #EQCD-040-06.00-TTR-TBL-1). The
following figure shows the QSE type connector from SAMTEC (the picture is obtained from the
SAMTEC web site (www.samtec.com)).
Figure 8 – SAMTEC QSE Type Connector for the SPI-4.2 Interface
October 27, 2004
17
3.4
Memory
The FF1152 development board provides two separate interfaces to physical memory blocks. A
dedicated set of pins interface to 32 MB of SDRAM and another set of FPGA pins provide an
interface to a second 32 MB block of SDRAM. These two dedicated memory interfaces improve
the performance of the processor-based designs in networking applications where 10GbE and/or
GbE ports are utilized.
A typical application of this dual-memory subsystem design would be a PowerPC based design
where the processor executes code from the SDRAM and also sets up a DMA controller to move
data to/from a high-speed serial link such as 10GbE and the second memory bank. The following
figure shows the Virtex-II Pro interface to the SDRAM banks. These interfaces will be described
in the subsequent sections.
3.4.1 Two Blocks of x32 Memory Configuration
Address[0:13]
Data[0:31]
SDRAM
(32MB)
Control
Virtex-II Pro FPGA
P20/P30
(FF1152)
Address[0:13]
Data[0:31]
SDRAM
(32MB)
Control
Figure 9 – 32-bit SDRAM Interface
October 27, 2004
18
3.4.2 Single Block of x64 Memory Configuration
Address[0:13]
Virtex-II Pro FPGA
P20/P30
(FF1152)
Data[0:63]
SDRAM
(64MB)
Control
Figure 10 - 64-bit SDRAM Interface
3.4.3 SDRAM Interfaces
The following figure shows the SDRAM interfaces on the FF1152 development board.
Data[15:0]
Addr[13:0]
BA[1:0]
DQM1
DQM0
CSn
RASn
CASn
WEn
CLKE
CLK
8M x 16
SDRAM
Virtex-II Pro
FPGA
Data[31:16]
DQM3
DQM2
8M x 16
SDRAM
Figure 11 - SDRAM Interface
Table 11 – SDRAM1 Interface Pin Assignments
Signal Name
sdram1_addr[0]
sdram1_addr[1]
sdram1_addr[2]
October 27, 2004
Description
Address 0
Address 1
Address 2
FPGA Pin #
AD6
W5
V5
19
sdram1_addr[3]
sdram1_addr[4]
sdram1_addr[5]
sdram1_addr[6]
sdram1_addr[7]
sdram1_addr[8]
sdram1_addr[9]
sdram1_addr[10]
sdram1_addr[11]
sdram1_addr[12]
sdram1_addr[13]
sdram1_dq[0]
sdram1_dq[1]
sdram1_dq[2]
sdram1_dq[3]
sdram1_dq[4]
sdram1_dq[5]
sdram1_dq[6]
sdram1_dq[7]
sdram1_dq[8]
sdram1_dq[9]
sdram1_dq[10]
sdram1_dq[11]
sdram1_dq[12]
sdram1_dq[13]
sdram1_dq[14]
sdram1_dq[15]
sdram1_dq[16]
sdram1_dq[17]
sdram1_dq[18]
sdram1_dq[19]
sdram1_dq[20]
sdram1_dq[21]
sdram1_dq[22]
sdram1_dq[23]
sdram1_dq[24]
sdram1_dq[25]
sdram1_dq[26]
sdram1_dq[27]
sdram1_dq[28]
sdram1_dq[29]
sdram1_dq[30]
sdram1_dq[31]
sdram1_ba[0]
sdram1_ba[1]
sdram1_dqm[0]
sdram1_dqm[1]
sdram1_dqm[2]
sdram1_dqm[3]
sdram1_csn
sdram1_rasn
sdram1_casn
sdram1_wen
sdram1_clk
sdram1_clke
October 27, 2004
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 17
Data 18
Data 19
Data 20
Data 21
Data 22
Data 23
Data 24
Data 25
Data 26
Data 27
Data 28
Data 29
Data 30
Data 31
Bank Select 0
Bank Select 1
Write Mask0
Write Mask1
Write Mask2
Write Mask3
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Clock
Clock Enable
AH6
Y6
V7
W6
W7
Y7
AA6
AA5
AB7
AA7
AD7
AB3
V4
AB4
W3
AA4
W4
AA3
Y4
Y1
AA1
Y2
AB1
AA2
AC1
AB2
AC2
AE4
AF4
AF3
AK4
AK3
AC4
AC3
AD4
AD2
AE2
AE1
AG1
AF2
AL1
AG2
AL2
V6
AD5
Y3
W2
AD3
AD1
AB5
AH5
AC6
AE5
AC7
AB6
20
Table 12 – SDRAM2 Interface Pin Assignments
Signal Name
sdram2_addr[0]
sdram2_addr[1]
sdram2_addr[2]
sdram2_addr[3]
sdram2_addr[4]
sdram2_addr[5]
sdram2_addr[6]
sdram2_addr[7]
sdram2_addr[8]
sdram2_addr[9]
sdram2_addr[10]
sdram2_addr[11]
sdram2_addr[12]
sdram2_addr[13]
sdram2_dq[0]
sdram2_dq[1]
sdram2_dq[2]
sdram2_dq[3]
sdram2_dq[4]
sdram2_dq[5]
sdram2_dq[6]
sdram2_dq[7]
sdram2_dq[8]
sdram2_dq[9]
sdram2_dq[10]
sdram2_dq[11]
sdram2_dq[12]
sdram2_dq[13]
sdram2_dq[14]
sdram2_dq[15]
sdram2_dq[16]
sdram2_dq[17]
sdram2_dq[18]
sdram2_dq[19]
sdram2_dq[20]
sdram2_dq[21]
sdram2_dq[22]
sdram2_dq[23]
sdram2_dq[24]
sdram2_dq[25]
sdram2_dq[26]
sdram2_dq[27]
sdram2_dq[28]
sdram2_dq[29]
sdram2_dq[30]
sdram2_dq[31]
sdram2_ba[0]
sdram2_ba[1]
sdram2_dqm[0]
sdram2_dqm[1]
sdram2_dqm[2]
sdram2_dqm[3]
sdram2_csn
October 27, 2004
Description
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 17
Data 18
Data 19
Data 20
Data 21
Data 22
Data 23
Data 24
Data 25
Data 26
Data 27
Data 28
Data 29
Data 30
Data 31
Bank Select 0
Bank Select 1
Write Mask0
Write Mask1
Write Mask2
Write Mask3
Chip Select
FPGA Pin #
T6
M6
L5
U6
M7
F7
L6
L7
N7
N6
N5
R9
P7
U7
M3
F5
N4
F4
M4
K5
L3
L4
H1
K2
J2
L2
K1
M2
L1
M1
R3
T3
T4
U3
U4
P4
N3
R4
N1
P1
P2
R1
R2
U2
T2
V2
J7
R6
K4
H2
P3
N2
P5
21
sdram2_rasn
sdram2_casn
sdram2_wen
sdram2_clk
sdram2_clke
3.5
Row Address Strobe
Column Address Strobe
Write Enable
Clock
Clock Enable
U5
R7
T5
T7
P6
Clock Sources
The Clock Generation section of the Virtex-II Pro system board provides all necessary clocks for
the PowerPC processor and the RocketIO transceivers integrated into the Virtex-II Pro FPGA. In
general, the clock sources on the board are grouped into two categories, differential and singleended clock sources. The differential clock sources are primarily used by the RocketIO
transceivers, while the single-ended clock sources are used by the processor section. The
differential clock sources consist of:
•
•
•
•
•
A programmable LVDS clock source providing a reference clock input to the top MGTs
A pair of SMA connectors to provide a clock input to the top MGTs
A programmable LVDS clock source providing a reference clock input to the bottom
MGTs
A pair of SMA connectors to provide a clock input to the bottom MGTs
A programmable LVDS clock source providing a reference clock input for the LVDS
interface
An on-board 100MHz oscillator provides the system clock input to the processor section. This
100Mhz clock will be used by the Virtex-II Pro Digital Clock Managers (DCMs) to generate
various processor clocks. In addition to the above clock inputs, a socket is provided on the
system board that can be used to provide single ended LVTTL clock input to the FPGA via an 8
or 4-pin oscillator. The following table shows the clock sources on the Virtex-II Pro system board.
The following figure shows the clock resources on the FF1152 development board. It should be
noted that all sixteen global clock inputs of the Virtex-II Pro FPGA are utilized in this design.
October 27, 2004
22
SMA
Connectors
H18
J18
D18
E18
TSCLK
D17
Bank 0 Clock Inputs
E17
H17
SMA_MGT_TOP_P
From SPI-4.2
SAM TSCLK
SMA
Connectors
SMA_MGT_TOP_N
From
To
OSC
P160 FPGA Socket
Module I/O
FPGA_GCLK0
RDCLK_N
SPI-4.2
RDCLKP, N
RDCLK_P
CLK_MGT_TOP_P
CLK_MGT_TOP_N
Programmable
LVDS Clock
Source
J17
Bank 1 Clock Inputs
Virtex-II Pro™
XC2VP20/P30-FF1152
Programmable
LVDS Clock
Source
From
P160
Module
LVTTL OSC
@100MHz
AK17 AL17
SMA_MGT_BOT_P
AH17
SMA_MGT_BOT_N
AJ17
CLK_100
AJ18
P160_CLK1
CLK_MGT_BOT_N
Programmable
LVDS Clock
Source
AH18
SYSCLK_N
AL18
Bank 4 Clock Inputs
SYSCLK_P
AK18
CLK_MGT_BOT_P
Bank 5 Clock Inputs
SMA
Connectors
SMA Connectors
Figure 12 - Clock Sources on the FF1152 Board
October 27, 2004
23
The following table provides a brief description of each clock input to the Virtex-II Pro FPGA.
Table 13 - Clock Sources
Signal
Name
SMA_MGT_TOP_P,
SMA_MGT_TOP_N
FPGA
Pin #
J17, H17
SMA_MGT_BOT_P,
SMA_MGT_BOT_N
AL17, AK17
CLK_MGT_TOP_P,
CLK_MGT_TOP_N
J18, H18
CLK_MGT_BOT_P,
CLK_MGT_BOT_N
AK18, AL18
RDCLK_P,
RDCLK_N
D18, E18
SYSCLK_P,
SYSCLK_N
AH18, AJ18
P160_CLK1
AJ17
CLK_100
AH17
FPGA_GCLK0
D17
TSCLK
E17
October 27, 2004
Description
Top MGT BREFCLK2 Clock Input – These clock inputs are
connected to a pair of SMA connectors. User can provide clock
input to the top MGTs via these connectors. The user clock input
must meet the MGT clock input requirements. Refer to the
RocketIO user’s guide for more information on the MGT clock
input requirements.
Bottom MGT BREFCLK2 Clock Input – These clock inputs are
connected to a pair of SMA connectors. User can provide clock
input to the bottom MGTs via these connectors. The user clock
input must meet the MGT clock input requirements. Refer to the
RocketIO user’s guide for more information on the MGT clock
input requirements.
Top MGT BREFCLK Clock Input – These clock inputs are
connected to the output of an LVDS clock synthesizer. This
programmable clock source can generate a clock frequency of
25 to 700MHz. Refer to the Programmable LVDS Clock Source
section for more information.
Bottom MGT BREFCLK Clock Input – These clock inputs are
connected to the output of an LVDS clock synthesizer. This
programmable clock source can generate a clock frequency of
25 to 700MHz. Refer to the Programmable LVDS Clock Source
section for more information.
Positive and Negative Differential SPI-4.2 Receive Clock
Inputs – These clock inputs are connected to the LVDS receive
connector on the Virtex-II Pro board. For the SPI-4.2
applications, these clock inputs are the SPI-4.2 receive clock
outputs.
Positive and Negative Differential System Clock Inputs –
These clock inputs are connected to the output of an LVDS clock
synthesizer. This programmable clock source can generate a
clock frequency of 25 to 700MHz. Refer to the Programmable
LVDS Clock Source section for more information.
P160 Module Clock Input – This clock input is connected to the
P160 connector located on the Virtex-II Pro board.
System Clock – This clock input is connected to a 100MHz
LVTTL oscillator.
LVTTL Clock Input – This clock input can be configured to be
connected to the SystemACE Module (SAM) clock output, P160
clock output, or the LVTTL socket on the Virtex-II Pro board. This
clock configuration is described in the following section.
SPI-4.2 Transmit Status Clock Input – This clock input is
connected to the SPI-4.2 transmit status clock output.
24
3.5.1 FPGA_GCLK0 Clock Source
SAM Clock
JP25
6
5
OSC
Socket
FPGA I/O Pin
4
3
2
1
Virtex-II Pro
FPGA
P160 Clock
Figure 13 – FPGA_GCLK0 Clock Source Jumper Settings
Global Clock
Input Source
OSC Socket
Installed
Jumpers
3-4
3-4 and 5-6
P160 Clock
1-3
SAM Clock
3-5
Table 14 – JP25 Jumper Settings
Usage
Any application needing a single ended clock
Using the MPU interface of the SAM in applications where this
interface needs to be synchronized to the OSC socket rather
than the SAM clock. In this case, SAM clock is input to the SAM.
P160 modules needing a clock connection to the FPGA global
clock input
Using the MPU interface of the SAM
The following table shows the jumper settings for routing the P160 clock to the FPGA I/O pin
when the FPGA global clock input is used by SAM or, if a connection from the OSC socket to the
global clock input is needed.
Table 15 – Jumper Settings for Routing the P160 Clock to FPGA I/O Pin
Installed
Usage
Jumpers
1-2
P160 clock can be routed to the FPGA I/O pin for applications where the global
clock input is used by the OSC socket or the SAM clock, and the P160 clock
needs to be routed to the FPGA as well.
2-4
The OSC socket can be routed to the FPGA I/O pin for applications where the
global clock input is used by the P160 clock or the SAM clock, and the OSC
socket needs to be routed to the FPGA as well.
October 27, 2004
25
3.5.2 Programmable LVDS Clock Sources
Three programmable LVDS clock synthesizers are used on the Virtex-II Pro development board
to generate reference clock input to the top MGTs, bottom MGTs, and LVDS interface. The use of
this variable clock source, allows designers to prototype various interconnect technologies with
different clock source requirements.
3.5.3 ICS8442 Programmable LVDS Clock Synthesizer
The Virtex-II Pro development board design uses the ICS8442 LVDS clock synthesizer for
generating various clock frequencies. A list of features included in the ICS8442 device are shown
below.
•
•
•
•
•
Output frequency range: 25MHz to 700MHz
RMS period jitter: 2.7ps (typical)
Cycle-to-cycle jitter: 27ps (typical)
Output rise and fall time: 650ps (maximum)
Output duty cycle: 48/52
The following figure shows a high-level block diagram of the ICS8442 programmable LVDS clock
synthesizer.
N[0:1]
nP_LOAD
Parallel Load
M[0:8]
VCO_SEL
MR
TEST
XTAL1
XTAL2
Control Inputs
TEST_CLK
ICS8442
FOUT0
nFOUT0
FOUT1
nFOUT1
Clock Input
XTAL_SEL
CLKOUT0
S_LOAD
CLKOUT1
S_CLOCK
Serial Load
S_DATA
Figure 14 – ICS8442 Clock Synthesizer
October 27, 2004
26
Table 16 – ICS8442 Clock Synthesizer Pin Description
Signal Name
M[0:4], M[6:8]
M[5]
N[0:1]
Direction
Input
Input
Input
TEST
Pull up/Pull down
Pull down
Pull up
Pull down
Output
MR
S_CLOCK
Input
Input
Pull down
Pull down
S_DATA
S_LOAD
Input
Input
Pull down
Pull down
TEST_CLK
nP_LOAD
Input
Input
Pull down
Pull down
XTAL1, XTAL2
XTAL_SEL
Input
Input
Pull up
VCO_SEL
Input
Pull up
FOUT0, FOUT1
nFOUT0, nFOUT1
Output
Output
Description
The M divider inputs, latched on the rising edge
of the nP_LOAD signal.
The N divider inputs, latched on the rising edge
of the nP_LOAD signal.
The TEST output is active during the serial mode
of operations. Please refer to the datasheet for
more information.
Active high reset signal.
Serial interface clock input. Data is shifted into
the device on the rising edge of this clock.
Serial interface data input.
Serial interface load signal. The contents of the
serial data shift register is loaded into the internal
dividers on the rising edge of this signal.
Test clock input.
The rising edge of this signal is used to load the
M and N divider inputs into the device.
Crystal clock input/output
This signal is used to select between the crystal
and the TEST_CLK input to the device. When
this high, crystal is selected.
This signal is used to place the internal PLL in
the bypass mode. When this signal is set to low,
the PLL is placed in the bypass mode. For
normal operations, this signal must be set to
high.
Positive LVDS clock outputs
Negative LVDS clock outputs
The Input Clock Select signals of the ICS8442 can be used to provide a reference clock input to
the device other than the 25MHz crystal oscillator (for test purposes). The following table shows
how these Input Clock Select signals are used to generate the output clock or to test the ICS8442
device. Please refer to the ICS8442 datasheet for more information on using the TEST_CLK
clock input.
Table 17 – Input Clock Select Signal Description
VCO_SEL
0
XTAL_SEL
0
0
1
25MHz crystal
1
1
0
1
TEST_CLK
25MHz crystal
October 27, 2004
Reference Clock Input
TEST_CLK
FOUT[0:1]
TEST_CLK/N (the TEST_CLK must be between
10 and 25MHz). This mode can be used to test
the ICS8442 device by routing the input clock to
the outputs.
25MHz crystal/N (This mode can be used to test
the ICS8442 device by routing the 25MHz
crystal clock to the outputs).
ICS8442 PLL Output/N (Normal Operation)
ICS8442 PLL Output/N (Normal Operation)
27
3.5.4 ICS8442 Clock Generation
The ICS8442 output clocks are generated based on the following formula (assuming the crystal
clock input is set to 25MHz):
FOUT[0:1] = 25 x M/N
Where 8 < M < 28 and N can take a value of 1, 2, 4, or 8. The variable M is determined by setting
the binary number M[0:8] while N is set according to the following table:
Table 18 – ICS8442 N Settings
N[1:0]
N
00
01
10
11
1
2
4
8
Output Clock Frequency Range (MHz)
Minimum
Maximum
200
700
100
350
50
175
25
87.5
For example, to generate a 62.5MHz clock, N[1:0] will be set to “10” (it can also be set to “11”
since either one will be the correct frequency range for the 62.5MHz clock) and M will be set to
“000001010” (decimal 10). So, from the above formula:
FOUT[0:1] = 25 x 10/4 = 62.5Mhz
The following table shows how the M and N values can be set to generate a clock source for a
few common applications. All the values for M and N are based on the 25MHz crystal clock input
to the ICS8442 device. A complete list of frequencies generated by the ICS8442 (based on a
25MHz input clock) are provided in the following sections.
Table 19 – Examples of the ICS8442 M and N Settings
Interconnect
Technology
Gigabit Ethernet
Fiber Channel
Infiniband
XAUI
FOUT0 and
FOUT1 (MHz)
62.5
53.125
106.25
125
156.25
M8
0
0
0
0
0
M7
0
0
0
0
0
M6
0
0
0
0
0
ICS8442 M and N Settings
M5 M4 M3 M2 M1
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
M0
0
1
1
0
1
N1
1
1
1
1
1
N0
0
1
0
0
0
3.5.5 ICS8442 Programming Modes
The ICS8442 provides two different methods of programming the M and N values into the device,
a Parallel Mode and a Serial Mode. In parallel mode, M and N values are programmed into the
device when the nP_LOAD signal pulses low. In the serial mode, the I2C pins (S_DATA and
S_CLOCK) along with the S_LOAD signal are used to shift the M and N values into the device.
Please refer to the ICS8442 datasheet for more information on programming modes of loading
the M and N values into the device.
3.5.6 ICS8442 M and N Settings
The following figure shows how the ICS8442 programmable LVDS clock synthesizer is used on
the Virtex-II Pro board. DIP switches are provided on the board for manual setting of the M and N
values for each ICS8442.
October 27, 2004
28
nFOUT1
SMA
Connectors
CLKOUT1
FOUT1
M[0:8]
N[0:1]
nP_LOAD
Parallel Load
DIP Switch
nFOUT0
CLKOUT0
FOUT0
Virtex-II Pro
FPGA
S_CLOCK
S_LOAD
Serial Load
S_DATA
ICS8442
XTAL_SEL
TEST_CLK
MR
TEST
Control Inputs
VCO_SEL
25Mhz
Figure 15 – ICS8442 Clock Synthesizer Interface to the FPGA
As shown in the above figure, the ICS8442 device outputs two identical LVDS clock sources. One
of these clock sources can be used to provide the reference clock input to the MGTs on the
Virtex-II Pro development board, while the other clock output can be used to trigger a scope
during testing of the gigabit link. The second output could also be used to provide an LVDS clock
source to a user board.
October 27, 2004
29
SYSCLK_N
SW12
M[8:0]
SW13
N1:0]
CONTROL
CLK_MGT_TOP_N
CLKOUT1
SMA
Connectors
SMA
Connectors
CLK_MGT_TOP_P
ICS8442
Synth #2
25Mhz
SYSCLK_P
SYSCLK_N
SMA
Connectors
SYSCLK_P
CLKOUT1
M[8:0]
N1:0]
SW11
SW10
Virtex-II Pro
FPGA
M[8:0]
CONTROL
N1:0]
CLK_MGT_TOP_N
CLK_MGT_BOT_N
25Mhz
CLKOUT0
CLK_MGT_TOP_P
CLK_MGT_BOT_P
ICS8442
Synth #1
CLKOUT0
SW1
SW9
CONTROL
CLKOUT1
CLK_MGT_BOT_N
CLKOUT0
CLK_MGT_BOT_P
ICS8442
Synth #3
25Mhz
Figure 16 – ICS8442 Clock Synthesizer M and N DIP Switches
The following tables show the DIP switch settings for M and N selections. Please refer to Table
20 for the information on pull-up and pull-down resistors provided internal to the ICS8442 device
for the M and N input signals.
October 27, 2004
30
3.3V
SW1, SW2, or SW10
ON OFF
10
9
M0
8
M1
7
M2
6
M3
5
M4
4
M5
2
Synthesizer
M6 #1, #2, or #3
M7
1
M8
3
SW9, SW11, or SW13
ON OFF
2
1
N0
N1
Figure 17 – M and N DIP Switches for the Synthesizers
Table 20 – DIP Switch Setting for M[8:0]
Switch Position
SW1, SW10, and SW2
DIP1
DIP2
DIP3
DIP4
DIP5
DIP6
DIP7
DIP8
DIP9
DIP10
M[8:0]
M8
M7
M6
M5
M4
M3
M2
M1
M0
Unused
OFF
0
0
0
1
0
0
0
0
0
NA
ON
1
1
1
0 Note (1)
1
1
1
1
1
NA
Note(1) – The polarity of M5 (DIP4) is the opposite of all other DIP switch positions.
Table 21 – DIP Switch Setting for N[1:0]
Switch Position
SW9, SW11, and SW13
DIP1
DIP2
N[1:0]
N1
N0
OFF
0
0
ON
1
1
The following table shows a complete list of frequencies generated by the ICS8442 device based
on a 25MHz crystal reference clock input.
October 27, 2004
31
Table 22 – Synthesizer Clock Outputs for M and N Values
M[8:0]
N[1:0]
FOUT[1:0] (MHz)
M[8:0]
N[1:0]
FOUT[1:0] (MHz)
000001000
000001001
000001010
000001011
000001100
000001101
000001110
000001111
000001000
000010000
000010001
000001001
000010010
000010011
000001010
000010100
000010101
000001011
000010110
000010111
000001100
000011000
000011001
000001101
000011010
000011011
000001110
000011100
000001111
000001000
000010000
000010001
000001001
000010010
000010011
000001010
000010100
000010101
000001011
000010110
000010111
000001100
11
11
11
11
11
11
11
11
10
11
11
10
11
11
10
11
11
10
11
11
10
11
11
10
11
11
10
11
10
01
10
10
01
10
10
01
10
10
01
10
10
01
25 (Min)
28.125
31.25
34.375
37.5
40.625
43.75
46.875
50
50
53.125
56.25
56.25
59.375
62.5
62.5
65.625
68.75
68.75
71.875
75
75
78.125
81.25
81.25
84.375
87.5
87.5
93.75
100
100
106.25
112.5
112.5
118.75
125
125
131.25
137.5
137.5
143.75
150
000011000
000011001
000001101
000011010
000011011
000001110
000011100
000001111
000001000
000010000
000010001
000001001
000010010
000010011
000001010
000010100
000010101
000001011
000010110
000010111
000001100
000011000
000011001
000001101
000011010
000011011
000001110
000011100
000001111
000010000
000010001
000010010
000010011
000010100
000010101
000010110
000010111
000011000
000011001
000011010
000011011
000011100
10
10
01
10
10
01
10
01
00
01
01
00
01
01
00
01
01
00
01
01
00
01
01
00
01
01
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
150
156.25
162.5
162.5
168.75
175
175
187.5
200
200
212.5
225
225
237.5
250
250
262.5
275
275
287.5
300
300
312.5
325
325
337.5
350
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700 (Max)
October 27, 2004
32
Table 23 – FPGA Pin Assignments for the Synthesizer Interface
Signal Name
Virtex-II Pro Pin #
Comments
Bottom MGT BREFCLK Clock Input (Synthesizer #1)
SYNTH1_PLOAD
AD18
This input is used to load the M and N values into the
synthesizer using the parallel mode configuration along
with the DIP switch settings for M and N.
SYNTH1_RESET
AE24
This input signal resets the synthesizer.
SYNTH1_SCLK
AE22
This clock input is used to load the M and N values into
the synthesizer using serial mode configuration.
SYNTH1_SDATA
AE21
Serial data input to the synthesizer for loading the M and
N values.
SYNTH1_SLOAD
AE20
This input signal is used to load the M and N values into
the synthesizer using the serial mode configuration.
SYNTH1_TEST
AE18
A test clock input can be provided to the synthesizer using
this clock input.
SYNTH1_VCOSEL
AD19
This input signal can be used to bypass the PLL for test
purposes.
SYNTH1_XTALSEL
AE19
This input signal is used to select between the test clock
input and the on-board crystal as clock source to the
synthesizer.
SYNTH1_DOUT
AK21
This output signal is used as the test clock output.
Top MGT BREFCLK Clock Input (Synthesizer #2)
SYNTH2_PLOAD
L19
This input is used to load the M and N values into the
synthesizer using the parallel mode configuration along
with the DIP switch settings for M and N.
SYNTH2_RESET
K24
This input signal resets the synthesizer.
SYNTH2_SCLK
K23
This clock input is used to load the M and N values into
the synthesizer using serial mode configuration.
SYNTH2_SDATA
K21
Serial data input to the synthesizer for loading the M and
N values.
SYNTH2_SLOAD
K20
This input signal is used to load the M and N values into
the synthesizer using the serial mode configuration.
SYNTH2_TEST
K18
A test clock input can be provided to the synthesizer using
this clock input.
SYNTH2_VCOSEL
L18
This input signal can be used to bypass the PLL for test
purposes.
SYNTH2_XTALSEL
K19
This input signal is used to select between the test clock
input and the on-board crystal as clock source to the
synthesizer.
SYNTH2_DOUT
F8
This output signal is used as the test clock output.
LVDS Interface Differential System Clock Input (Synthesizer #3)
SYNTH3_PLOAD
V25
This input is used to load the M and N values into the
synthesizer using the parallel mode configuration along
with the DIP switch settings for M and N.
SYNTH3_RESET
Y33
This input signal resets the synthesizer.
SYNTH3_SCLK
AG34
This clock input is used to load the M and N values into
the synthesizer using serial mode configuration.
SYNTH3_SDATA
AG33
Serial data input to the synthesizer for loading the M and
N values.
SYNTH3_SLOAD
AL34
This input signal is used to load the M and N values into
the synthesizer using the serial mode configuration.
SYNTH3_TEST
AC25
A test clock input can be provided to the synthesizer using
this clock input.
SYNTH3_VCOSEL
V24
This input signal can be used to bypass the PLL for test
purposes.
October 27, 2004
33
SYNTH3_XTALSEL
AL33
SYNTH3_DOUT
AJ22
3.6
This input signal is used to select between the test clock
input and the on-board crystal as clock source to the
synthesizer.
This output signal is used as the test clock output.
Miscellaneous I/O Interface
The FF1152 development board will provide a set of interfaces that are typically used in a
development environment. These interfaces range from a simple LED interface to providing a
network connection via Ethernet. The following sections describe the interfaces provided on the
FF1152 development board.
3.6.1 10/100 Ethernet
ETH_RXD[0:3]
TD+
ETH_RXDV
TD-
ETH_RXER
RD+
ETH_RXC
RD-
RJ45
Connector
(built-in magnetics)
The FF1152 development board will provide a 10/100 Ethernet port for network connection.
ETH_TXD[0:3]
ETH_TXEN
Virtex-II Pro
FPGA
ETH_TXER
ETH_TXC
Broadcom
BCM5221
10/100 PHY
ETH_COL
ETH_CRS
Crystal
20Mhz
ETH_MDC
ETH_RESETn
LEDs
ETH_MDIO
Figure 18 – 10/100 Ethernet Interface
Table 24 – Ethernet Pin Assignments
Signal Name
ETH_TXC
ETH_RXC
ETH_CRS
ETH_RXDV
October 27, 2004
Virtex-II Pro™ Pin #
AG26
AH26
AG18
AH25
34
ETH_RXD[0]
ETH_RXD[1]
ETH_RXD[2]
ETH_RXD[3]
ETH_COL
ETH_RXER
ETH_TXEN
ETH_TXER
ETH_TXD[0]
ETH_TXD[1]
ETH_TXD[2]
ETH_TXD[3]
ETH_MDC
PHY_RESETn
ETH_MDIO
AF25
AF24
AF22
AF21
AG19
AG25
AG22
AH22
AH21
AG21
AH20
AH19
AF20
AF18
AF19
3.6.2 IDE/General-Purpose 40-Pin Header
The FF1152 development board provides a 40-pin header to allow connection of an IDE device
(such as HD, CDROM, etc.) or to be used as a general-purpose header for user access. If not
used as the IDE port, this header can serve as a test port. Being able to connect to a Hard Drive
in a processor-based design can add great value to this platform. A simple header can be used
to provide the IDE interface or a general-purpose interface with 28 user signals as shown below.
IDE_RESETn
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
GND
IDE_DMARQ
IDE_DIOWn
IDE_DIORn
IDE_IORDY
IDE_DMACKn
IRQ
IDE_DA1
IDE_DA0
IDE_CS1FXn
IDE_DASPn
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
40-Pin Header
(IDE Pinout)
20
23
22
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
NC
GND
GND
GND
NC
GND
IDE_IOCS16n
NC
IDE_DA2
IDE_CS3FXn
GND
Figure 19 - 40-Pin User Header With IDE Pinout
October 27, 2004
35
Table 25 – IDE Connector Pin Assignments
Virtex-II Pro™
Pin #
D30
D29
D26
C26
D25
D24
C24
D23
D22
C22
F22
E21
F21
F20
E19
F19
F18
J25
J23
IDE Signal
Name
IDE_RESETn
IDE_DD[7]
IDE_DD[6]
IDE_DD[5]
IDE_DD[4]
IDE_DD[3]
IDE_DD[2]
IDE_DD[1]
IDE_DD[0]
GND
IDE_DMARQ
IDE_DIOWn
IDE_DIORn
IDE_IORDY
IDE_DMACKn
IDE_INTRQ
IDE_DA[1]
IDE_DA[0]
IDE_CS1FXn
IDE_DASPn
IDE Connector Pin #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
IDE Signal
Name
GND
IDE_DD[8]
IDE_DD[9]
IDE_DD[10]
IDE_DD[11]
IDE_DD[12]
IDE_DD[13]
IDE_DD[14]
IDE_DD[15]
NC
GND
GND
GND
NC
GND
IDE_IOCS16n
NC
IDE_DA[2]
IDE_CS3FXn
GND
Virtex-II
Pro™ Pin #
D21
C21
D20
D19
E29
E28
E26
F26
E25
E22
J21
The following figure shows the IDE connection to the Virtex-II Pro FPGA.
DATA{15:0]
A[2:0]
IOWn
IORn
IOCS16n
Virtex-II Pro
FPGA
ALE
IDE
Connector
CS0n
CS1n
IRQ
ACTIVEn
Figure 20 – IDE Interface
October 27, 2004
36
3.6.3 LCD Panel
The FF1152 development board provides an 8-bit interface to a 2x16 LCD panel (MYTECH
MOC-16216B-B). The following table shows the LCD interface signals.
Table 26 – LCD Interface Signals
Signal Name
Description
D7
LCD Data Bit 7
D6
D5
D4
D3
D2
D1
D0
EN
RW
LCD Data Bit 6
LCD Data Bit 5
LCD Data Bit 4
LCD Data Bit 3
LCD Data Bit 2
LCD Data Bit 1
LCD Data Bit 0
LCD Enable Signal
LCD Write Signal (this signal is connected to logic “0” on
the Virtex-II Pro board, enabling write only cycles).
LCD Register Select Signal
RS
Virtex-II Pro™ Pin #
V28
W27
W28
V27
Y28
AG28
AH27
AJ28
AJ27
W24
3.6.4 RS232
The FF1152 development board provides two RS232 ports with RX and TX signals and two-pin
headers for connection to RTS and CTS signals. The following figure shows one of the RS232
interfaces to the Virtex-II Pro FPGA.
o
2
1
RXD
Din1
Dout1
RD
2
3
TD
TXD
Rout1
Virtex-II Pro
FPGA
RS232
Drivers
MAX3223
2
Rin1
3
o
RTS
CTS
RS232
Connector
1
Dout2
Din2
Rout2
Rin2
3
RTS
CTS
2-Pin
Header
Figure 21 – RS232 Interface
October 27, 2004
37
Table 27 – RS232 Signals
Signal Name
RS232_RXD1
RS232_TXD1
RS232_RTS1
RS232_CTS1
RS232_RXD2
RS232_TXD2
RS232_RTS2
RS232_CTS2
Description
RS232 Port1
Received Data, RD
Transmit Data, TD
Request To Send, RTS
Clear To Send, CTS
RS232 Port2
Received Data, RD
Transmit Data, TD
Request To Send, RTS
Clear To Send, CTS
Virtex-II Pro Pin #
AJ19
AK19
AJ20
AJ21
AL14
AM14
AL15
AL16
3.6.5 User DIP and PB Switches
The Virtex-II Pro system board provides four user push button switches as described in the
following table. An active low signal is generated when a given switch is pressed. It should be
noted that there are no pull-up resistors on the push button switch signals. Hence, internal FPGA
pull-up resistors must be used to force a given push button switch signal to a logic “1” when its
associated switch is not pressed.
Table 28 – Push Switch Pin Assignments
Signal Name
PUSH1
PUSH2
PUSH3
PUSH4
Virtex-II Pro
Pin #
G25
H25
G26
H26
Description
SW3
SW4
SW5
SW6
Table 29 – DIP Switch Pin Assignments
Signal Name
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
Virtex-II Pro
Pin #
G18
H19
G19
G20
H21
G21
H22
G22
Description
User Switch Input 8
User Switch Input 7
User Switch Input 6
User Switch Input 5
User Switch Input 4
User Switch Input 3
User Switch Input 2
User Switch Input 1
3.6.6 User LEDs
The Virtex-II Pro system board provides four user LEDs that can be turned “ON” by driving the
LEDx signal to a logic “0”. The following table shows the user LEDs and their associated Virtex-II
Pro FPGA pin assignments.
October 27, 2004
38
Table 30 – LED Pin Assignments
LED Designation
DS18
DS19
DS20
DS21
DS13
DS14
DS15
DS16
3.7
LED #
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
Virtex-II Pro Pin #
E31
E32
F31
F30
E1
E2
E3
E4
Configuration and Debug Ports
Various methods of configuration and debug support are provided on the FF1152 development
board to assist designers during testing and debugging of their applications. The following
sections provide brief descriptions of each of these interfaces.
3.7.1 JTAG Chain
The following figure shows the JTAG chain on the FF1152 development board. The XC9536XV
along with a serial Flash is used to configure the FPGA. The serial Flash programming is
described in the following section.
TDO
TDI
SAM
Connector
JTAG_JP
1
2
3
4
5
6
TDI
TDO
TMS
TCK
TMS
XC9536XV CPLD
TDI
TDO
TMS
TCK
Virtex-II Pro FPGA
TCK
JTAG Port
(PC4)
CPU
JTAG Port
Figure 22 – JTAG Chain
October 27, 2004
39
3.7.2 System ACE Module Connector
The FF1152 development board provides the SAM 50-pin connector on the board for using the
Memec Design System ACE Module (SAM). The Memec Design SAM can be used to configure
the FPGA or to provide bulk Flash to the PowerPC processor.
JTAG Configuration Port
(includes VCC and GND for
stand-alone operation)
JTAG Test Port
(inludes VCC and GND)
The FF1152 development board provides a System ACE interface that can be used to configure
the Virtex-II Pro FPGA. The interface also gives software designers the ability to run real-time
operating systems (RTOS) from removable CompactFlash cards. The Memec Design System
ACE module (DS-KIT-SYSTEMACE) can be used to perform both of these functions. The figure
below shows the System ACE module connected to the header on the Virtex-II Pro board.
CF Connector
SystemACE™
Controller
50-pin Connector
(connects to a 40-pin 0.1" square post header on the main board)
4
JTAG
Configuration Port
28
MPU
Interface
2
Reset &
Clock
10
Power &
Ground
6
Misc
Signals
3.7.2.1 System ACE Controller Clock Input
The following figure shows the clocking scheme for the System ACE controller. When the MPU
port of the System ACE controller is used, the Virtex-II Pro FPGA and the System ACE controller
must use the same clock source. Hence, jumpers are provided on the Virtex-II Pro system board
and the System ACE module to provide the clock input to both devices. Two clocking schemes
are provided to ensure full synchronization of the MPU interface and also allow a variable clock
input to the System ACE controller. The following table shows these two clocking options.
October 27, 2004
40
OSC
Socket
System ACE
Controller
2
4
6
OSC
@ 24MHz
JP25
1
3
5
EN
JP5
System ACE Module
Virtex-II Pro FPGA
Virtex-II Pro System Board
Table 31 – System ACE Clock Source
Clock Source
Jumper Settings
JP25
JP5
Place jumper on
Open
pins 3-5
Place jumpers on
Closed
pins 5-6 and 3-4
System ACE module 24Mhz OSC
Virtex-II Pro system board OSC socket
When this option is used, the OSC must not exceed 33Mhz.
3.7.2.2 System ACE Controller Signal Description
The following table shows the System ACE Module signal assignments to the FPGA I/O pins.
Table 32 - SAM Interface Signals
Virtex-II Pro
Pin #
Note 2
Note 2
Note 2
Note 3
AJ8
AH8
October 27, 2004
System ACE
Signal Name
3.3V
TDO
TMS
TDI
PROGRAMn
GND
OEn
MPA0
SAM Connector Pin #
(JP26)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
System ACE
Signal Name
3.3V
GND
CLOCK
GND
TCK
GND
INITn
WEn
Virtex-II Pro
Pin #
Note 1
Note 2
Note 3
AD8
41
AB8
MPA2
2.5V
MPD00
MPD02
MPD04
MPD06
MPD08
MPD10
MPD12
MPD14
MPA4
MPA6
IRQ
RESETn
DONE
CCLK
GND
V8
AC9
AA9
M10
M9
N8
T9
U8
U10
T11
R10
P10
Note 3
Note 3
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
MPA1
MPA3
2.5V
MPD01
MPD03
MPD05
MPD07
MPD09
MPD11
MPD13
MPD15
MPA5
GND
CEn
BRDY
BITSTREAM
NC
AA8
W8
AB9
J8
L8
N9
P8
T8
U9
U11
T10
P9
N10
Note 3
3.7.3 Serial Flash
This section describes the procedure for programming the Atmel serial flash on the Memec
Design FF1152 development board. This serial flash along with a CPLD is used to configure the
Virtex-II Pro FPGA located on the FF1152 development board on power up. The following figure
shows a high-level block diagram of the serial flash interface to the Virtex-II Pro FPGA.
Master Serial
Interface
SPI Interface
SI
CCLK
SO
DIN
INITn
SCK
DONE
CSn
Virtex-II Pro
FPGA
XC9536XV
CPLD
Atmel
AT45DB321B/
AT45DB161B
Serial Flash
Figure 23 – FF1152 Development Board Configuration Interface
The primary function of the CPLD is to translate the Master Serial interface to the SPI interface of
the serial flash. The XC9536XV CPLD uses the FPGA CCLK clock along with the INITn and
October 27, 2004
42
DONE signals to drive the SPI SI, SCK and CSn signals. The SO output of the serial flash is used
by the CPLD to drive the DIN signal of the FPGA. For more information on detail of the CPLD
design, please refer to the Xilinx XAPP800.
3.7.3.1 JTAG Chain on the FF1152 Development Board
The following figure shows the JTAG chain on the FF1152 development board. As mentioned in
the above section, the CPLD is used for interfacing to the configuration flash and does not
provide any user logic. Hence, this CPLD is programmed by Memec prior to shipping the board.
The programming file for the CPLD is provided in case re-programming of the CPLD becomes
necessary. The CPLD must be programmed prior to performing any operations on the
serial flash such as erasing, programming, reading or verifying.
TDO
TDI
SAM
Connector
JTAG_JP
1
2
3
4
5
6
TDI
TDO
TMS
TCK
TMS
XC9536XV CPLD
TDI
TDO
TMS
TCK
Virtex-II Pro FPGA
TCK
JTAG Port
(PC4)
CPU
JTAG Port
Figure 24 – FF1152 Development Board JTAG Chain
The following table shows jumper settings for the JTAG chain on the FF1152 development board.
Since CPLD is already programmed by Memec prior to shipment, the board is shipped with
jumpers installed on pins 1-2 and 4-5 (FPGA only, in the JTAG chain).
Table 33 – JTAG Chain Jumper Settings
Devices in the JTAG Chain
Jumpers Installed
CPLD and FPGA
Pins 1-2, 3-4 and 5-6
CPLD
Pins 2-3 and 5-6
FPGA
Pins 1-2 and 4-5
October 27, 2004
43
3.7.3.2 Configuration Flash on the FF1152 Development Board
The following figure shows the detail interface between the FPGA and the serial flash. A PC4
cable is used to program the serial flash with the FPGA bitstream. Once the flash is programmed,
the CPLD will read the data from the flash and configure the FPGA over the Master Serial
interface.
XC9536XV
CPLD
Virtex-II Pro FPGA
J1
JP15
TDO
INITn
TMS
TDI
DIN
TCK
Flash
Programming
Header (PC4)
CCLK
M0
M1
M2
Atmel
AT45DB321B/
AT45DB161B
Serial Flash
DONE
SI
SO
VCC
SCK
CSn
WPn
RESETn
Flash Programming/
Normal Mode Jumper
JP40
RDY/BUSYn
Figure 25 – Serial Flash Configuration Interface
3.7.3.3
Procedure for Programming the Serial Flash
1. The Memec Design FF1152 development board is shipped with a self-extracting zip file
called Serial_Flash_Programming. Double-click on this self-extracting zip file to unzip it.
After unzipping this file, a folder called C:\Flash_Utilities is created.
2. In order to program the Flash, Flash programming utilities included in the xapp800 must
be downloaded from the following web site:
http://www.xilinx.com/products/xaw/coolvhdlq.htm
3. Click on the above link to download the xapp800 zip file and unzip it to a temporary
folder on your hard drive. You need to register prior to downloading the xapp800 zip file.
4. Copy xmcsutil.exe and xspi_at.exe files from this temporary folder to the
C:\Flash_Utilities folder. The following table shows the contents of the C:\Flash_Utilities
folder after copying these two executable files.
October 27, 2004
44
Table 34 – Files in the Flash_Utilities Folder
File Name
Description
xmcsutil.exe
A utility that is used to reverse the
bytes in an MCS file. This is needed
by the xspi_at utility.
xspi_at.exe
This utility is used to erase, program
and verify the Atmel serial flash on
the FF1152 development board.
prog_flash.bat
This batch file calls the xmcsutil and
xspi_at utilities to erase, program and
verify the Atmel serial flash on the
FF1152 development board.
spi_cpld.jed
Programming file for the XC9536XV
CPLD
5. Generate a bit file for the FPAG
6. Use iMPACT to generate an MCS file for the bit file generated in the previous step. When
generating the MCS file, select a single platform flash device that will hold the entire
design configuration bits. The following table shows the platform flash devices that must
be used when generating the MCS file in iMPACT for the FF1152 board:
Table 35 – Platform Flash Selection
FPGA Used
Platform Flash Used
P20
XCF08P, XCF16P or XCF32P
P30
XCF16P or XCF32P
P40
XCF16P or XCF32P
P50
XCF32P
7. Un-install JP15 jumpers.
8. Make sure JP40 jumper is un-installed. When JP40 jumper is un-installed, the CPLD
outputs are placed in the tri-state mode allowing the Flash Programming Header to drive
the serial flash SPI bus.
9. Connect a PC4 cable to the Flash Programming Header and power up the FF1152
development board.
10. Copy the MCS file to the C:\Flash_Utilities folder
11. Open a DOS window in the C:\Flash_Utilities folder and enter the following command to
program the serial flash:
C:\ Flash_Utilities > prog_flash design_name.mcs flash_part_number
Where:
design_name.mcs -> The mcs file generated using
the bit file
flash_part_number -> Either AT45DB321B or
AT45DB161B (FF1152 board is populated with one or
the other device).
The prog_flash batch file will erase the flash, program and verify it.
October 27, 2004
45
12. Once the flash programming is completed, open the verify_result.txt file in the
C:\Flash_Utilities folder. If the flash programming was successful, you should see the
following line in the verify_result.txt file:
--> Total byte mismatches [0]
If there is anything other than this line in the verify_result.txt file, the flash programming
was NOT successful. Check the following jumper settings:
a. Make sure JP15 jumpers are un-installed.
b. Make sure JP40 jumper is un-installed.
After checking these jumper settings go back to the step 11 and re-program the flash.
13. Upon completion of the serial flash programming, power down the board and remove the
PC4 cable from the Flash Programming header.
14. Set the mode jumpers to Master Serial (install all mode jumpers on JP15)
15. Install a jumper on JP40.
16. Power up the board and FPGA will configure.
3.7.4 JTAG Port (PC4)
The FF1152 development board provides a JTAG port (PC4 type) connector for configuration of
the FPGA and programming of the on-board ISP PROMs. The following figure shows the pin
assignments for the PC4 header on this development board.
2.5V
PC4
Connector
1
3
5
7
9
11
13
2
4
6
8
10
12
14
TMS
TCK
TDO
TDI
Figure 26 – PC4 JTAG Port Connector
3.7.5 CPU JTAG Port
The Virtex-II Pro development board provides a CPU JTAG connector that can be used to
download code into the Virtex-II Pro integrated PowerPC processor. This JTAG port can also be
used as the processor debug port. The following figure shows the pin assignments for the CPU
JTAG connector on the board.
October 27, 2004
46
CPU JTAG
Connector
TDO
TDI
TCK
TMS
CPUJTAG_HALT
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
pullup
CPUJTAG_TRST
Figure 27 - CPU JTAG Port Connector
Signal Name
TCK
TDI
TMS
TDO
CPUJTAG_TRST
CPUJTAG_HALT
Virtex-II Pro™ Pin #
Y9
W9
Description
CPU JTAG Clock Input
CPU JTAG Data Input
CPU JTAG TMS Input
CPU JTAG Data Output
CPU JTAG Reset Input
CPU HALT Input
3.7.6 CPU Debug Port
The FF1152 development board provides a CPU Debug header for connection of a debug probe
(such as the Wind River visionProbe-II™) to the PowerPC processor.
The Virtex-II Pro development board provides a dedicated CPU Debug connector that can be
used to download code into the Virtex-II Pro integrated PowerPC processor. This JTAG port can
also be used as the processor debug port. The figure below shows the pin assignments for the
CPU Debug connector. The FPGA general-purpose I/O pins are used for this interface.
CPU Debug
Connector
CPU_TDO
CPU_TDI
CPU_TCK
CPU_TMS
CPU_HALT
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
pullup
CPU_TRST
Figure 28 - CPU Debug Port Connector
October 27, 2004
47
Table 36 – CPU Debug Interface Signals
Signal Name
CPU_TCK
CPU_TDI
CPU_TMS
CPU_TDO
CPU_TRST
CPU_HALT
Virtex-II Pro™
Pin #
AA34
AB34
Y34
AC34
AC33
W33
Description
CPU Debug Clock Input
CPU Debug Data Input
CPU Debug TMS Input
CPU Debug Data Output
CPU Debug Reset Input
CPU HALT Input
3.7.7 CPU Trace Port
The FF1152 development board provides a CPU Trace header for connection of a debug probe
(such as the Wind River visionTrace™ or Agilent FPGA Trace Port Analyzer) to the PowerPC
processor.
The processor uses the trace interface when operating in real-time trace-debug mode. Real-time
trace-debug mode supports real-time tracing of the instruction stream executed by the processor.
In this mode, debug events are used to cause external trigger events. An external trace tool uses
the trigger events to control the collection of trace information. The broadcast of trace information
on the trace interface occurs independently of external trigger events (trace information is always
supplied by the processor). Real-time trace-debug does not affect processor performance. The
following figure shows the CPU Trace connector on the Virtex-II Pro development board.
Mictor
Connector
NC
NC
NC
HALT
NC
CPU.TDO
NC
CPU.TCK
CPU.TMS
CPU.TDI
TRST
CPU.HRESET/ATDD15
ATDD14
ATDD13
ATDD12
ATDD11
ATDD10
ATDD9
ATDD8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
NC
NC
TRACE.CLK
NC
NC
Vref
NC
ATDD19
ATDD18
ATDD17
ATDD16
TRACE.TS10/ATDD7
TRACE.TS20/ATDD6
TRACE.TS1E/ATDD5
TRACE.TS2E/ATDD4
TRACE.TS3/ATDD3
TRACE.TS4/ATDD2
TRACE.TS5/ATDD1
TRACE.TS6/ATDD0
Figure 29 – CPU Trace Port Connector
October 27, 2004
48
Table 37 – Trace Port Pin Assignments
Signal Name
TRACE.CLK
TRACE.TS3
TRACE.TS4
TRACE.TS5
TRACE.TS6
TRACE.TS10
TRACE.TS1E
TRACE.TS20
TRACE.TS2E
ATDD10
ATDD11
ATDD12
ATDD13
ATDD14
ATDD16
ATDD17
ATDD18
ATDD19
ATDD8
ATDD9
Virtex-II Pro Pin #
V26
AF31
AF32
AK31
AK32
Y31
AD31
Y32
AD32
Y29
W30
W29
V30
V29
W32
W31
V32
V31
AH30
AH29
Description
Trace Clock
Trace Status
Execution status
3.7.8 Configuration Modes
The following table shows the Virtex-II Pro configuration modes.
Table 38 - FPGA Configuration Mode Jumper Settings
Mode
Master Serial
Master Serial
Slave Serial
Slave Serial
Master SelectMap
Master SelectMap
Slave SelectMap
Slave SelectMap
JTAG
JTAG
3.8
PC Pullup
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
1-2 (M2)
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
Open
Configuration Mode Jumpers
3-4 (M1)
5-6 (M0)
7-8 (HSWAP_EN)
Closed
Closed
Closed
Closed
Closed
Open
Open
Open
Closed
Open
Open
Open
Open
Open
Closed
Open
Open
Open
Open
Closed
Closed
Open
Closed
Open
Closed
Open
Closed
Closed
Open
Open
Supply Voltages
The following figure shows the voltage regulators that are used on Virtex-II Pro development
board to provide various on-board voltage sources. As shown in the following figure, a connector
is used to provide the main 5.0V and 3.3V voltages to the board. The 3.3V voltage source is
provided to all on-board regulators to generate the 1.5V and 2.5V voltages for the digital section
of the board and the 2.5V for the Rocket I/O transceiver section.
October 27, 2004
49
3.3V
2.5V
1.5V
2.5V
2.5V
Regulator
1.5V
Regulator
2.5V Regulator
for the MGTs
2.5V
Alternate
Source
1.5V
Alternate
Source
5.0V
3.3V and 5.0V
Connector
Figure 30 - Voltage Regulators
For the on-board digital voltages (1.5V and 2.5V), if the current provided by the on-board
regulator is not sufficient for some applications, the user can directly drive the voltage source and
bypass the on-board regulators. This is accomplished by removing the jumpers that connect the
3.3V supply to the regulators and connecting external sources to the 1.5V and 2.5V connectors.
Table 39 – Current Provided for each Voltage Source on the Board
Voltage
1.5V
2.5V
3.3V
5.0V
2.5V
3.9
Current (A)
6
6
6
6
3
Comments
FPGA Core voltage
FPGA I/O voltage, P160 supply voltage
FPGA I/O voltage, P160 supply voltage
LCD, P160, and LVDS connector supply voltage
Rocket I/O supply voltage
Bank I/O Voltage
The following table shows the Virtex-II Pro bank I/O voltages on the FF1152 board.
Table 40 – I/O Bank Voltages
Bank #
0
1
2
3
4
5
6
7
October 27, 2004
I/O Voltage
2.5V
3.3V
2.5V
2.5V
3.3V
3.3V
2.5V
2.5V
50
3.10 P160 Expansion Module Signal Assignments
The following tables show the Virtex-II Pro pin assignments to the P160 Expansion Module
connectors (JX1 & JX2) located on the Virtex-II development board.
Table 41 – P160 Connector Pin Assignments
Virtex-II Pro FPGA
Pin #
NC
NC
NC
NC
AD16
AF10
AC10
W11
V11
V10
W10
Y10
AF11
AF13
AF14
AF15
AA10
AB10
AF16
AJ17
October 27, 2004
I/O Connector
Signal Name
TCK
GND
TMS
Vin
TDI
GND
TDO
3.3V
LIOA9
GND
LIOA11
2.5V
LIOA13
GND
LIOA15
Vin
LIOA17
GND
LIOA19
3.3V
LIOA21
GND
LIOA23
2.5V
LIOA25
GND
LIOA27
Vin
LIOA29
GND
LIOA31
3.3V
LIOA33
GND
LIOA35
2.5V
LIOA37
GND
LIOA39
Vin
JX1 Pin #
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10 B10
A11 B11
A12 B12
A13 B13
A14 B14
A15 B15
A16 B16
A17 B17
A18 B18
A19 B19
A20 B20
A21 B21
A22 B22
A23 B23
A24 B24
A25 B25
A26 B26
A27 B27
A28 B28
A29 B29
A30 B30
A31 B31
A32 B32
A33 B33
A34 B34
A35 B35
A36 B36
A37 B37
A38 B38
A39 B39
A40 B40
I/O Connector
Signal Name
FPGA.BITSTREAM
SM.DOUT/BUSY
FPGA.CCLK
DONE
INITn
PROGRAMn
NC
LIOB8
LIOB9
LIOB10
LIOB11
LIOB12
LIOB13
LIOB14
LIOB15
LIOB16
LIOB17
LIOB18
LIOB19
LIOB20
LIOB21
LIOB22
LIOB23
LIOB24
LIOB25
LIOB26
LIOB27
LIOB28
LIOB29
LIOB30
LIOB31
LIOB32
LIOB33
LIOB34
LIOB35
LIOB36
LIOB37
LIOB38
LIOB39
LIOB40
Virtex-II Pro FPGA
Pin #
NC
NC
NC
NC
NC
NC
NC
AF17
AH9
AH10
AG10
AH13
AG13
AH14
AG14
AH15
AH16
AG16
AG17
AK6
AK7
AK8
AK11
AJ11
AK13
AJ13
AK14
AJ14
AJ15
AK16
AJ16
AL5
AM7
AL7
AL8
AM11
AL11
AL12
AM13
AL13
51
Table 42 - P160 Connector Pin Assignments
Virtex-II Pro FPGA
Pin #
D5
D6
D9
C9
D10
D11
C11
D12
D13
C13
D14
C14
D15
D16
H9
G9
H10
G10
H13
G13
H14
G14
G15
H16
G16
G17
J10
J11
J12
J14
J15
J16
E6
AD17
AE17
AE16
AE15
AE14
AE13
AE11
October 27, 2004
I/O Connector
Signal Name
RIOA1
RIOA2
RIOA3
RIOA4
RIOA5
RIOA6
RIOA7
RIOA8
RIOA9
RIOA10
RIOA11
RIOA12
RIOA13
RIOA14
RIOA15
RIOA16
RIOA17
RIOA18
RIOA19
RIOA20
RIOA21
RIOA22
RIOA23
RIOA24
RIOA25
RIOA26
RIOA27
RIOA28
RIOA29
RIOA30
RIOA31
RIOA32
RIOA33
RIOA34
RIOA35
RIOA36
RIOA37
RIOA38
RIOA39
RIOA40
JX2 Pin #
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10 B10
A11 B11
A12 B12
A13 B13
A14 B14
A15 B15
A16 B16
A17 B17
A18 B18
A19 B19
A20 B20
A21 B21
A22 B22
A23 B23
A24 B24
A25 B25
A26 B26
A27 B27
A28 B28
A29 B29
A30 B30
A31 B31
A32 B32
A33 B33
A34 B34
A35 B35
A36 B36
A37 B37
A38 B38
A39 B39
A40 B40
I/O Connector
Signal Name
GND
RIOB2
Vin
RIOB4
GND
RIOB6
3.3V
RIOB8
GND
RIOB10
2.5V
RIOB12
GND
RIOB14
Vin
RIOB16
GND
RIOB18
3.3V
RIOB20
GND
RIOB22
2.5V
RIOB24
GND
RIOB26
Vin
RIOB28
GND
RIOB30
3.3V
RIOB32
GND
RIOB34
2.5V
RIOB36
GND
RIOB38
Vin
RIOB40
Virtex-II Pro FPGA
Pin #
F17
F16
E16
F15
F14
E14
F13
E13
E10
F9
E9
E7
L16
L17
K17
K16
K15
K14
K12
K11
52
4
Revisions
V1.0
Initial release for Rev 1 board
November 24, 2003
V1.1
Corrected ICS DIP Switch Diagram (Fig 18)
November 26, 2003
V1.2
Removed Fig 18 and corrected references to the
P160 module in the GbE section. Also, changed
the part number for the LCD.
April 2, 2004
V1.3
Removed references to the ISP PROMs and included
description for programming the Atmel serial Flash on
the board.
October 27, 2004
October 27, 2004
53