74HC21 Dual 4-input AND gate

74HC21

Dual 4-input AND gate

Rev. 7 — 30 November 2015 Product data sheet

The 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V

CC

.

2. Features and benefits

Low-power dissipation

Complies with JEDEC standard no. 7A

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Specified from

40

C to +85

C and from

40

C to +125

C.

Table 1.

Ordering information

Type number Package

74HC21D

74HC21DB

74HC21PW

Temperature range

40

C to +125

C

40

40

C to +125

C to +125

C

C

Name

SO14

Description plastic small outline package; 14 leads; body width 3.9 mm

SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm

TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm

Version

SOT108-1

SOT337-1

SOT402-1

NXP Semiconductors

74HC21

Dual 4-input AND gate

$

%

&

'

$

%

&

'

<

<

Fig 1.

Functional diagram

DDE

$

%

&

'

$

%

&

'

Fig 2.

Logic symbol

<

<

DDE

Fig 3.

IEC Logic symbol

DDE

$

%

&

'

Fig 4.

Logic diagram

DDE

<

5.1 Pinning

+&

&

'

<

$

%

QF

*1'

DDE

Fig 5.

Pin configuration SOT108-1

QF

%

$

9

&&

'

&

<

74HC21

Product data sheet

+&

$

%

QF

&

'

<

*1'

%

$

<

9

&&

'

&

QF

DDL

Fig 6.

Pin configuration SOT337-1 and SOT402-1

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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5.2 Pin description

Table 2.

Pin description

Symbol

1A, 1B, 1C, 1D n.c.

1Y

GND

2Y

2A, 2B, 2C, 2D

V

CC

Pin

1, 2, 4, 5

3, 11

6

7

8

9, 10, 12, 13

14

Table 3.

Function table

[1]

Input

X

H

X

X nA

L nB

X

L

X

X

H nC

X

X

L

X

H

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

L

H

X

X nD

X

Description data input not connected data output ground (0 V) data output data input supply voltage

74HC21

Dual 4-input AND gate

L

H

L

L

Output nY

L

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V

CC

I

IK

I

OK

I

O

I

CC

I

GND

T stg

P tot

Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation

Conditions

V

I

<

V

O

0.5 V or V

I

> V

<

0.5 V or V

O

0.5 V < V

O

< V

CC

CC

+ 0.5 V

> V

CC

+ 0.5 V

+ 0.5 V

SO14 and (T)SSOP14 packages

[1]

[1]

[2]

Min

0.5

-

-

-

-

50

65

-

Max

+7 V

20 mA

20 mA

25 mA

50 mA

-

+150

500

Unit mA

C mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO14 package: P tot

derates linearly with 8 mW/K above 70

C.

For (T)SSOP14 packages: P tot

derates linearly with 5.5 mW/K above 60

C.

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter supply voltage

Conditions

V

CC

V

I

V

O

 t/

V

T amb input voltage output voltage input transition rise and fall rate ambient temperature

V

V

CC

CC

= 2.0 V

= 4.5 V

V

CC

= 6.0 V

74HC21

Dual 4-input AND gate

-

-

-

40

Min

2.0

0

0

Typ

5.0

-

-

-

1.67

-

-

Max

6.0

V

CC

V

CC

625

139

Unit

V

V

V ns/V ns/V

83 ns/V

+125

C

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25

C

40

C to +85

C

40

C to +125

C Unit

I

I

V

V

V

V

I

IH

IL

OH

OL

CC

C

I

Min Typ Max

HIGH-level input voltage

V

CC

= 2.0 V

V

CC

= 4.5 V

V

CC

= 6.0 V

V

CC

= 2.0 V

1.5

3.15

4.2

1.2

2.4

3.2

-

-

-

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage input leakage current

V

I

= V

CC

or GND;

V

CC

= 6.0 V supply current V

I

= V

CC

or GND; I

O

V

CC

= 6.0 V

= 0 A; input capacitance

I

O

= 4.0 mA; V

CC

= 4.5 V

I

O

= 5.2 mA; V

CC

= 6.0 V

-

-

-

-

-

0.8

V

CC

= 4.5 V

V

CC

= 6.0 V -

-

-

2.1

2.8

V

I

= V

IH

or V

IL

I

O

=

20

A; V

CC

= 2.0 V

I

O

=

20

A; V

CC

= 4.5 V

1.9

4.4

2.0

4.5

I

O

=

20

A; V

CC

= 6.0 V 5.9

6.0

I

O

=

4.0 mA; V

CC

= 4.5 V 3.98

4.32

I

O

=

5.2 mA; V

CC

= 6.0 V 5.48

5.81

V

I

= V

IH

or V

IL

I

O

= 20

A; V

CC

= 2.0 V

I

O

= 20

A; V

CC

= 4.5 V

I

O

= 20

A; V

CC

= 6.0 V -

-

0

0

0

1.35

1.8

-

-

-

-

-

0.1

0.1

0.1

0.15

0.26

0.16

-

-

3.5

0.5

0.26

0.1

2.0

-

Min

1.5

3.15

4.2

1.9

4.4

5.9

3.84

5.34

-

-

-

-

-

-

-

-

-

-

-

Max

-

-

-

0.5

1.35

1.8

-

-

-

-

-

0.1

0.1

0.1

0.33

0.33

20

-

1

Min

1.5

3.15

4.2

-

-

-

-

-

1.9

4.4

5.9

3.7

5.2

-

-

-

-

-

-

Max

-

-

-

0.5

1.35

1.8

-

-

-

-

-

0.1

0.1

0.1

0.4

0.4

-

1

40

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

A

A pF

74HC21

Product data sheet

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Rev. 7 — 30 November 2015

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74HC21

Dual 4-input AND gate

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND = 0 V; test circuit see

Figure 8

.

Symbol Parameter Conditions 25

C

Min Typ Max

40

C to +85

C

40

C to +125

C Unit

Min Max Min Max t t t pd

C

PD propagation delay nA, nB, nC or nD to nY; see

Figure 7

V

CC

= 2.0 V

V

CC

= 4.5 V

V

CC

= 6.0 V

V

CC

= 5.0 V; C

L

= 15 pF transition time nY output; see

Figure 7

power dissipation capacitance

V

CC

= 2.0 V

V

CC

= 4.5 V

V

CC

= 6.0 V

V

I

= GND to V

CC

[1]

[2]

[3]

-

-

-

-

-

-

-

-

[1] t pd

is the same as t

PHL

and t

PLH

.

[2] t t

is the same as t

THL

and t

TLH

.

[3] C

PD is used to determine the dynamic power dissipation (P

D

in

W):

P

D

= C

PD

V

CC

2  f i

N +

(C

L

V

CC

2  f o

) where: f i

= input frequency in MHz; f o

= output frequency in MHz;

C

L

= output load capacitance in pF;

V

CC

= supply voltage in V;

N = number of inputs switching;

(C

L

V

CC

2  f o

) = sum of outputs.

33 110

12 22

10 19

10 -

19 75

7 15

6

15

13

-

-

-

-

-

-

-

-

140

28

24

-

95

19

16

-

-

-

-

-

-

-

-

165

33

28

ns ns ns ns

110 ns

22

19

ns ns pF

74HC21

Product data sheet

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Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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74HC21

Dual 4-input AND gate

11. Waveforms

9

,

Q$Q%Q&

Q'LQSXW

*1'

9

0

9

2+

Q<RXWSXW

9

2/

W

3+/

9

0

9

<

9

;

W

7+/

W

3/+

W

7/+

DDE

Measurement points are given in Table 8 .

V

OL

and V

OH

are typical voltage output levels that occur with the output load.

Fig 7.

Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times

Table 8.

Measurement points

Type Input

74HC21

V

M

0.5V

CC

Output

V

M

0.5V

CC

V

X

0.1V

CC

V

Y

0.9V

CC

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

6 of 14

NXP Semiconductors

74HC21

Dual 4-input AND gate

9

,

QHJDWLYH

SXOVH

*1'

9

0

W

:

9

0

W

I

W

U

W

U

W

I

9

,

SRVLWLYH

SXOVH

*1'

*

9,

9

0

57

W

:

9

&&

'87

92

9

0

&/

DDK

Test data is given in

Table 9

.

Definitions test circuit:

R

T

= termination resistance should be equal to output impedance Z o

of the pulse generator.

C

L

= load capacitance including jig and probe capacitance.

Fig 8.

Test circuit for measuring switching times

Table 9.

Test data

Type

74HC21

Input

V

I

V

CC t r

, t f

6.0 ns

Load

C

L

15 pF, 50 pF

Test t

PLH

, t

PHL

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

7 of 14

NXP Semiconductors

12. Package outline

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74HC21

Dual 4-input AND gate

627

'

F

(

+

(

$

;

Y 0 $

=

\

SLQLQGH[

H

E

S

Z 0

$

$

/

S

/

GHWDLO;

4

$ $ ș

PP

VFDOH

',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV

81,7

$

PD[

$ $ $ E

S

F ' ( H +

(

PP

LQFKHV

/ /

S

4

1RWH

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287/,1(

9(56,21

627

,(&

(

5()(5(1&(6

-('(& -(,7$

06

Y Z

(8523($1

352-(&7,21

\ = ș

,668('$7(

R

R

Fig 9.

Package outline SOT108-1 (SO14)

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

8 of 14

NXP Semiconductors

6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP

74HC21

Dual 4-input AND gate

627

'

F

(

+

(

$

;

Y

0 $

=

\

SLQLQGH[

$

$

/

/

S

GHWDLO;

4

$

$ ș

H

E

S

Z 0

PP

VFDOH

',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV

81,7

$

PD[

$ $ $ E

S

F

PP

' ( H +

(

/ /

S

4

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287/,1(

9(56,21

627

,(&

5()(5(1&(6

-('(& -(,7$

02

Y Z

(8523($1

352-(&7,21

\ = ș

R

R

,668('$7(

Fig 10. Package outline SOT337-1 (SSOP14)

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

9 of 14

NXP Semiconductors

76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP

74HC21

Dual 4-input AND gate

627

'

F

(

+

(

$

;

Y 0 $

\

=

SLQLQGH[

H

E

S

Z 0

$

$

/

/

S

GHWDLO;

4

$

$ ș

PP

VFDOH

',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV

81,7

$

PD[

$ $ $ E

S

F

PP

' ( H

1RWHV

3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG

3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG

287/,1(

9(56,21

,(&

5()(5(1&(6

-('(& -(,7$

627 02

+

(

/ /

S

4 Y Z

(8523($1

352-(&7,21

\ = ș

R

R

,668('$7(

Fig 11. Package outline SOT402-1 (TSSOP14)

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

10 of 14

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74HC21

Dual 4-input AND gate

13. Abbreviations

Table 10.

Abbreviations

Acronym

CMOS

Description

Complementary Metal Oxide Semiconductor

DUT

ESD

HBM

MM

TTL

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

Transistor-Transistor Logic

14. Revision history

Table 11.

Revision history

Document ID

74HC21 v.7

Modifications:

74HC21 v.6

Release date Data sheet status Change notice

20151130 Product data sheet -

Type numbers 74HC21N (SOT27-1) removed.

20130208 Product data sheet -

Supersedes

74HC21 v.6

74HC21 v.5

Modifications:

74HC21 v.5

Section 2 : Typo corrected in the specified temperature range.

20090507 Product data sheet 74HC21 v.4

Modifications:

74HC21 v.4

Modifications:

74HC21 v.3

Table 1 : Type number 74HCT21PW changed to 74HC21PW.

20090407 Product data sheet 74HC21 v.3

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.

Added type number 74HC21PW (TSSOP14 package).

20041112

74HC_HCT21_CNV v.2

19970828

Product data sheet

Product specification -

74HC_HCT21_CNV v.2

74HC_HCT21 v.1

74HC_HCT21 v.1

19901201 Product specification -

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

11 of 14

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74HC21

Dual 4-input AND gate

15. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

74HC21

Product data sheet

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

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74HC21

Dual 4-input AND gate

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

16. Contact information

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC21

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 30 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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NXP Semiconductors

17. Contents

7

8

9

10

11

12

13

14

15

15.1

15.2

15.3

15.4

16

17

1

2

3

4

5

5.1

5.2

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

Pinning information . . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics . . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11

Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Contact information. . . . . . . . . . . . . . . . . . . . . 13

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

74HC21

Dual 4-input AND gate

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2015.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 November 2015

Document identifier: 74HC21