Page 1 of 25
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
Q 1. a) Attempt any THREE of the following:
i.
Ans:
12
List the addressing modes of 8051. Also give example of each mode.
1. Immediate addressing mode: e.g
MOV A, #n - Copy immediate data byte n to register A.
MOV DPTR, #nn - Copy the immediate 16bit number nn to the DPTR
register.
2. Register Addressing mode: e.g
MOV A, R0 - Copy the data from register R0 to Register A.
MOV R5, #A – Copy the register A to register R5.
3. Direct addressing mode: e.g
MOV Rr, Add- Copy data from direct address Add to register Rr.
MOV Add1, Add2 – copy data from direct address Add2 to direct address Add1.
4. Indirect Addressing Mode: e.g MOV A, @R0 - copy the content of Address in R0 to the
register A.
MOV @R1, #35H- copy the number 35 to address in R1.
-----------------------------4 mark for relevant example and description above
ii.
Ans:-
Draw Port “3” structure of 8051 with neat label. Also list any two alternate function of port3.
Page 2 of 25
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SUMMER – 12 EXAMINATIONS
Model Answer
Sample pin function :
P3.0 (RXD) It is the receive data pin for serial port in UART mode.
P3.1 (TXD) It is the transmit data pin for serial port in UART mode. It works as the clock o/p in
the shift register mode.
----------------------2 mark for correct diagram and 2 for relevant pin and function description
iii.
List parallel bus device protocols and describe any one.
Ans:-Parallel Bus device protocols
ISA
PCI
PCI-X
ARM Bus
PCI Bus
-----------------------------1 mark for any 4 correct names
The PCI Local Bus is a high performance bus for interconnecting chips, expansion
boards, and processor/memory subsystems
The maximum theoretical transfer rate of the base configuration is 132 Mbytes/sec.
Extensions to the base PCI specification can boost this by a factor of four to 528
Mbytes/sec. The PCI-X enhancements extend potential bandwidth to over 4 gigabytes
per second.
Any device on the bus can be a bus master and initiate transactions.
The transfer protocol is optimized around transferring blocks of data.
PCI is officially processor-independent.
It uses little-endian byte ordering.
PCI implements Plug-and-Play configurability. Every device in a system is automatically
configured each time the system is turned on.
The configuration protocol supports up to 256 devices in a system.
The electrical specifications emphasize low power use including support for both 3.3
and 5 volt signalling environments.
-----------------------------3 mark for any three relevant points from above
iv.
Give any four application of embedded system with their example.
Ans:
Telecommunication system: employ numerous embedded systems from telephone
switches for the network to mobile phones at the end user.
Computer networking: uses dedicated routers and network bridges to route data.
Consumer electronics: include personal digital assistant (PDAs), mp3 players, mobile
phones, videogames, digital cameras, GPS receivers and printers.
Page 3 of 25
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SUMMER – 12 EXAMINATIONS
Model Answer
Household application: such as microwave ovens. Washing machines, dish washers are
including embedded systems tp provide flexibility, efficiency and features.
Advanced HVAC: system used networked thermostats to more accurately and efficiently
control temp that can change by time of the day and seasons.
Transportation system: from flight to auto mobiles increasingly use embedded system
new airplanes contain advanced avionics such as inertial guidance system and GPS
receivers that also have considerable safety requirements.
Various electric motors: brushless DC motors, including motors and DC motors- are using
electric/electronics motor controllers.
Medical equipment: is continuing to advance with more embedded system for vital signs
monitoring, electronics stethoscopes for amplifying sounds, and various medical imaging
(PET, SPECT, CT, and MRI) for the non invasive internal inspections.
-----------------------------4 mark for any 4 relevant example and description above
Q1 b) Attempt any one of the following:
i.
Draw and describe internal memory organization of 8051µc.
6
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MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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SUMMER – 12 EXAMINATIONS
Model Answer
The 8051 has 128 byte of internal memory which is organize in three parts
Thirty two bytes from address 00h to 1Fh are 32 working register organize as four banks of
eight register each.
The four register banks are numbered 0 to 3 and are made up of 8 registers r0 to r7.
Next memory block in the range 20 to 2F is bit addressable means that each bit is being has its
own address from 00 to 7F.
A general purpose RAM area is above the bit are 30 to 7F addressable as byte.
SFR registers exist in the address range of 80h through FFH.
------------------6 mark for relevant diagram and description above
ii) Divide the data in RAM location 13H by the data in RAM location 14H, then restore the original
data in 13H by multiplying the answer by the data in 14H. Use assembly language for 8051
microcontroller.
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Model Answer
Ans:- org 0000
mov R0,#13h
mov R1,#14h
mov a,@r1
mov b,@r0
div ab
mul ab
mov @r0,a
end
;initialize pointer
; initialize pointer
; move data in 13h to accumulator
; move data in 14h to accumulator
; Divide data in 13h by data in 14h
;multiply answer by data in 14h
;replace data in 13h with the answer
-----------------------------6 mark for correct assembly / c language program (The word RESTORE
in question should be considered as REPLACE as shown in above program)
Q2 Attempt any FOUR of the following:
16
a) Give an overview of 8051 family.
Ans: Overview of 8051 family
In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051. This
microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port,
and four ports (each 8-bits wide) all on a single chip. Intel refers 8051 family of devices as
MCS-51. This family is characterised by block diagram given below.
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Model Answer
There are two other members in the 8051 family of microcontrollers. They are the 8052 and
the 8031
The UV-EPROM version of the 8051 is the 8751. The flash ROM version is marketed by many
companies including Atmel Corp. and Dallas Semiconductor. The Atmel Flash 8051 is called
AT89C51, while Dallas Semiconductor calls theirs DS89C4xO (DS89C420/430/440). The NVRAM version of the 8051 made by Dallas Semiconductor is called DS5000.
There are also OTP (one-time-programmable) versions of the 8051 available from different
sources. Philips family of 8051 microcontroller include features such as A-to-D converters, Dto-A converters, extended I/O, and both OTP and flash.
-----------------------------4 mark for relevant description above
Q 2 b) Write “C” or assembly language program for 8051 to transfer letter “M” serially at 4800 baud
rate.
Ans:
C Program
#include<reg51.h>
void init_uart()
{
SCON = 0x50;
TMOD |= 0x20;
TH1 = 0xFA;
TR1 = 1;
}
void tx()
{
while(!TI);
SBUF=’M’;
TI=0;
}
void main()
{
init_uart();
tx();
}//end of main...
// initilazation of uart
// timer 1,mode 2(auto reload)
// transmission to uart
-----------------------------4 mark for correct c language /assembly language program (as given below)
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Model Answer
Subject code: 12262
Assembly Program:
MOV TMOD, #20H
MOV TH1, #FA
MOV SCON, #50H
SETB TR1
CLR TI
MOV SBUF, #”M”
HERE: JNB TI, HERE
END
; timer 1, mode 2(auto reload)
; 4800 baud rate
; 8-bit, 1 stop, REN enabled
; start timer 1
; clear TI
; letter “M” to transfer
; wait for the last bit
Q 2 c) Describe the features if ISA.
Ans:- Features of ISA
Original ISA was 8 bit wide and ran at 4.77 MHz Later bus width was doubled to 16 bita and speed was
increased to 8 MHz
8 bit ISA has 20 address lines and 16 bit ISA bus has 24 bit addressing.
Two CPU cycles are used are used for every read and write
ISA provides Bus Master support.
Bandwidth of 8 bit ISA is between 0.6 MB/s to 2.38 MB/s
Power lines included -5V and +/-12 V .
------------------------- 4 Mark for any 4 correct points
Q2 d) What do you mean by system on chip?
Ans:- System on Chip
A system on chip is an integrated circuit (IC) that integrates all components of a computer or
other electronic system into a single chip.
It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a
single chip substrate.
A typical SoC consists of:
o A microcontroller, microprocessor or DSP core(s).
o Memory blocks including a selection of ROM, RAM, EEPROM and flash memory.
o Timing sources including oscillators and phase-locked loops.
o Peripherals including counter-timers, real-time timers and power-on reset generators.
o External interfaces including industry standards such as USB, FireWire, Ethernet,
USART, SPI.
o Analog interfaces including ADCs and DACs.
o Voltage regulators and power management circuits.
An SoC consists of both the hardware described above, and the software that controls the
microcontroller, microprocessor or DSP cores, peripherals and interfaces.
SoCs can be fabricated by several technologies, including:
o Full custom
o Standard cell
o FPGA
------------------------- 4 Mark for any 4 correct points
Page 8 of 25
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Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
Q2 e) Draw the Structural Units available in Processor
Ans:- Structural Units available in Processor
------------------------- 4 Mark for diagram (any relevant diagram can be considered)
Q2 f) What do you meant by DMA? Describe the DMA process.
Ans: DMA
A DMA Chip is a special processor that copies data from one memory (or I/O) device to another (or
I/O) device without involving CPU. There are some clock cycles that the CPU does not need the buses.
DMA can use these bus cycles to transfer data.
The peripheral to memory DMA operates according to the following steps:
1. Microprocessor writes to DMA controller and peripheral device to request particular DMA
operation.
2. When peripheral device is ready, it sends a DMA request signal to DMA controller.
3. DMA controller requests CPU for buses (Hold Request).
4. CPU gives the buses to DMA (Hold Ack) and disconnects itself from the buses.
5. DMA controller gives DMA Ack signal back to peripheral device to signal the start of DMA.
6. DMA sends read control signal to peripheral device and puts the destination address and read
signal on address and control buses for memory.
7. Data transfers from peripheral to memory directly.
8. As each byte transferred, the destination address is incremented by 1.
Page 9 of 25
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SUMMER – 12 EXAMINATIONS
Model Answer
9. If the value in the byte counter is not equal to the block size, go to step 6; else, DMA gives the
buses back to CPU (withdraws Hold Request).
------------------------ 1 mark for DMA meaning and 3 Mark for description
Q 3 Attempt any FOUR of the following:
16
a) Describe any four bit handling instructions of 8051
Ans: Boolean Variable Manipulation Instructions
The MCS-51 device family comprises of a complete Boolean processor i.e. a single bit
processor. All the port lines are bit addressable and each line can be accordingly programmed
as a single bit port with the Boolean Variable Manipulation instructions discussed below. .
There are total 17 instructions in this group.
Mnemonic
Function
CLR C
Clear Carry
1
12
CLR C
CLR bit
Clear direct bit
2
12
CLR P2.7
SETB C
Set Carry
1
12
SETB C
SETB bit
Set direct bit
2
12
SETB P1.5
CPL C
Complement Carry
1
12
CPL C
2
12
CPL P2.4
2
24
ANL C, P2.2
2
24
ANL C, / P2.2
2
24
ORL C, P1.3
CPL bit
ANL C, bit
ANL C , /bit
ORL C, bit
Complement
Byte
direct
bit
AND direct bit to
Carry
AND complement of
direct bit to Carry
OR direct bit to carry
Oscillator Period
Example
Page 10 of 25
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Model Answer
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ORL C, /bit
MOV C, bit
MOV bit, C
OR complement of
direct bit to Carry
Move direct bit to
Carry
Move carry to direct
bit
2
24
ORL C, P3.2
2
12
MOV C, P1.1
2
24
MOV P1.1, C
JC rel
Jump if Carry is set
2
24
JC LABLE1
JNC rel
Jump if Carry not set
2
24
JNC LABLE2
3
24
JB 99,LOOP
JB bit, rel
JNB bit, rel
JBC bit, rel
Jump if Carry bit is
set
Jump is direct bit is
not set
Jump if direct bit is
set & clear bit
JNB P1.4,HERE
3
24
JBCACC.7,NEXT
3
24
rel : signed 2’s complement offset byte (Range – 128 to+ 127 bytes relative to the first
byte of the following instruction.)
------------------------- 4 Mark for any four instructions with relevant description
b) Draw the format of SCON and describe its bits functionality.
Ans: - Serial Port Control (SCON) Register
SM0 - Serial port mode bit 0 is used for serial port mode selection.
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Model Answer
SM1 - Serial port mode bit 1.
SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. When
set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It
should be cleared in mode 0.
REN - Reception Enable bit enables serial reception when set. When cleared, serial reception
is disabled.
TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of
transmitting the 9th bit in modes 2 and 3. It is set to transmit logic 1 in the 9th bit.
RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit
received is logic 0. Set by hardware if 9th bit received is logic 1.
TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent.
It's a signal to the processor that the line is available for new bytes transmit. It must be
cleared from within the software.
RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte is
received and should be read quickly prior to being replaced by a new data. This bit is also
cleared from within the software.
------------------------- 4 Mark for above correct points
c) How many timer/counters are available in 8051? When they are used? Write its intialization
instruction if any.
Ans:- Available Timer in 8051 are
Timer 0 (16 bit) & Timer 1 (16 bit)
They are used during timer and counter operations.
Timer is used to calculate delay and counter is used to count the occurrence of events
To initialized timer the count is loaded in the timers lower and upper register by
instruction.
MOV THX,# (count)H
MOV THL, # (count) H
------------------------- 4 Mark for above correct points
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Model Answer
Subject code: 12262
d) Describe the context switching mechanism with suitable diagram
Ans:- Context switching
Each task has its own context, which is the state of the CPU registers required each time it
is scheduled to run. A context switch occurs when the scheduler switches from one task to
another.
Every time a new task is created, the kernel also creates and maintains an associated task
control block (TCB). TCBs are system data structures that the kernel uses to maintain taskspecific information. TCBs contain everything a kernel needs to know about a particular
task.
As shown in above figure when the kernel’s scheduler determines that it needs to stop
running task 1 and start running task 2, it takes the following steps:
1. The kernel saves task 1’s context information in its TCB.
2. It loads task 2’s context information from its TCB, which becomes the
current thread of execution.
3. The context of task 1 is frozen while task 2 executes, but if the scheduler
needs to run task 1 again, task 1 continues from where it left off just
before the context switch.
------------------------- 4 Mark for any four correct points with relevant diagram
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Model Answer
e) What do you mean by task synchronization and mutual exclusion.
Ans: Task synchronization
Tasks synchronize and communicate amongst themselves by using intertask
primitives, which are kernel objects that facilitate synchronization and communication
between two or more threads of execution.
Examples of such objects include semaphores, message queues, signals, and pipes,
as well as other types of objects.
Tasks, along with task-management services, allow developers to design applications
for concurrency to meet multiple time constraints and to address various design
problems inherent to real-time embedded applications.
------------------------- 2 Mark for relevant description
Mutual Exclusion (Mutex) Semaphores
A mutual exclusion (mutex) semaphore is a special binary semaphore that
supports ownership, recursive access, task deletion safety, and one or more
protocols for avoiding problems inherent to mutual exclusion.
Figure illustrates the state diagram of a mutex.
As opposed to the available and unavailable states in binary and counting
semaphores, the states of a mutex are unlocked or locked (0 or 1, respectively).
Page 14 of 25
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Model Answer
A mutex is initially created in the unlocked state, in which it can be acquired by
a task. After being acquired, the mutex moves to the locked state.
Conversely, when the task releases the mutex, the mutex returns to the
unlocked state. Note that some kernels might use the terms lock and unlock for
a mutex instead of acquire and release.
Depending on the implementation, a mutex can support additional features not
found in binary or counting semaphores. These key differentiating features
include ownership, recursive locking, task deletion safety, and priority inversion
avoidance protocols.
------------------------- 2 Mark for relevant description
Q4 a) Attempt any THREE of the following:
i.
12
Draw PSW of 8051. State the function of each bit.
Function of the status bits of PSW:PSW 0: Parity Flag (P)
P = 0 Indicates even parity i.e. even number of ‘1’ in accumulator.
P = 1 Indicates odd parity i.e. odd number of ‘1’s in accumulator.
PSW 1: Reserved for future use. It is the undefined bit.
PSW 2: Overflow flag (OV) This flag is used to detect the errors in the signed arithmetic
operations.
OV=1 When there is carry generated out of bit 6, but not out of bit 7 or When there is carry
generated out of bit 7, but not out of bit 6, after an arithmetic operation (like addition,
subtraction, multiplication or division)
OV= 0 When there is carry both from D6 to D7 & from D7 out, after an arithmetic operation.
PSW4& PSW3:RS1 & RS0 (respectively) are the Register Bank Select bits. These bits are used
to select one of the four register banks of 8051 microcontroller. The bank section
combinations are as given below
RS1(PSW.4)
RSO(PSW.3)
Register Bank
Address
0
0
0
00H – 07H
0
1
1
0
1
2
1
1
3
08H – 0FH
10H -17H
18H – 1FH
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PSW.5: User defined flag (F0): This status bit available to the user and can be set or cleared by
software.
PSW.6: Auxiliary Carry (AC) This flag is used during BCD arithmetic operation
AC=1 If there is carry from D3 to D4 bit during ADD or SUB operation.
AC=0 If there is no carry from D3 to D4 bit during ADD or SUB operation.
PSW.7: Carry Flag (CY)
CY=1 When there is carry out of seventh bit of result, during addition and subtraction
operation.
CY =0 When there is no carry out of seventh bit of result, during addition and subtraction
operation.
------------------------- 4 Mark for correct format + description
ii.
Enlist the Processors available in the embedded System.
Processors available in Embedded Systems
------------------------- 4 Mark for any 4 correct points
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Model Answer
Subject code: 12262
iii.
State the Various types of memories available in embedded system. Also state the
example of each.
Different types of memories in embedded system
Internal RAM of 256 or 512 bytes in a microcontroller for registers, temporary data
and stack.
Internal ROM/PROM/E2PROM for about 4 kB to 64 kB of program (in the case of
micro controllers).
External RAM for the, temporary data and stack (in most systems) or internal caches
(in the case of certain microprocessors).
Internal flash (in many systems the results of processing can be saved in non-volatile
memory: for example, system status periodically and images, songs, or speeches after
suitable format compression).
Memory stick (or card): video, images, songs, or speeches and large storage in digital
camera and mobile systems.
External ROM or PROM for embedding software (in almost all systems other than
microcontroller based systems).
RAM memory buffers at ports.
Caches (in pipelined and superscalar microprocessors).
------------------------- 4 Mark for any 4 correct points
iv.
Enlist the scheduling algorithm and explain any one.
Scheduling Algorithms
preemptive priority-based scheduling
round-robin scheduling
Earliest Deadline First Scheduling
Rate Monotonic
Preemptive Priority-Based Scheduling
With this type of scheduling, the task that gets to run at any point is the task with
the highest priority among all other tasks ready to run in the system.
With a preemptive priority-based scheduler, each task has a priority, and the
highest-priority task runs first.
If a task with a priority higher than the current task becomes ready to run, the
kernel immediately saves the current task’s context in its TCB and switches to the
higher-priority task.
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Model Answer
As shown in following figure task 1 is preempted by higher-priority task 2, which is
then preempted by task 3. When task 3 completes, task 2 resumes; likewise, when
task 2 completes, task 1 resumes.
Advantage:
Once the priorities are set properly, we can rest assured that only the
important tasks are handled first.
Disadvantage:
It is possible that one or more of the lower priority tasks do not get to execute
at all. So, to avoid this, a proper analysis must be done at design phase.
--------- 1 Mark for enlisting algorithm and 3 Mark for any 3 correct points from description above
a) Attempt any ONE of the following
i.
6
Draw “DB-9” RS232 Connector and describe any four signal.
DB-9 connector
DTR: Computer tells the DCE that it is ready to communicate. Raised by DTE when powered
on. In auto-answer mode raised only when RI arrives from DCE.
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Model Answer
RTS: Computer asks the modem if it can send information. Raised by DTE when it wishes to
send. Expects CTS from DCE.
TxD:Computer sends information to the DCE.
RxD:Computer receives information sent from the DCE.
------------------------- 4 Mark for correct pin out and 2 mark for any 4 correct signals
ii.
Describe the software tools for designing an embedded system.
Software tools for designing Embedded Systems
Editors
Software Code for a microcontroller is written in a programming language of choice
(often Assembler or C).This source code is written with a standard ASCII text editor and
saved as an ASCII text file.
Assemblers
Assemblers translate assembly instructions to binary machine instructions.
Cross-Compilers
Compilers translate structured high level language programs into machine (or
assembly) programs. A cross-compiler executes on one processor (our
development processor), but generates code for a different processor (our target
processor). Cross-compilers are extremely common in embedded system
development.
Linkers
Linkers link code modules saved in different files together into a single final
program. At the same time they take care of a chip's memory allocation by
assigning each instruction to a microcontroller memory addresses in such a way
that different modules do not overlap.
Debuggers
A debugger is a piece of software running on the PC, which has to be tightly
integrated with the emulator that you use to validate your code
Simulators
Simulators try to model the behaviour of the complete microcontroller in software.
Some simulators go even a step further and include the whole system (simulation
of peripherals outside of the microcontroller).
Emulators
An emulator is a piece of hardware that ideally behaves exactly like the real
microcontroller chip with all its integrated functionality. It is the most powerful
debugging tool of all.
------------------------- 6 Mark for any 4 correct points
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Model Answer
Q 5 Attempt any FOUR of the following:
a) Draw the architecture of 8051
Architecture of 8051
------------------------- 4 Mark for the correct diagram
16
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Model Answer
b) Enlist the various interrupts of the 8051 with their priorities, vector locations and
cause of interrupts.
Interrupts
Interrupt
Vector address
Priority
Cause of Interrupt
External interrupt 0
0003h
1 Highest
External Event on Pin 3.1
Timer/counter 0
External interrupt 1
Timer/counter 1
Serial port
000Bh
0013h
001Bh
0023h
2
3
4
5 Lowest
Timer 0 overflow
External Event on Pin 3.2
Timer 1 Overflow
When valid last bit is
transmitted or received
------------------------- 4 Mark for correct details and description
b) Compare serial and parallel communication.
Comparison
Lines required
Space required
Transmission Line
Length
Speed
Cost
Issues
Serial Communication
Data is sent and received, one
bit at a time over one line.
Requires fewer interconnecting
cables and hence occupies less
space.
Data can be transmitted over a
short or long distance
Faster
Less
No cross talk or clock skew
Parallel Communication
A parallel port sends and
receives data bits at a time
over separate wires or lines
Requires more interconnecting
cables and hence occupies
more space
Data can be transmitted over a
short distance only
Slower
More
Clock Skew, Cross talk present
------------------------- 4 Mark for any 4 correct points
c) What do you mean by Harvard architecture? Describe process memory interface in it.
Harvard Architecture: It is a type of processor architecture that uses a separate memory space
for data and program.
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Model Answer
Subject code: 12262
It has independent address and databases for two memories. Hence, there is no need to have
separate time division multiplexing (sharing) of address and data buses.
It has separate instructions and control signals for data transfer from these two memories.
The size of data and address bus can vary. Thus the optimal use of bus width is possible, which
allows fast execution of the instruction.
-------------------------1 Mark for diagram and 3 Mark for any 3 correct points
d) Describe the specifications of RTOS.
Specifications of RTOS
Reliability,
Predictability,
Performance,
Compactness
Scalability.
 Reliability
Embedded systems must be reliable. Depending on the application, the system might
need to operate for long periods without human intervention.
Page 22 of 25
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2005 Certified)
Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
A common way that developers categorize highly reliable systems is by quantifying their
downtime per year, as shown in following table. The percentages under the 'Number of 9s'
column indicate the percent of the total time that a system must be available.
Categorizing highly available systems by allowable downtime.1
Number of 9s
Downtime per year
Typical application
3 Nines (99.9%)
~9 hours
Desktop
4 Nines (99.99%)
~1 hour
Enterprise Server
5 Nines (99.999%)
~5 minutes
Carrier-Class Server
6 Nines (99.9999%)
~31 seconds
Carrier Switch Equipment
 Predictability
The RTOS used in this case needs to be predictable to a certain degree. The term
deterministic describes RTOSes with predictable behavior, in which the completion of
operating system calls occurs within known timeframes.
 Performance
This requirement dictates that an embedded system must perform fast enough to fulfill its
timing requirements.
Typically, the processor's performance is expressed in million instructions per second
(MIPS).
Throughput also measures the overall performance of a system, with hardware and
software combined.
One definition of throughput is the rate at which a system can generate output based on
the inputs coming in.
 Compactness
In embedded systems, where hardware real estate is limited due to size and costs, the
RTOS clearly must be small and efficient. In these cases, the RTOS memory footprint can
be an important factor.
 Scalability
Because RTOSes can be used in a wide variety of embedded systems, they must be able to
scale up or down to meet application-specific requirements.
Depending on how much functionality is required, an RTOS should be capable of adding or
deleting modular components, including file systems and protocol stacks.
------------------------- 4 Mark for any 4 correct points
Page 23 of 25
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2005 Certified)
Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
e) Define the term starvation and deadlock with respect to multiple process.
Starvation and Deadlock
Starvation
CPU starvation occurs when higher priority tasks use all of the CPU execution time and
lower priority tasks do not get to run.
The possibility of blocked states is extremely important in real-time systems because
without blocked states, lower priority tasks could not run. If higher priority tasks are not
designed to block, CPU starvation can result.
Deadlock
Deadlock is the situation in which multiple concurrent threads of execution are blocked
permanently because of resource requirements that can never be satisfied.
A typical real-time system has multiple types of resources and multiple concurrent threads
of execution contending for these resources. Each thread of execution can acquire
multiple resources of various types throughout its lifetime.
Potential for deadlock exist in a system in which the underlying RTOS permits resource
sharing among multiple threads of execution. deadlock occurs when the following four
conditions are present:
------------------------- 2Mark each for any 2 correct points relevant to the operation
Q 6 Attempt any FOUR of the following:
16
a) State the functions of pins VPP, PSEN, PROG, ALE
Functions of pins are as follows
VPP: In EPROM devices this pin is used to receive supply voltage necessary for programming
the internal EPROM.
PSEN Program Store Enable is the read strobe to external Program Memory.
PROG: This pin is used as a program pulse input (PROG) during EPROM programming.
ALE: Address Latch Enable output pulse is used for latching the low byte of the address during
accesses to external memory
------------------------- 4 Mark for correct function of each pin
Page 24 of 25
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2005 Certified)
Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
b) Write assembly on “C” language program to generate a square wave of 50 Hz frequency on
pin P 1.2. Use interrupts for timer. Assume crystal frequency 11.0592 MHz.
C Program to generate a square wave of 50 Hz frequency on pin P1.2
#include <reg51.h>
sbit WAVE =P1^2;
void timer0() interrupt 1 {
WAVE=~WAVE; //toggle pin
TL0=0x00;
TH0=0xDC;
}
void main() {
unsigned char x;
TMOD=0x01;
TL0=0x00;
TH0=0xDC;
IE=0x82; //enable interrupts
TR0=1; //start timer 0
while (1); //wait until interrupted
------------------------- 4 Mark for correct logic program ( Correct assembly language program can
also be considered for assessment , sample program is given below )
Assembly program to generate a square wave of 50 Hz frequency on pin P1.2
ORG 0
LJMP MAIN
ORG 000BH ;ISR for Timer 0
CPL P1.2
MOV TL0,#00
MOV TH0,#0DCH
RETI
ORG 30H
;--------main program for initialization
MAIN:MOV TM0D,#00000001B ;Timer 0, Mode 1
MOV TL0,#00
MOV TH0,#0DCH
MOV IE,#82H ;enable Timer 0 interrupt
SETB TR0
HERE:SJMP HERE
END
Page 25 of 25
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2005 Certified)
Subject code: 12262
SUMMER – 12 EXAMINATIONS
Model Answer
c) What do you meant by virtual device driver?
Virtual device driver
An embedded system is designed to control multiple physical and virtual devices like
file, pipe, socket, RAM Disk etc.
Besides the physical devices of a system, drivers are also used in embedded system for
virtual devices called virtual device drivers.
Virtual device drivers also have functions for device open, read, write and close. Device
configuring is equivalent to creating a file. Device configuration on interrupt is
equivalent to opening a file. Device resetting is equivalent to closing a file. Device
detaching is equivalent to freeing a memory space allotted to a file data.
Example virtual device driver is given below
A physical device transceiver is equivalent to a virtual device called loop back
device . It stores allocated memory blocks using a block device driver and
returns the data back from the memory.
------------------------- 4 Mark for any 4 correct points
d) Describe various operating system Functionality in RTOS.
Operating System Functionality in RTOS
Process management
It is nothing but execution of quasi-parallel tasks on a processor using processes or
threads (lightweight process) by maintaining process states, process queuing,
preemption (fast context switching) and quick interrupt handling
CPU scheduling
It guarantees deadlines, minimizing process waiting time, fairness in granting
resources such as computing power
Process synchronization
It is done using semaphores, mutual exclusion etc
Inter-process communication
It is carried out by using pipes, message queues
------------------------- 4 Mark for any 4 correct points
e) Define RTOS. Why RTOS is needed?
RTOS:A real-time operating system (RTOS) is a program that schedules execution in a timely
manner, manages system resources, and provides a consistent foundation for developing
application code.
RTOS is needed when
Application requires the system to respond to an event within specific amount of time.
System need to do multitasking in a manner in which all the concurrent task s will get
completed within specific time limit.
Extreme optimization of memory recourses is required.
Better inter process communication resulting in deterministic behavior of system is
required.
------------------------- 1Mark for definition and 3 mark for any 3 relevant points