University Of Hail
Community College
Electrical Engineering Department
Electronics Engineering and Instrumentation Program
Digital Circuits II (EEI 200)
Dr. Fawzy Hashem
Date:
PROGRAMMABLE LOGIC DEVICES
(PLDs)
Programmable Logic Devices (PLDs) are ICs with a large number of gates and flip
flops that can be configured with basic software to perform a specific logic function
or perform the logic for a complex circuit. Major types of PLDs are:
SPLDs: (Simple PLDs) are the earliest type of array logic used for fixed functions
and smaller circuits with a limited number of gates.
CPLDs: (Complex PLDs) are multiple SPLDs arrays and inter-connection arrays on a
single chip.
FPGAs: (Field Programmable Gate Arrays) are a more flexible arrangement than
CPLDs, with much larger capacity.
SIMPLE PROGRAMMABLE LOGIC DEVICES (SPLDs)
Two major types of SPLDs are the PAL and the GAL. PAL stands for programmable
array logic, and GAL stands for generic array logic. Generally, a PAL is one time
programmable (OTP), and a GAL is a type of PAL that is reprogrammable. The basic
structure of both PAL and GAL is a programmable AND array and a fixed OR array,
which is the basic sum-of-products (SOP) architecture.
SPLD: The PAL
A programmable array is essentially a grid or matrix of conductors that form rows and
columns with a programmable link at each cross point, as shown below:
Each programmable link, which is a fuse in case of PAL, is called a cell. Each row is
connected to the input of an AND gate, and each column is connected to an input
variable or its complement.
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By programming the presence or absence of a fuse connection, any combination of
input variables or complements can be applied to an AND gate to form the desired
product terms. The AND gates are connected to an OR gate, creating a sum-ofproduct output.
SPLD: The GAL
The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For
this reason, they are useful for new product development (prototyping) and for
training purposes. The basic difference is that a GAL uses reprogrammable process
technology, such as EEPROM (E2CMOS), instead of fuses, as shown below:
Simplified Notation for PAL/GAL Diagrams
Most PAL and GAL diagrams that you may see on a data sheet use simplified
notation, as illustrated below:
The triangle symbol represents a buffer that produces both the variable and its
complement. Programmable links in an array are indicated by X at the cross point for
an intact fuse or other type of link. The absence of X indicates an open fuse or other
type of link. The output of the OR gate indicates that the variable logic function
(AB + AB’ + A’B’) is programmed.
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PAL/GAL General Block Diagram
A general block diagram of a PAL or GAL is shown below:
Remember, the basic difference is that a GAL has a reprogrammable array and the
PAL is one-time programmable.
The programmable AND array output go to fixed OR gates that are connected
additional output logic. An OR gate combined with its associated output logic is
typically called a macrocell.
Macrocells
The following figure illustrates three basic types of macrocells with combinational
logic.
Part (a) shows a simple macrocell with the OR gate and an inverter with a tristate
control that can make the inverter like an open circuit to completely disconnect the
output. The output of the tristate inverter can be either LOW, HIGH, or disconnected.
Part (b) is a macrocell that can either an input or an output. When it is used as an
input, the tristate inverter is disconnected, and the input goes to the buffer that is
connected to the AND array.
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Part (c) is a macrocell that can be programmed to have either an active-HIGH or an
active-LOW output, or it can be used as an input. One input to the exclusive-OR
(XOR) gate can be programmed to be either HIGH or LOW. When the
programmable XOR input is HIGH, the OR gate output is inverted. And when the
programmable XOR input is LOW, the OR gate output is not inverted.
SPDL Chip
The PAL16V8 and the GAL22V10 are common types of PALs and GAL. The device
designation indicates the number of inputs, the number of outputs, and the type of
output logic. For example, 16V8 means that the device has (16) inputs, (8) outputs,
and the outputs are variables (V). The block diagram of a PAL16V8 and a typical
SPLD package are shown below:
Each macrocell has (8) inputs from the AND gate array, so you can have up to (8)
product terms for each output. There are (10) dedicated inputs (I), (2) dedicated
output (O), and (6) pins that can be used as either inputs or outputs (I/O). The PAL
16V8 has a density of approximately 300 equivalent gates.
THE COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLDs)
The CPLD is basically a single device with multiple SPLDs that provide more
capacity for larger logic design. A Typical CPLD device, shown below, has multiple
logic array blocks (LABs) that are actually SPLDs on a single IC. LABs are
connected via a programmable interconnect array (PIA).
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Most programmable logic manufacturers make a series of CPLDs that range in
density, process technology, power consumption, supply voltage, and speed. Most
CPLDs are reprogrammable and use EEPROM or SRAM process technology for
programmable links. Several manufacturers like Altera, Xilinx, Lattic, and Cypress
produce CPLDs with different architectures.
Xilinx CPLDs
The architecture of the Xilinx CPLD family is based on PLA (programmable logic
array) structure rather than on PAL (programmable array logic). The following figure
compares a simple PAL structure with a simple PLA structure.
As you know, the PAL has a programmable AND array followed by a fixed OR array
and produces an SOP expression, as shown in part (a). The PLA has a programmable
AND array followed by a programmable OR array, as shown in part (b).
Macrocell
The macrocell for Xilinx architecture includes, in addition to combination logic, flipflops (registers), as shown below, which allow the CPLD to perform sequential logic
as well. The macrocell can be programmed to operate in either combinational or
registered mode.
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In combinational mode, the macrocell is programmed to produce an SOP
combinational logic function. In this case the data path is selected (multiplexed) to
bypass the flip-flop.
In registered mode, the macrocell is programmed such that the SOP combinational
logic output providing the data input to the flip-flop, which is clocked (synchronized)
by one of the global clocks.
THE FIELD PROGRAMMABLE GATE ARRAYS (FPGAs)
The FPGA differs in architecture from classic CPLD. It does not use PAL/GAL or
PLA type logic array, and has much greater densities than CPLDs.
The FPGA architecture consists of three basic elements: the configurable logic block
(CLB), the programmable interconnections, and the input/output (I/O) blocks, as
illustrated below:
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Configurable Logic Blocks (CLBs)
Typically, an FPGA logic block consists of several small logic modules that are the
basic building units, somewhat analogous to macrocells in CPLD.
The figure below shows the fundamental configurable logic blocks (CLBs) within the
global row/column programmable interconnects that are used to connect logic blocks.
Logic Modules
A logic module in an FPGA logic block can be configured for combinational logic,
registered logic, or a combination of both. A bock diagram of typical LUT-based
logic module is shown below:
As you know, an LUT (look-up table) is a type of memory that is programmable and
used to generate SOP combinational logic functions. The LUT essentially does the
same job of PAL or PLA does.
Programmable Interconnect
-----------------------
FPGA Cores
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FPGA, as we have discussed, is essentially soft-core that the end user can program
for any logic design. FPGAs are available that also contain hard-core logic. A hard –
core is a portion of logic in an FPGA that is put by the manufacturers to provide a
specific fixed function.
For example, if the end user needs a small microprocessor as part of a system design,
it can be programmed into the FPGA by the user or it can be provided as hard-core by
the manufacturers. Hard-cores are generally available for functions that are commonly
used in digital systems, such as a microprocessor, standard input/output interfaces,
and digital signal processors.
The figure below illustrates the concept of a hard-core surrounded by configurable
logic programmed by the user. This is the basic embedded system because the hardcore function is embedded in the user-programmed logic.
PROGRAMMABLE LOGIC SOFTWARE
All manufacturer of SPLDs, CPLDs, and FPGAs provide software support for each
hardware device. These software packages are in category of software known as
computer-aided design (CAD). The programming process is generally referred to as
design flow. A basic design flow diagram for implementing a logic design in a
programmable device is shown below:
The first step is to enter the logic design into a computer. It is done in one of two
ways:
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1) Schematic entry
2) Hardware description language (HDL).
In schematic entry, the design is drawn on a computer screen by placing components
and connecting then with simulated wires. After drawing the schematic, it can be
reduced to a single block symbol.
In text entry, the design is entered via a hardware description language such as
VHDL or Verilog.
After entering the circuit into an HDL (such as VHDL), the circuit is tested in a
functional simulation. The functional simulation is part of the HDL. You can test the
circuit with waveforms to verify the operation.
After the simulation, the computer program optimizes the logic by eliminating
redundant terms and synthesizing (generating) a netlist, (a connection list) that is a
complete description of the circuit.
The computer next “maps” the design from the netlist to fit it to a target device. Data
for all potential target devices are in a software library. The computer must account
for the I/O pins and fit the logic to the target device.
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