SIGGSP: Low-Power Circuit Techniques for iSensors
Monthly Report (August 15, 2011)
1. Team Members
NTU PI:
Students:
Intel Champion:
Tsung-Hsien Lin
Chun-Yu Lin (MS), Jian-You Chen (MS)
Hasnain Lakdawala
2. Discussion with Intel Champion
8/9 (Tue.) 8~9 am: conference call with Dr. Y.-K. Chen, Dr. Hasnain Lakdawala, and
Dr. Chang-Tsung Fu.
a. Discuss the background IP issue.
Summary (copied from the note email (8/9) from YK):
(1) We would like to get around the background IP technically.
a. We prefer not going through the legal process of licensing the background IP.
(2) We will design a new circuit architecture based on some prior publications (e.g., from
Intel) so that it does not depends on the background IP.
a. The new circuit architecture will be the tech transfer target between NTU and
Intel. Intel will have to re-implement the circuit for Intel process technology and,
thus, we should not exactly “copy” NTU implementation.
b. However, we will NOT change the working items this year. This is because
Tsung-Hsien’s current working items will continue to contribute the basics of the
new architecture.
ARs:
(1) Tsung-Hsien will send the patent application to Hasnain and Chang-Tsung [Due today]
(2) Hasnain and Chang-Tsung will find a couple of publications and come up with a new
target architecture [Due three weeks]
(3) We plan to document the new architecture in the RPD.
b. Briefly discuss the low-power design of a delta-sigma modulation; .
3. Progress
a. The prototype chip design has passed the CIC review on 7/23, and is current
under fabrication. The expected chip out date is Dec. 1, 2011 (according to CIC
data).
b. The whole chip layout and performance summary is shown below.
1
4. Brief Plan for Next Month
a. Improve the power consumption of the VCO from 2.2 mW to sub-mW;
investigate the tradeoff among power, phase noise, and other performance
metrics.
b. Investigate the 2.4-GHz and 900-MHz dual-band operation.
c. Improve the digital FIR spur by enhancing the OSR.
5. Research Byproducts
N/A
6. Reference
N/A
2