EE6621/EE4407 Project (2013) 30%
Project Description.
A basic 4-digit calculator system is modelled to the block diagram, pin description,
functional table and waveform example. A sequence of up to 4 BCD (Binary Coded Decimal)
inputs is entered, followed by a + or – operation. Another 4 inputs are entered, and the resulting
addition or subtraction of both numbers is displayed on the 4 ½ signed digital output.
Figure 1: Block Diagram
DigMinus
ENT
Dig4
Dig_in
Dig3
CLR
CALCULATOR
CALCULATOR
Dig2
+
Dig1
=
Dig0
Figure 2: Pin Description and functional table
PIN
CLR
Input / Output
Input
Dig_in
ENT
Input (4-bit)
Input
+
Input
-
Input
=
Input
Dig4
Dig3
Output
Output (4-bit)
Dig2
Output (4-bit)
Dig1
Output (4-bit)
Dig0
Output (4-bit)
DigMinus
Output
Description
Active high reset pulse, to set all output to 0 and
reset the system.
A 4-bit BCD number. Valid number is 0 to 9.
An active high of this signal should indicate to
the circuit that the value at pin Dig_in is valid
for calculation.
An active high of this signal indicates that the
previous inputs from Dig_in should be stored at
the first valid number (REG_A). The following
(up to 4) inputs to Dig_in (REG_B) should be
added to this number.
An active high of this signal indicates that the
previous inputs from Dig_in should be stored at
the first valid number (REG_A). The following
(up to 4) inputs to Dig_in (REG_B) should be
subtracted from this number.
An active high of this signal should perform an
addition (REG_A+REG_B) or subtraction
(REG_A-REG_B), and display the result on
pins Dig4, Dig3, Dig2, Dig1, Dig0 and
DigMinus.
The most significiant bit of the result.
The 2nd most significiant digit of the result, or
the current 2nd most significiant digit of the
current input.
The 3rd most significiant digit of the result, or
the current 3rd most significiant digit of the
current input.
The 2nd least significiant digit of the result, or
the current 2nd least significiant digit of the
current input.
The least significiant digit of the result, or the
current least significiant digit of the current
input.
1 indicates the result is negative. 0 indicates the
result is positive.
Figure 3: Waveform Example 0827 + 9293 = 10120.
CLR
ENT
Dig_in[3:0]
0
8
2
7
9
2
9
3
+
=
Dig0[3:0]
Dig1[3:0]
Dig2[3:0]
Dig3[3:0]
Dig4
DigMinus
0
8
0
2
7
8
2
0
8
0
9
2
9
3
0
9
2
9
2
9
2
1
9
0
Figure 4: Waveform Example 0827 - 9293 = -8466.
CLR
ENT
Dig_in[3:0]
0
8
2
7
9
2
9
3
=
Dig0[3:0]
Dig1[3:0]
Dig2[3:0]
Dig3[3:0]
Dig4
DigMinus
0
8
0
2
7
8
2
0
8
0
9
2
9
3
6
9
2
9
6
9
2
4
9
8
Design the Verilog Behavioural Code for the above system.
module calc (clr,d_in,ent,pls,mns,eq,q0,q1,q2,q3,q4,qmin)
.
.
.
.
.
.
.
endmodule
Complete the following test stimulus to test the full functionality of the circuit, using al least 8
different calculations.
module test;
.
.
.
.
calc i1 (clr,d_in,ent,pls,mns,eq,q0,q1,q2,q3,q4,qmin)
.
.
.
.
endmodule
Simulate and Synthesise the design.
Work to be done.
Task
Write a behavioural VERILOG description of the calculator. Compile
without Errors.
Simulate the full functionality of the design with an appropriate set of
test vectors.
Synthesize the design.
Project Deadline.
End of Week 13. (Friday 6 December 2013).
Marks
10
10
10