97.350
Sample Problems
Short Answer
1. What is the main purpose of synthesis?
Take a high level description and convert it into a gate level description which is
typically implemented in an FPGA or custom chip (ASIC).
2. What is the purpose of Verilog?
Allows you to (a) textually describe circuits at a number of different levels (b) easily
simulate parallel components and circuit timing.
3. Why don't we use a programming language like C or C++ for hardware simulation?
Standard programming languages normally do not have all the build in hooks to handle
hardware operating in parallel and the associated timing properties of hardware (i.e. it is
much more difficult than using Verilog or VHDL)
4. What is a key difference between a C compiler and synthesizer like FPGA Express?
A C compiler targets a single hardware configuration (i.e. the processor your running the
code on) and is therefore typically very efficient. A synthesizer has to target a possibly
infinite number of hardware configurations (i.e. the number of registers, ALUs, counters,
etc. is only constrained by the amount of hardware you have available).
5. What are the differences and similarities of a C subroutine and a Verilog module?
A module/subroutine can be called by another module/subroute and can pass
signals/variables and form a hierarchical program structure. Unlike a subroutine,
different versions of a module (instances) can exist and run at the same time.
6. What are the main characteristics of a verilog test bench?
It is the highest level module and is normally not synthesized (i.e. converted into
hardware). It generates all signals and timing to feed into the circuits and controls the
simulation of the circuits.
7. What is the typical module hierarchy in a design?
The highest level module is the test bench which controls the overall simulation of the
circuit (it is not synthesized into hardware). Below the test bench is the top circuit
module which contains all the I/Os of the circuit and usually collects all the lower level
modules (e.g. the top circuit module for a microprocessor might collect modules like
ALU, instruction_ram, data_ram, interrupt controller, etc.). Below the top modules are
the other modules which may have their own hierarchy (e.g. an ALU module might have
submodules register, adder, incrementer, etc. and adder might have a submodule
one_bit_adder).
8. Give two examples of verilog data types and explain what they would synthesize into.
wire - synthesize into a wire (i.e. a simple connection in the circuit)
reg - may synthesize into a latch, flip-flip, or wire
integer - normally does not get synthesized
9. What are the results of the following operations?
(27 && 3)
5'b11001 ^ 5'b01101
& 3'b101
1
5'b10100
0
10. What is the main advantage of procedural Verilog code? What is the main
disadvantage?
Main advantage - easier to code (i.e. don't have to worry about lower level gates can use
stagements like if-then-else, case, etc.)
Main disadvantage - More difficult to synthesize. May use more hardware then necessary
and harware is expensive.
11. Does it make sense to combine procedural and structural Verilog in a single module?
Yes. This is one of the strengths of a hardware description languate like Verilog. It
allows you to combine easily written procedural code with hardware efficient structural
code which can all be simulated in parrallel and synthesized. It's like a C compiler that
allows embedded assembly code modules.
12. What would the following code synthesize into? Why?
always @(x)
begin
Q=4'b0000;
If (clk) Q[x] = 1;
end
This would synthesize into combinations logic. All Q[i]'s are calculated in one entry (i.e.
three are set to 0 and the forth (active one selected by x) is set to 1 every time there is a
change in x). There is no need to remember the Q's therefore not latches or flip-flops.
13. What are the three main concepts of time in Verilog. Explain one.
delay , edge-triggered event, and wait.
A delay if of the form # <delay> <event> . The simulator will wait <delay> time units
before a scheduled event takes place (e.g. q = #5 x&y waits 5 time units before any
change on q).
14. What are the two types of procedures in Verilog? When do they operate?
Initial procedure starts operating at time t=0 and continues until told to stop (i.e. last
event occurs).
Always procedure runs all the time. When it finishes it starts again.
15. Why do we separate the timing from the logic in a verilog FSM?
It makes it easier to code. Once the timing is defined it doesn't have to change. We can
modify the functionality (e.g. case statement) without affecting the timing.
16. Do Verilog FSM's normally used flip-flops or latches? Why? Write some code to
generate the storage elements of a Verilog FSM.
They normally use flip-flops. Latches would allow the state variable to cycle right
through the FSM when in transparent mode (i.e. the FSM wouldn't work).
always @(posedge clk or negedge reset_N);
begin
if(!reset_N) state = s0;
else
state = nxt_st;
end
17. What does the following Verilog code describe? What is wrong with it?
reg [3:0] q;
always @(posedge clk or negedge reset_N);
begin
if (!reset_N) q = 0;
else
q = q << 1;
q[0] = q[3];
end
This is a four bit shift register that feeds it's output back to it's input. The problem is that
it uses feedback and blocking assignment operators. q[0] will be set to the new value of
q[3] not the old value and therefore the shift register will not operate correctly.
18. Are there any problems with the following Verilog code?
always @ (state or a or b or c);
begin
a = b | (c & d);
b = d | c;
end
The problem is that d is not in the trigger list. The value of d could change and you
would not see a change in the outputs until a, b, or c changed.
A second problem is that a variable on the left side of the equal sign (a, b) cannot appear
in the trigger list. The machine may go into a infinite zero-delay loop.
19. Would the following code infer combinational logic, latches or flip-flops? Why?
module infer(q,d,c);
input d,c;
output q;
always @(c or d);
if (c == 1) q <= d;
endmodule
This would infer a latch. If c or d changes and the value of c is 0 the q output has to
remember the old value (i.e. it needs a storage element). Since the trigger is level
sensitive (i.e. no posedge or negedge) the storage element will be a latch.
20. How can you prevent a case statement from inferring latches?
Make sure all possible cases are defined or include a default case.
21. Write some simple Verilog code to generate a flip-flip with asynchronous reset. Why
is it asynchronous?
always @(posedge clk or negedge reset_N);
begin
if (!reset_N) q <= 0;
else
q <= d;
end
It is asynchrouous because if reset changes from high to low (negedge) it will trigger the
always proceedure and reset the flip-flop irrespective of the value of clock (i.e. it doesn't
need a change on the clock signal to reset the flip-flop).
22. What are Verilog compiler directives? Give an example.
A compiler directive is a special command that forces the synthesizer to generate the
hardware is a specific way. An example would be to force an asynchrounous reset or a
full case statement.
// synopsys asynch_set_reset "R"
For the synopsys synthesizer the signal "R" is an asynchronous reset.
23. Rewrite the following Verilog code to minimize the number of flip-flips.
reg [2:0] onereg, tworeg;
always @(posedge clk or negedge reset_N);
begin
if (!reset_N) onereg <= 0;
else
begin
onereg <= ounreg + 1;
tworeg <= & onereg;
end
end
It can be rewritten to eliminate the flip-flops in tworeg since then can be directly
generated from onereg and some combinational logic.
reg [2:0] onereg, tworeg;
always @(posedge clk or negedge reset_N);
begin
if (!reset_N) onereg <= 0;
else
begin
onereg <= ounreg + 1;
end
end
assign tworeg = & onereg;
note: even though tworeg is defined as a Verilog register it with be synthesized into
combinational logic as it doesn't have to remember it value (i.e. its value is continually
updated using the assign statement).
24. In Verilog what do we mean by multiple assignments? Is it ok?
Multiple assignments mean that we have two outputs connected together (e.g. two
separate procedures set the value of the same register). This will not function correctly as
the synthesizer will not allow two outputs to be connect (would destory your chip). Even
if the outputs never have the situation that they are driving opposite signal levels the
compiler will not be smart enough to realize this.
25. How are negative numbers handled by verilog registers?
Verilog registers are always treated as non-negative integers.
26. How does the casex statement work in verilog. Why would you want to use it?
The casex statement is like a regular case statement with the additional feature of being
able to handle unknown or don't care values. The advantage is that it allows you to write
more compact code. Case 8'b1xxxxxxx specifies 128 of the 256 possible states.
27. What does the signal for a static-zero hazard look like?
The signal will always be logic zero except when the hazard occurs which will cause it to
temporarly go to logic one (i.e. glitch rises).
28. What causes a static-one hazard?
Two parallel paths for a signal in which (1) one of the signal paths is inverted (2) the two
signal paths reconverge into an OR gate.
29. Can a dynamic hazard have an embedded static hazard? When?
Yes. A dynamic hazard always has an embedded static hazard.
30. Can you elliminate a hazard by adding delays to your circuit?
If the delays through the paths of the hazard are exactly matched you can eliminate the
hazard. In the real world this is almost impossible to do as the delays will vary with
temperature and supply voltage and will be impossible to match, even if you have very
fine control of the delays such as you would with a custom chip design.
31. Using a Karnaugh map, how can we tell if a circuit has a hazard?
On a karnaugh map, adjacent but non-overlapping circles are hazards.
32. Using a sum of products Karnaugh map, how can we mask a static-1 hazard?
Find adjacent but non-overlapping circles, form a new circle (using an AND gate) that
covers (stats high across) the transition between the original circles.
33. A product of sums karnaugh map can be used to mask what type of hazards. How
does the mask get physically implemented?
The product of sums map can be used to mask static-0 hazards. The mask gets physically
implemented as an OR gate.
34. What types of hazards are the following?
xx
x + xx
static-0 hazard
dynamic hazard
35. When using boolean algebra with hazards what is an important rule to follow?
(1) treat x and !x as separate variable (2) avoid the distributive law (factoring).
36. For the following boolean expression are there any hazards? Find a mask for any
hazards.
f  (a  b)c  cab
a=1, b=1
(1  1)c  c  1  1
c c
Yes there is a static-1 hazard. Using a sum of products representation, the mask for the
hazard would be a . b to give the final expression.
f  (a  b)c  cab + ab
37. If you have a boolean expression, what is the first test to see if there is a potential
hazard in a given variable.
The first test is to see if the variable and its complement are present in the expression. If
not, there is no possibility of that variable causing a hazard.
38. It is always possible to determine if hazards exist by going through all possible
combinations of the inputs to a boolean expression. Fortunately, in most cases the
analysis can be simplified by using a little thought. Explain how you could simplify
the analysis of the following expression.
f  (a  b + c)(d + e)  cde + (a + b + e)d
The only variable that can give a possible hazard is c (i.e. there are both c and !c in the
expression). Since c and !c only occur once, for them not to be eliminated d and e have
to be 1 (otherwise there would be no !c) and a and b have to be 0 (otherwise there would
be no c). Once you set the values of a,b,d and e the analysis is greatly simplified.
39. How do you mask a dynamic hazard?
Embedded in any dynamic hazard is a static-0 or static-1 hazard. Determine the part of
the boolean expression that contains the static hazard. Mask the static hazard using
regular sum of products or product of sums analysis. Form final expression by
combining masked static hazard with remainder (part that doesn't contain the static
hazard) of original expression.
40. Can a sum of products circuit have a static-0 hazard?
Only in the careless case where the is a product term that includes a signal and its
complement (a useless term that is always equal to 0).
41. Using a Karnaught map analysis, explain whay some two variable changes not
maskable?
When the inputs change you travel from one location on the Karnaugh map to another. If
both the starting and final location have the same value and you travel through an
intermediate location of the opposite value you can generate a glitch (i.e. there is a
hazard). You cannot mask this because you cannot overlay the intermediate location with
the opposite value, otherwise the overall logic would be incorrect.
42. For multiple variable changes, what are the two possible conditions required for
hazard free operation?
a) All possible Karnaugh map sqaure that may be travelled through have the same value.
b) Fixing the stationary variable cannon reduce the function to any of the hazard
combination (e.g. a + !a, a!a, etc.)
43. Why don't hazards hurt synchronous circuits?
In synchronous circuits flip-flops only respond on a clock edge. Glitches due to variable
changes occure shortly after the clock edge. If the clock period is long enough to allow
the glitches to die out they will have no effect.
44. Give an example of a circuit that is sensitive hazards (i.e. glitches).
Any asynchronous circuits (e.g. memories, bus drivers, etc.).
45. What effect to glitches have on the power consumption of a circuit. Why?
They increase the power consumption. In particular, the dynamic power consumption is
dependent on the number of nodes charged or discharged in a given period of time.
Glitches will increase the number of nodes that are changing state and therefore being
charged or discharged.
Second set of Questions
1. What defines the region of a d-flip-flop where the data must hold still?
The region is defined by the setup time and hold time of the d-flip-flop.
2. What do we know about the hold time of most modern flip-flops?
It is zero or negative.
3. Give an example of typical setup and hold times for modern d flip-flop.
Setup time = 2ns , hold time = 0ns
4. What happens if the d input of a flip-flop changes in the restricted region?
The flip-flop output can go 0,1 or metastable.
5. What is the definition of an asynchronous signal?
An asynchronous signal is one that can change in the restricted region around a clock
edge.
6. Why is the output of a flip-flop synchronous? Is this always true?
The output is synchronous because the finite output delay guarantees that it will not
change in the restricted region of any subsequent flip-flop. This is true as long as the
output delay is greater than the hold time and the flip flops clocks change at the same
time (i.e. must take into account clock skew).
7. If we have an asynchronous signal being fed into a synchronous circuit, what is the
easiest whay to make it acceptable?
The simplest way is to pass it through a synchronous flip-flop whose output will be
synchronous signal.
8. What is the potential problem with feeding an asynchronous input into a synchronous
state machine?
If the input is fed into two or more flip-flops of the state machine is may cause a race
condition if its change is captured by one flip-flop and not by another.
9. If we have a synchronous state machine with two unencoded asynchronous inputs
what do we know about the state assignment?
Children states must be adjacent on the karnaugh map (i.e. only one stage variable change
apart)
10. What is the potential difficulty of flip-flops with asynchronous reset?
In a synchronous state machine all the flip-flops will have a common asynchronous input
(reset) which could cause problems when coming output of reset.
11. What is the potential difficulty with a group of asynchronous inputs which are
logically related (i.e. encoded)?
We have to ensure that they all get captured at the same time otherwise their encoded
values will have no meaning. If there not related to each other we don’t care if there
captured one or two clock cycles early or late.
12. How can we use coding to minimize problems with encoded asynchronous inputs?
We can code them such that there is only one bit change at any given time (e.g. gray
code, thermometer code).
13. What is the basis for using handshaking for multiple encoded asynchronous inputs?
We mush know the timing relationship between all the asynchronous inputs so that the
synchronous circuit that accepts the handshaking signal will wait for all the inputs to
stabilize before it accepts the inputs.
14. How can we use a debouncing circuit to accept a group of encoded asynchronous
inputs? Will it always work?
If we sample the inputs two or more times and they do not change then we assume they
have stabilized and accept their value. It will work as long as the inputs once changed
will stay stable for several clock cycles.
15. Which is preferred, hardware or software debouncing?
If it is fast enough and does not create to much overhead for the processor, software
debouncing is preferred because it requires no extra hardware.
16. If you have two synchronous flip-flops with some gates in between what is the
minimum clock period?
Tmin = Tchqv + Tpd + Tsetup
17. Why is there a minimum gate proagation delay between two synchronous flip-flops?
If there is clock skew or a large hold time you have to observe a minimum prop delay or
you will have cycle skipping (i.e. signal passing through two flip-flops in one clock
cycle).
18. How does negative clock skew affect the minimum and maximum prop delays
between synchronous flip-flops?
It decreases both the minimum and maximum prop delay. Decreasing the minimum is
good (less likely to have cycle skipping) whereas decreasing the maximum is bad
(reduces the maximum clock frequency).
19. If a shift register has Tpd = 0ns, Tchqv = 1ns, Tsetup = 1ns, Thold = 0ns, Tclock =
10ns and a worst case positive clock skew Tskew = 7ns. Will the circuit work
correctly?
No. Cycle skipping will occur if Tchqv + Tpd < Thold + Tskew. Normally want to keep
Tskew < Tchqv
20. In a shift register, what is the advantage of routing the clock against the data shifting
direction?
This gives a negative skew which means that we normally wont have to worry about
minimum prop delay (i.e cycle skipping) problems.
21. What are the problems with gating a clock signal?
Added clock skew, false clock edges, difficult to test (scan based testing)
22. What is the advantage of gating the clock?
It saves power by turing off the high frequency clock signals to flip-flops.
23. For a positive edge triggered flip-flop that is gated with an AND gate. How do we
prevent false clocks?
Make sure there are no positive edges on the enable signal when the clock is high.
24. What is the advantage of gating a positive edge triggered clock with an OR gate
instead of an AND gate?
It is easier to design because we only have to worry about its state in the second have of
the clock cycle (when clock is low). This means we don’t have to worry about minimum
prop delays or fast glitches.
25. What is the advantage of adding a transparent low latch to your AND gated postitive
edge triggered clock.
Like the OR gate it eliminates the problems of minimum delay and fast glitches, unlike
the OR gate it gives a full clock cycle (instead of a half clock cycle) for maximum prop
delay.
26. What is the advantage of using a clock divider compared to clock gating?
A clock divider uses less power with lower speed clocks during normal operation and
when the clocks are turned off. Even when the flip-flop clocks are turned off, a gated
clock dissipates power in the high speed clock signal distributed around the chip (i.e. the
gating is done locally)
27. Whey is a synchronous counter better than a ripple counter for use as a clock divider?
The outputs of a synchronous counter change at approximately the same time (i.e. they
are connected to the flip-flop outputs and the flip-flops are clocked with the same signal).
28. What is the purpose of a clock resynchronizer?
It synchronizes the main clock with the clock divider outputs.
29. How can we prevent cycle skipping between isochronic regions?
Add gate delays to compensate for clock skew or even better add a transparent latch
which will allow up to 180 degrees clock skew.
30. An asynchronous circuit with an odd number of inversions in the feedback path is
what kind of circuit?
An oscillator.
31. What defines the state variables in an asynchronous circuit?
A feedback loop.
32. What three steps that are typically used to analyze an asynchronous circuit?
(a) break feedback loops at appropriate places (b) write equations relating the values of
the input side to the values of the output side of the break (c) make a state table
33. When an asynchronous circuit behave differently when certain gate delays are fast or
slow what can we say about the circuit?
It is delay dependent and has a race.
34. How can we tell if an asynchronous circuit has a race?
It will have a double state variable change during at least one of its state transitions.
35. What are noncritical races?
Races that take different paths but always end in the same final stable state.
36. What can we say about a cycle in the state table that has no stable states in the column
of the cycle and no races in the path?
The oscillation with continue forever or until it is turned off.
37. How are races and hazards related?
Races are hazards where the glitch may be latched.
38. If an asynchronous circuit has no races in the state table, but an analysis of the state
variable equations shows that there is a hazard, what do we know?
If there is a hazard the state table is unreliable and there may in fact be a race. If there is
a race it can usually be found by placing the state variable breaks at another location.
39. How do we get rid of races?
Races can be eliminated by proper state assignment. States connected to another state
must differ in value by only one state variable bit.
40. What are the three conditions required for having a delay depended asynchronous
circuit?
No races, hazard or essential hazards.
41. What is an essential hazard in an asynchronous circuit?
It is a race between an input and a state variable. It is an inherent property in any circuit
which must remember three input changes from a single input.
42. How can you eliminate essential hazards?
You can’t eliminate them. They are essential to the operation of the circuit by definition.
43. How do you test for essential hazards?
Make three changes in a single input variable. If a stable state after one change differs
from the stable state after three changes there is an essential hazard.
44. How can you defuse (i.e. make circuit work correctly with) essential hazards?
If necessary, add delays so the input signal change always races the state variable change.