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Chip Designer
October 21, 2007
Advanced Chip Verification
www.chipdesignmag.com/chipdesigner
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In this Issue:
1. Do Verification Engineers Have the Odds Stacked Against Them?
2. ARM and EVE Enter Co-Emulation Partnership
3. Low-Cost, Third-Party Starter Kits for STM32 Microcontroller
4. CryptoMemory Prevents Cloning and Counterfeiting
5. VisualDSP++ Release 5.0 for Blackfin, SHARC, and TigerSHARC
6. Japan's STARC Selects Extreme DA GoldTime
7. Low-Power SFF Motherboard Launches
8. In-Depth Coverage Links
> SystemVerilog Assertions and Functional Coverage Support Advanced Verification
> Moving to Advanced Design Abstraction
9. Featured Book
> ESL Design and Verification: A Prescription for Electronic System Level Methodology
10. Happenings -- Conferences
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1. Viewpoint - Exclusive
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Do Verification Engineers Have the Odds Stacked Against Them?
By Michel Courtoy, President and CEO, Certess Inc.
(http://www.certess.com/)
[headshot: 1007_CD_MCourtoy.jpg]
The increasing complexity of design verification is a subject that has been rehashed many times. The
often-repeated complaints are that the resources needed to verify a chip, and to generate the required
quantity and complexity of code, exceed the resources used on the design side.
Clearly, the old rumor that verification was a career only for engineers who could not cut it on the
design side has been put to rest. Verification attracts the brightest and most creative talents, eager to
master the complexity of their task and adopt new technologies. This assertion (pun intended!) is true for
both tool creation and tool use.
On the electronic design automation (EDA) tools side, a lot of innovative technologies are emerging in
the functional verification space. Over the last few years, we have seen, in succession, start-ups get
funded and their products enjoy significant acceptance in the areas of testbench automation, assertionbased verification, and formal verification. At the most recent Design Automation Conference, a new
group of verification start-ups emerged. Gary Smith created the new “intelligent testbench automation”
segment to bracket those companies together; this grouping includes Certess.
However, there seems to be a scarcity of quality verification engineers. So why aren’t we training more
top-notch verification engineers?
The education work must start in the universities, where verification must be integrated in the
engineering curriculum. A quick survey shows that verification classes are becoming available, although
they still trail design courses by a large margin. But we are missing the most important tool for coaching
verification engineers: providing them with regular feedback based on objective quality measurements
of their work.
Let’s contrast this with design engineers: How do they become good at their craft? They start with all
the great knowledge gleaned from design classes taken throughout college. Then, they are guided by
clear specs with well-defined objectives: timing, power, area, and so on. And finally, they get constant
feedback on the quality of their work from their verification colleagues. This feedback is quick,
automated, and objective. With this combination of clear objectives and constant feedback, design
engineers quickly learn what mistakes not to make and can become proficient at their jobs without major
risk to a complex project.
Compare this to the plight of young verification engineers. The education system provides them, in most
cases, with only the basic rudiments of verification technology. The are then faced with writing lots of
code of great complexity while having to choose among a large arsenal of verification technologies. And
all this work must be done without the clear goals and tight feedback loop provided to the design
engineers. Verification work is most certainly conducted with targets in mind; however, those targets
often lack objectivity. For example, verification plans and coverage points are typical objectives set by
verification teams, but those are defined by engineers and thus subjective.
Where verification engineers are at a real disadvantage is in the lack of feedback loops. One obvious
loop is bugs found in silicon: a costly mechanism that is not very useful given its long lag time. There
are also code reviews, but those lack the automation and the objectivity that is inherent in the
verification tools that help the designers.
The lack of feedback about the quality of verification has interesting implications. Here are a few that
come to mind:
Some design and verification activities are exported by companies in search of new and lower-cost
talent pools. How does management gain the confidence that the new team is ready to take on a
more critical verification project?
All large semiconductor companies are formed through the merger of various corporations. Each
brings its own verification tools and methodologies. What criteria can be used to compare the flows
and bring some unity inside the company?
The same is true when considering the addition of a new tool to the flow. Does it really make the
flow better? Is vendor A better than vendor B?
When project managers are selecting the intellectual property (IP) blocks that will be used in a
system-on-chip (SoC) design, they must make a decision on how much trust to place in the quality of
the verification of the IP block. Wouldn’t it be easier to have an objective measurement to help this
assessment?
The emergence of an objective feedback loop will provide great help to the verification engineers and
SoC project managers. This will let engineers improve their skill sets and extract better value out of the
large array of verification tools at their disposal.
Michel Courtoy is the president and CEO of Certess Inc.
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2. News
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ARM and EVE Enter Co-Emulation Partnership
Emulation and Verification Engineering (EVE) has announced that it's signed a partnership agreement
with ARM to produce an integrated, high-end co-emulation environment. The ARM RealView SoC
Designer electronic system-level design software will be coupled and integrated with EVE's ZeBu
hardware-assisted verification platform for early architectural exploration and prototyping. The ARM
SoC Designer tool enables the deployment and simulation of system-level models of its IP blocks. Using
ZeBu with the SoC Designer tool allows reuse of existing RTL code without writing new models for
existing peripherals. Designs can move from simulation to emulation by removing models from the SoC
Designer tool and synthesizing the RTL on ZeBu.
ARM >> http://www.arm.com/
EVE >> http://www.eve-team.com/
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3. News
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Low-Cost, Third-Party Starter Kits for STM32 Microcontroller
STMicroelectronics has announced four low-cost evaluation and development kits from third-party tool
suppliers designed to support its STM32 microcontroller, which is based on the ARM Cortex-M3 core.
The Hitex starter kit is based on the HiTOP5 integrated development environment, offering project
management, source-code editing, and debugging features through an intuitive graphical interface.
IAR’s KickStart kit is based on the IAR Embedded Workbench for ARM (EWARM) development
environment, running on an STM32F103B KickStart development board. The Keil starter kit features
the Keil RealView Microcontroller Development Kit software, including the µVision3 integrated
development environment for application programming and debugging. The Raisonance REva starter
kit, based on the RIDE development environment for code up to 32KB, offers application debugging
and seamless control of the included GNU C/C++ compiler through an intuitive graphical interface.
STMicroelectronics >> http://www.st.com/
Hitex >> http://www.hitex.com/
IAR >> http://www.iar.com/
Keil >> http://www.keil.com/
Raisonance >> http://www.raisonance.com/
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4. News
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CryptoMemory Prevents Cloning and Counterfeiting
Atmel has announced the CryptoMemory family of devices that provide a secure means of preventing
product counterfeiting and piracy of IP and OEM parts. CryptoMemory uses a 64-bit embedded
hardware encryption engine, four sets of non-readable, 64-bit authentication keys, and four sets of nonreadable, 64-bit session encryption keys to provide a higher level of protection than products based
solely on EEPROM technology. Each time a transaction occurs, CryptoMemory uses its “secret”
authentication keys and a random number to generate a unique 64-bit session encryption key and a
unique 56-bit encrypted identity, called a cryptogram. Once the authentication and session encryption
keys are written to the device, fuse bits are blown to permanently lock the security information in the
device.
Atmel Corp. >> http://www.atmel.com/
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5. News
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VisualDSP++ Release 5.0 for Blackfin, SHARC, and TigerSHARC
Analog Devices has announced the release of VisualDSP++ Release 5.0. The integrated software
development and debugging environment is available for Blackfin, SHARC, and TigerSHARC
processors. The product comprises an integrated development environment, debugger, C/C++ compiler,
assembler, linker, and simulator as well as support for ADI’s range of emulators and development
boards. New features include a core file support feature that stores the contents of all registers and
memory at any point in time, allowing state restoration at a later time, and custom board support, letting
users customize register windows and reset values, then display the custom register windows in the
IDDE.
Analog Devices >> http://www.analog.com/
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6. International News
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Japan's STARC Selects Extreme DA GoldTime
Japan's Semiconductor Technology Academic Research Center (STARC) has selected the Extreme DA
GoldTime timing analyzer as its reference tool for STARC's statistical static timing analysis flow (SSTA
v. 1.5). The flow uses the GoldTime SSTA to optimize performance in conjunction with common IC
design tool sets. STARC engineers analyzed test chips and confirmed the benefits of the SSTA design
flow compared with traditional, worst-case corner methods. STARC expects its member companies to
see design performance improvements of approximately 10% through reduction in unnecessary
pessimism. The companies can also expect to reduce turn-around-time, IC die area, and power loss
through leakage.
STARC >> http://www.starc.jp/index-e.html
Extreme DA >> http://extreme-da.com/
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7. International News
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Low-Power SFF Motherboard Launches
Belgium's IMCE has introduced an ultra-low power (0.7 mW), high-speed (50MSamples/s) analog-todigital converter that claims to achieve a figure of merit of 65fJ per conversion step. IMEC's SAR ADC
design is designed for battery-powered IT applications. Its power scales linearly with the clock rate over
a wide range, makes it well suited for software-defined radio applications. The low-power architecture
of the SAR ADC uses passive charge-sharing to sample the input signal and perform the successiveapproximation cycling. As a result, the SAR operation is no longer based on voltage comparisons. It
operates in the charge domain, yielding enhanced performance. The ADC's digital implementation
requires only MOS switches and metal-oxide-metal capacitors, making it scalable toward the 45nm node
and beyond.
IMEC >> http://www.imec.be/
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8. In-Depth Coverage Links
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Every engineer knows that system-on-a-chip (SoC) verification is hard. Several widely cited studies
have concluded that functional verification consumes 60% to 80% of the resources during the registertransfer-level (RTL) phase of a typical SoC project. To learn more, read Tom Anderson's "
SystemVerilog Assertions and Functional Coverage Support Advanced Verification."
Chip Design Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1448
Today's changing design landscape is challenging existing design methodologies that have their roots in
a traditional board-centric approach, where separate tools create the hardware and software elements
from a "circuitry-up" perspective. To learn more, read Rob Evan's " Moving to Advanced Design
Abstraction."
iDesign Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1666
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9. Featured Book
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ESL Design and Verification: A Prescription for Electronic System Level Methodology
By Grant Martin, Brian Bailey, and Andrew Piziali
ISBN: 0123735513
Publisher: Morgan Kaufmann
From its genesis as an algorithm modeling methodology with no links to implementation, electronic
system-level (ESL) design is evolving into a set of complementary methodologies that enable embedded
system design, verification, and debug through to the hardware and software implementation of custom
SoC, system-on-FPGA, system-on-board, and entire multiboard systems. ESL technologies are
stabilizing on a useful set of standardized languages, such as SystemC, and use models are beginning to
get real adoption. ESL Design and Verification provides a prescriptive guide to ESL that reviews its past
and outlines the best practices of today. The authors share their experience as industry practitioners,
having seen ESL go through its many stages and false starts to its acceptance as a viable, mainstream
design approach.
Morgan Kaufmann >> http://www.mkp.com/
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10. Happenings -- Conferences
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International Test Conference
Santa Clara Convention Center, Santa Clara, CA
October 21-26, 2007
http://www.itctestweek.org/
GSPx 2007 International Signal Processing Conference
Santa Clara Convention Center, Santa Clara, CA
October 27 - November 2, 2007
http://www.gspx.com/
ICCAD 2007
DoubleTree Hotel, San Jose, CA
November 5-8, 2007
http://www.iccad.com/
11th OpenAccess+ Conference
Santa Clara Conference Center, Santa Clara, CA
November 5, 2007
http://www.si2.org/?page=890
Common Platform Technology Forum 2007
Santa Clara Convention Center, Santa Clara, CA
November 6, 2007
http://www.commonplatform.com/tf2007/default.asp
International System-on-Chip Conference
Radisson Hotel, Newport Beach, CA
November 7-8, 2007
http://www.savantcompany.com/SoC5-Nov2007/main.htm
IASTED Conference on Software Engineering and Applications (SEA 2007)
Hilton Family Hotel @ MIT, Cambridge, MA
November 19-20, 2007
http://www.iasted.org/conferences/home-591.html
Parallel and Distributed Computing and Systems (PDCS 2007)
Hilton Family Hotel @ MIT, Cambridge, MA
November 19-21, 2007
http://www.iasted.org/conferences/venue-590.html
IEEE Globecom 2007
Hilton Washington, Washington DC
November 26-30, 2007
http://www.ieee-globecom.org/
IEEE International Electron Devices Meeting (IEDM)
Hilton Washington, Washington DC
December 9-10, 2007
http://www.his.com/~iedm/
Wireless Broadband Forum
Hinxton Hall, Cambridge, U.K.
December 10-13, 2007
http://www.meridianconferences.co.uk/Wireless_Broadband_Forum_2007.htm
ISSCC
San Francisco, CA
February 3-8, 2008
http://www.isscc.org/isscc/
DesignCon 2008
Santa Clara Convention Center, Santa Clara, CA
February 4-7, 2008
http://www.designcon.com/2008/
DVCon 2008
DoubleTree Hotel, San Jose, CA
February 19-21, 2008
http://www.dvcon.org/
International Symposium on Field Programmable Gate Arrays
Monterey Beach Resort, Monterey, CA
February 24-26, 2008
http://www.ece.wisc.edu/~kati/fpga2008/
ISQED '08: The 9th Annual Symposium on Quality Electronic Design
March 17-19, 2008
DoubleTree Hotel, San Jose, CA
http://www.isqed.org/
System Level Interconnect Prediction (SLIP 2008)
Newcastle University, Newcastle. U.K.
April 5-6, 2008
http://www.sliponline.org/
International Symposium on Networks-on-Chip (NoCS 2008)
Newcastle University, Newcastle. U.K.
April 7-11, 2008
http://async.org.uk/nocs2008/
15th Annual Reconfigurable Architectures Workshop (RAW 2008)
Miami, FL
April 14-15, 2008
http://www.ece.lsu.edu/vaidy/raw/
International Symposium on Physical Design (ISPD 2008)
Embassy Suites, Portland, OR
April 13-16, 2008
http://www.ispd.cc/
International Symposium on Circuits and Systems (ISCAS 2008)
Sheraton Seattle Hotel, Seattle, WA
May 18-21, 2008
http://www.iscas2008.org/
Semicon West
Moscone Center, San Francisco, CA
July 15-17, 2008
http://semiconwest.semi.org/index.htm
Signal and Image Processing (SIP 2008)
Kailua-Kona, HI
August 18-20, 2008
http://www.iasted.org/conferences/ipc-623.html
Intel Developer Forum
Moscone Center West, San Francisco, CA
August 19-20, 2008
http://www.intel.com/idf/index.htm
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CHIP DESIGNER e-NEWSLETTER CONTACTS
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