Design Review I
Dual Threshold Voltage Domino Logic
Zhiwen Lu and Robert Addo
Part I
Publication summaries
by Zhiwen
The main references that lead to the topic we finally decide are listed and summarized
as follow. Not all the references will be included in the final report.
Reference 1:
Neeraj Kr. Shukla, Debasis Mukherjee, Shilpi Birla and R. K. Singh, ‘Leakage
Current Minimization in Deep-Submicron Conventional Single Cell SRAM’, 2010
International Conference on Recent Trends in Information, Telecommunication and
Computing
This paper includes a simple review of several popular techniques for leakage current
reduction, such as data retention gated ground, a drowsy mode and dynamic threshold
voltage. It demonstrates the first two approaches on a single 6T cell SRAM. The
author has provided good explanation of data retention gated-ground (DRG) cache
and the so called drowsy mode. It’s a good material for students outside the CMOS
field to have a grasp of the main technology involved nowadays.
In addition, the introduction brings up several approaches for the leakage reduction,
including standby leakage control using transistor stack, multiple Vth shceme
(multi-threshold voltage CMOS, dual threshold voltage CMOS, dynamic threshold
voltage CMOS, double gate dynamic threshold SOI CMOS, etc. ) Among them, Dual
Threshold Voltage CMOS finally becomes our topic for this project. And this paper is
a thread to it.
Reference 2:
Kalyana C. Bolapalli, Rajesh Garg, Kanupriya Gulati and Suil P. khatri, ‘Low power
and high performance SRAM design using bank-based selective forward body bias’,
GLSVLSI’09 May 10-12, 2009.
Applying a concept of word line groups (WLGs), suppressing leakage current is
demonstrated in a 512K Byte SRAM with 45nm technology. Several highlights of this
paper:
1. Achieved both improvement in power and speed by partitioning the SRAM into
WLGs: 9.2% improvement in access time and 53.4% reduction in power
consumption.
2. It develops an approach to optimize a WLGs based memory by modifying the
forward body bias, number of WLGs and the size for the driver driving the bulk of
WLG. The tradeoff between power and delay is thus achieved.
Reference 3:
Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag,
K. Soumyanath and Shekhar Y. Borkar, ‘A 130-nm 6-GHz 256 x 32 bit leakage –
tolerant register file’, IEEE Journal of solid-state circuits, VOL 37, NO. 5, May 2003
This paper describes a 256 word X 32 bit register file for 6 GHz operation in 1.2 V
130nm technologies. It realizes the leakage reduction with an approach named
pseudo-static technique. The pseudo-static technique is then further compared with
dual threshold Vt in performance, robustness and keeper sizing. It finally comes to the
conclusion that the pseudo-static technique achieves 8% faster read performance and
a simultaneous 36% increase in dc noise robustness.
Reference 4:
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping
Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, and Mark Bohr, ‘A 3.8 GHz 153 Mb
SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm
High-k Metal Gate CMOS Technology’ , IEEE Journal of solid-state circuits, vol. 44,
NO. 1, January 2009
This paper coordinates the 45nm high-k metal gate technology with the traditional
dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM
VCC in Sleep. VCCmin, performance, leakage and area are optimized for a 0.346 μm2
6T SRAM bitcell. The improvement in performance is demonstrated with a 16 KB
subarray on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.
Reference 5:
James T. Kao and Anantha P. Chandrakasan, ‘Dual-threshold voltage techniques for
low-power digital circuits’, IEEE journal of solid-state circuits’, VOL. 35, NO. 7,
July 2000
Reference 5 and 6 are closely related to the topic of this project. During the
demonstration of the similar idea – dual threshold voltage, a new domino logic will
be presented and addressing keeper sizing to achieve an optimized circuit with
analysis in different modes.
‘Dual threshold voltage domino logic provides the performance equivalent of a purely
low-Vt design with the standby leakage characteristic of a purely high-Vt
implementation.’
Several dual-threshold voltage techniques are applied in this paper, including
hierarchical transistor sizing methodology and a imbedded dual threshold domino
logic.
Reference 6:
Volkan Kursun and Eby G. Friedman, ‘Low Swing Dual Threshold Voltage Domino
Logic’, GLSVLSI .02, April 18-19, 2002
This paper combines low swing circuit technology and dual threshold voltage
technology in domino logic to achieve leakage reduction. It reviews the power
reduction techniques in design of reliable domino logic circuits. A low swing domino
logic with and without a keeper is discussed, where two types of keeper are also
compared. Low swing domino logic circuit with fully driven keeper is demonstrated
to provide the better performance compare to standard domino logic circuit and low
swing domino logic circuit with weakly driven keeper.
Part II
Initial implementation of a domino logic with and
without dual Vt voltage
By Robert Addo
We implemented an 8-input 4-stage AND gate using domino logic to investigate how
leakage current could be reduced in subthreshold operations. A keeper transistor was
introduced in each stage so that it could help in the “pull-up” of the output during a
low-to-high output transition. We built these circuits using only low threshold
transistors in one circuit, a purely high threshold transistors in a second circuit and a
combination of both in a third circuit. This helped us to compare their output under
various simulations.
Preliminary simulation result of the domino logics with and without dual VT shows
that the dual threshold voltage domino circuit which utilizes both a high threshold and
low threshold transistors has a similar performance characteristic as the domino logic
implemented with all low threshold transistors but it characteristics during the standby
mode is that of a domino circuit implemented with a high threshold transistors. This is
because the high threshold transistors are put along a non critical transition path that
switches during the precharge while the low threshold transistors are put along a
critical path which switches during the evaluate phase.
With the correct sizing of both the high and low threshold transistors in the dual VT
domino circuit, the leakage current of the circuit when operated in subthreshold is
significantly reduced
Further works to be done include sizing the transistors using various methods so that
an optimum operation could be achieved, finding ways of further improving the
performance of the circuit during both the precharge and evaluate phases by
proposing new techniques in duel VT.
Part III
Project progress and plan
By Zhiwen Lu
Phase 1: (Before proposal)
1. Research on the prevalent issues in VLSI design through references, narrow
the topic to reduce sub-threshold leakage current. Pick an efficient technique –
dual Vt and implement it into a popular circuit – domino logic to see if this
topic is practical. The results turn out promising.
2. Simulate a conventional domino logic to gain some initial result, including
comparison between circuits with and without dual Vt. During the simulation
process, transistor sizing turns out to play an important role in the performance
of the circuit. This may lead to the new idea on how to improve the current
dual Vt technique.
Phase 2: (After proposal)
3. Future work could include:
a. Develop a specific method to evaluate the circuit performance
b. Investigate the transistor sizing issues and expand the volume of the
circuit if necessary and possible
c. Study the various characteristics of the domino circuit, such as noise
margin, time delay and power consumption. Look for new techniques
that can optimize as many properties as possible within contemporary
technologies
Simulation printout and initial result: