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Design of HTS Coplanar Waveguide Matching
Circuit for Low Noise CMOS-HTS Receiver
H. Kanaya, Member, IEEE , Y. Koga, G. Urakawa, and K. Yoshida

Abstract—For realizing a single chip HTS integrated
microwave receiver, a superconducting slot antenna and a
Si-CMOS low noise amplifier (LNA) combined with a broad band
matching circuit composed of coplanar waveguide (CPW)
meanderline resonators has been designed and tested. By applying
the filter technique and using admittance inverters (J inverters),
we propose a new design method of CPW broadband impedance
matching circuit connected to low and high impedance loads such
as HTS antenna and CMOS device. Based on the design method,
we designed a Chebyshev type impedance matching circuit
connecting with slot antenna and CMOS-LNA at 10 GHz center
frequency. More over, in order to increase the antenna directivity,
we designed 2-dimensional antenna array by folding the slot
antenna.
loss in the passband of the matching circuit. CMOS-LNA was
designed and its noise figure and input and output impedance
were obtained by HSPICE simulation The circuit simulator and
electromagnetic field simulator studies provide the expected
performances of the slot antenna and CMOS-LNA with the
impedance matching circuit designed with the present method.
Moreover, in order to increase the antenna directivity, we
designed 2-dimensional antenna array by folding the slot
antenna.
The prototype miniaturized practical device, which integrates
the slot antenna and the CPW matching circuit within 15 mm x 6
mm dimensions, was fabricated by a YBCO thin film on a MgO
substrate and it performance was confirmed by the cryogenic
experiment around 10GHz.
Index Terms—Broadband impedance matching circuit, HTS
slot antenna, CMOS low noise amplifier, Coplanar waveguide
II. DESIGN OF BROADBAND IMPEDANCE MATCHING CIRCUIT
I. INTRODUCTION
T
HERE are many reports on High Tc superconducting (HTS)
bandpass filter (BPF) [1]-[3] and HTS BPF based
cryogenic receiver front-ends [4], [5], because the remarkable
demands of data transmissions, such as wireless LAN,
bluetooth, IMT-2000 and satellite telecommunications. For
active devices, there are great expectations of RF-CMOS
devices such as low noise amplifier (LNA) [6]. Although the
lumped element such as the spiral inductor and MIM capacitor
are adopted for matching circuit, it cannot be used at high
frequency range because of the self-resonance and stray
impedances. On the other hand, distributed element made of
transmission line is particularly effective because its size
becomes smaller, as the frequency is higher. Coplanar
waveguide (CPW) is easy to be connected the CMOS chip
because the signal line and ground plane exist on the same side
[7]. In our previous paper [8], we proposed a new design
method for the broadband impedance matching circuit for the
small antenna. In this paper, we generalize the design method to
the matching circuit connecting not only the slot antenna but
also with the CMOS-LNA. By obtaining the radiation resistance
and the antenna reactance, and input impedance of the
CMOS-LNA, we can design the fractional bandwidth and return
Manuscript received August 5, 2002.
H. Kanaya, Y. Koga, G. Urakawa, and K. Yoshida are with Department of
Electronics, Graduate School of Information Science and Electrical
Engineering, Kyushu University, Fukuoka 812-8581, (phone: +81-92-6423917; fax: +81-92-642-3943; e-mail: kanaya@ ed.kyushu-u.ac.jp).
Figure 1 shows the circuit model of n-pole broadband
matching circuit with the antenna and LNA, where antenna
impedance and load impedance of the LNA are Za=Ra+jXa and
ZL=RL+jXL, respectively. This theory is based on the
conventional design theory for the BPF by using the opened
resonators connected with J inverters (Ji, i+1) [9]. At first, we
propose the method of conjugate matching. Since LNA has
large input impedance, in general, we insert the quarter
wavelength transmission line, which has length (), electrical
length () and characteristic impedance (Z0), in order to make
impedance inversion.
Antenna
Za
Z a  Ra  jX a
J’0,1
(a)
jB1
J’1,2
jB2
J2,3

Zin
Jn-2,n-1
jBn-1
J’n-1,n
jBn
J’n,n+1
Z L  RL  jX L

 
4
, Z0
LNA
ZL
Zout
series resonator
(b)
Z’L
-jX’L
jX
reactance
compensation circuit
Z 02
 RL'  jX L
ZL
Fig. 1. Circuit model of n-pole matching circuit with antenna and LNA.
When  is around /4, it can be easily shown that the input
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impedance Z’L seen from the left of the transmission line is
approximately given by,
Z2
Z' L  jX '  0
ZL
,
(1)
X '  X  0 L ,
(2)
where X’=-Z0cot, and X and x are the reactance of /4 line and
reactance slope parameter of the series resonance circuit at =
0. As shown in (1), ZL is inverted as,
Z 02
Z 2R
Z2X
 2 0 L 2  j 2 0 L 2  R' L  jX L
Z L RL  X L
RL  X L
.
III. RESULTS OF THE BROADBAND MATCHING CIRCUIT
A. Design of Antenna and CMOS-LNA
Figure 3 shows the pattern of the slot antenna, and schematic
and chip layout of the CMOS-LNA (gate length =0.35m).
Radiation resistance of the antenna is calculated by using
EM-simulator (Momentum: Agilent) and which has Ra=5 at
10GHz. The maximum stable power gain (MSG) and ZL is
simulated by the HSPICE (Avanti!). Figure 4 shows the
Z
frequency adependence
of the MSG. AtJ’10GHz, MSG=8dB
and
J’0, 1
, Z0 ZL
n,n+1
ZL=1.00-j0.925 (K).
(3)


 
4
In order to compensate the jX’L (see Fig.1(b)), we adjust the
inverter length to =/4+ as,
  
Z 02 X L
X 'L

0 L  L R 2  X 2
0
L
L


,
where L is the inductance per unit length of the transmission
line.
In the case of noise matching, it is easy to replace ZL with
Z*opt, where Zopt=Ropt+jXopt is the impedance which minimize
the noise figure [10].
Finally, J inverters are given by,
LNA
CPW
Interdigital
gap
Slot Antenna
Fig. 2. CPW layout of matching circuit of antenna and LNA section.
b1
,
Ra g1
 w
J1,2
b'1 b2
,
g1 g 2
J i -1,i  w
bi -1bi
g i -1 g i
J ' n-1,n  w
J ' n ,n 1  w
bn-1b' n
,
g n-1 g n
b' n
,
RL g n
(a)
W=400m , L=5878m
i  3,4,  , n - 1 ,
(b)
RF_in
RF_out
(5)
b1
b1 
,
wxa
1
Ra g1
bn
,
wx
1
RL g n
where xa is the reactance slope parameter at the series resonance
of the antenna impedance (see [8]), and bi is the susceptance
slop parameter of the /2 resonator which has susceptance Bi.
The values of gi and w are normalized filter elements and
fractional bandwidth, respectively. Substituting x of /4 line and
R’L into b’n, we can design the matching circuit with high
impedance element. Figure 2 shows the CPW layout of
broadband matching circuit connecting with slot antenna and
LNA, where J-inverters are realized by the interdigital gaps.
For the size reduction, we adopt the mender line structure.
RF_in
RF_out
10m
Fig. 3. Pattern of the slot antenna (a), and schematic and chip layout of CMOS
LNA (b).
106
104
MSG (dB)
  w
J 0,1
b' n 
Meander line
(4)
102
1 -3
10
10-2
10-1
100
Frequency (GHz)
101
102
Fig. 4. Maximum stable power gain (MSG) of LNA.
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B. Simulation results of the impedance matching circuit
Figure 5 shows the frequency dependence of the input
impedance Zin seen from the left of the inverter J’0,1 and Zout seen
from the LNA towards antenna (see Fig. 1(a)), respectively. Rin
and Xin are almost matched to Ra (5), and also Rout and Xout are
2
almost matched
to Z*L (=1.00+j0.925 (K)) in 20
the center
Re[Zin]
frequency =10GHz
and w=70MHz.
Im[Zin]
G
Re[Zout]
Im[Zout]
15
10
5
0
Zout 
Zin (K)
1



Figure 7 shows the spatial distribution of the magnitude of the
electric field in the slot array antenna. It is considered that the
folded slot antenna acts as a magnetic-current dipole antenna
array. Figure 8 shows the radiation patterns of the slot antenna.
Figure 9 shows the folding number dependence of directivity of
the slot array antenna. EM-simulation results agree with the
theoretical value calculated form (5) and (6).
0
-5
w
-1
9.8
9.9
-10
10.2
10
10.1
Frequency (GHz)
Fig. 5. Frequency dependences of the Zin and Zout.
Fig. 7. Spatial distribution of the magnitude of the electrical field
in the slot array antenna.
IV. SIMULATION OF THE SLOT ARRAY ANTENNA
In order to increase the directivity of the antenna, we
designed 2-dimensional antenna array by folding the slot
antenna. Figure 6 shows the layout of the slot array antenna and
definition of the axis for calculating directivity. N is the folding
number of the slot antenna. Since the spatial distribution of the
magnitude of the electric field of N=1 antenna is similar to that
of one wavelength magnetic-current dipole antenna, the
directivity Gd is given by,
Gd , 
E ,
2

1 2
2
,
d E , sin  d
0
4  0
cos cos   1 sin Nkd cos  sin  2
E , 

sin 
sin kd cos  sin  2
(5)
,
Fig. 8. Radiation pattern of the slot antenna (N=folding number).
(6)
z
where d is an interval
of the dipole antenna and k=2/
z
P(R,,)
N=6


x



l
y

y


d


22×15 mm
x


Fig. 6. Definition of the axis for calculating directivity.
V. EXPERIMENTAL RESULT
Figure 10 shows the size of the prototype slot antenna
connecting with 50 matching circuit. In the figure, the size of
the interdigital gaps and meanderline resonators are also
described. This device was fabricated by the wet etching
process and was placed in a vacuum chamber with refrigerator
cooling system. By vector network analyzer (HP-8722C: HP),
we measured S-parameter by using coplanar waveguide probes.
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Figure 11 shows the frequency responses of the n=3 YBCO
matching circuit at 28K. In the figure, simulation results are also
plotted. The observed center frequency and fractional
bandwidth are similar to that of the simulation results. However,
because of the over-etching and the residual loss from the
16
connection
of the probe, pole frequencies and the base line are
not in full agreementEM-simulation
with simulation results.
-10
-20
Theoretical value
14
Directivity (dBi)
antenna. 0The prototype YBCO slot antenna with matching
circuit (f0=10GHz, w=70MHz and n=3) is also fabricated and
tested in the cryogenic temperature.
-30
12
Experimental result
Circuit model
10
-40
9.6
10
10.2
10.4
Frequency (GHz)
Fig. 11. Experimental results of YBCO slot antenna with n=3 matching
circuit at 28K.
8
6
9.8
0
2
4
6
Folding number (N)
8
10
Fig. 9. Folding number dependence of directivity of the slot array antenna.
L
W
L4
L3
G34
G23
G12
L2
ACKNOWLEDGMENT
The VLSI chip in this study is designed with Cadence and
Avant! CAD tools through the chip fabrication program of
VLSI Design and Education Center (VDEC), the University of
Tokyo. This work was partly in collaboration with Innovation
Plaza Fukuoka, Japan Science and Technology Corporation
(JST).
L1
G01
◆ Length of Resonators
L1=5878m , L2=6069m
L3=4581m , L4=5256m
W=400m , L=5878m
Ra=5.00 , xa=157
REFERENCES
◆
x
[1]
Interdigital gap
x’
x
x
[2]
x
Gi,i+1
x’=6.5m , x=5m
G01=232m, G12=10m
G23=18m, G34=992m
Fig. 10. Mask pattern of the YBCO slot antenna with n=3 matching circuit.
[3]
Size : 6mm×15 mm
[4]
[5]
[6]
[7]
VI. CONCLUSION
A superconducting slot antenna and a Si-CMOS-LNA
combined with a broadband matching circuit composed of CPW
meanderline resonators has been designed and tested. We can
design broadband impedance matching circuit connected to low
and high impedance loads such as HTS antenna and CMOS
device. Moreover, in order to increase the directivity, we
designed 2-dimensional antenna array by folding the slot
[8]
[9]
G. Tsuzuki, M. Suzuki, and N. Sakakibara, “Superconducting filter for
IMT-2000 band,” IEEE. Trans. Microwave Theory Tech., vol. 48, pp.
2519-2525, December 2000.
H. Fuke, Y. Terashima, H. Kayano, M. Yamazaki, F. Aiga and K. Kato,
“Tuning Properties of 2GHz Superconducting Microstrip-line Filters,”
IEEE Trans. Appl. Supercond., vol. 11, pp. 434-437. March 2001.
H. Kanaya, T. Shinto, K. Yoshida, T. Uchiyama, and Z. Wang,
“Miniaturized HTS Coplanar Waveguide Bandpass Filters with Highly
Packed Meanderlines,” IEEE Trans. Appl. Supercond., vol. 11, pp.
481-484. March 2001.
K. Satoh, T. Mimura, S. Narahashi, and T. Nojima, “Today and
Tomorrow of HTS Technology Applications,” MWE Microwave
Workshop Digest, pp.102-17, 2000.
W. Hattori, T. Yoshitake, and K. Takahashi, “An HTS 21-Pole
Microstrip Filter for IMT-2000 Base Stations With Steep Attenuation,”
IEEE Trans. Appl. Supercond., vol. 11, pp. 4091-4094. Sept. 2001.
A. Matsuzawa, “RF-SoC-Expectations and Required Conditions,” IEEE.
Trans. Microwave Theory Tech., vol. 50, pp. 245-253, January 2002.
M. Ono, N. Suematsu, S. Kubo, K. Nakajima, Y. Iyama, T. Takagi, and
O. Ishida, “Si Substrate Resistively Design for On-Chip Matching Circuit
Based on Electro-Magnetic Simulation,” IEICE Trans. Electron., vol.
E84-C, pp. 923-929, July 2001.
K. Yoshida, T. Takahashi, H. Kanaya, T. Uchiyama, and Z. Wang,
“Superconducting slot antenna with broadband impedance matching
circuit,” IEEE Trans. Appl. Supercond., vol. 11, pp. 103-106. March
2001.
G. Matthaei, L. Young, and E. Jones, Microwave Filters, ImpedanceMatching Networks, and Coupling Structures. New York: McGraw-Hill,
1964, pp. 427-440.
765
[10] K. B. Niclas, “Noise in Broad-Band GaAs MESFET Amplifiers with
Parallel Feedback” IEEE. Trans. Microwave Theory Tech., vol. 30, pp.
63-70, January 1982.
[11] C. A. Balanis, Antenna Theory: Analsis and Design, 2nd ed. New York:
John Wiley & Suns, Inc., 1997, ch. 6.
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