8042
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KB controller ------------8742/8741 programming scheme: 1. 8742 STRUCTURE DATA MEMORY MAP 127 ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ ｳ ｳ ｳ 8742 RAM ｳ ｳ ｳ 64 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ 8741 RAM ｳ 32 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ Bank 1 ｳ ｳ R7 ｳ ｳ .. ｳ ｳ R1 ｳ ｳ R0 ｳ 24 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ 8 level ｳ ｳ STACK ｳ 8 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ Bank 0 ｳ ｳ R7 ｳ ｳ .. ｳ ｳ R1 ｳ ｳ R0 ｳ 0 ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ PROGRAM MEMORY MAP 2047 ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ 8042 ｳ ｳ Page 7 8742 ｳ 8742 ROM ｳ ｳ ｳ ｳ ｳ Page 4 ﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄ 1024 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ ｳ ｳ Page 3 8041A ｳ 8741 ROM ｳ ｳ 8741A ｳ ｳ Page 1 & 256 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ﾄﾄﾄﾄﾄﾄ 8042 ｳ ｳ ｳ 8742 ｳ ｳ ｳ ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ 7 ｳ TIMER INT. ｳ ｳ ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ ｳ Page 0 ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ 3 ｳ IBF INT. ｳ ｳ ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ ｳ ｳ ｳ ﾃﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｴ ｳ 0ｳ RESET ｳ ｳ ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ ﾄﾄﾄﾄﾄﾄ (1) PC - Program Counter Stack 10-bit counter starting from data memory address 8 to low nibble of address 9. (2) PSW - Program Status Word 8-bit register used to store general information about program execution. bit 0 - 2 : Stack Pointer Bits S0, S1, S2 bit 3 : Not used bit 4 : Working Register Bank bit 5 : User flag(F0) bit 6 : Auxiliary Carry(AC) bit 7 : Carry(CY) (3) Location 0 - Reset vector Following a RESET* input to the processor, the next instruction is automatically fetched from location 0. (4) Location 3 - IBF inerrupt vector An interrupt generated by an Input Buffer Full(IBF) condition (with EN I instruction) causes the next instruction to be fetched from location 3. (5) Location 7 - Timer interrupt vector A timer overflow interrupt(with EN TCNTI instruction) will cause the next instruction to be fetched from location 7. (6) Instruction Cycle 1/(X MHz/15) = Y microseconds (7) Timer - 1/[X MHz/(15*32)] = Z microseconds The STRT T instruction enable the counter. The STOP T instruction disable the counter. 2. 8741/8742 FEATURE (1) 8-bit CPU (2) 8-bit data bus interface registers (3) 1K(2K) by 8 bit EPROM for 8741/8742 (4) 64(128) by 8 bit RAM memory for 8741/8742 (5) Interval timer/event counter (6) Two 8-bit TTL compatible I/O ports (7) Resident clock oscillator (8) 12M Hz operation for 8041AH, 8742, 8042 3. DBBOUT, DBBIN and STATUS registers (1) DBBOUT - Data Bus Buffer OUTput The host processor(system) may read data from DBBOUT. (2) DBBIN - Data Bus Buffer INput The host processor(system) may write command or data to DBBIN. (3) STATUS The status of DBBOUT, DBBIN and user_defined status is provided in the STATUS. This SPECIFICATION of 8042/8041 include 1. PORT definition 2. COMMAND 3. Timing of TRANSMITTING(error conditions included) 4. Timing of RECEIVING(error conditions included) 5. Timing of RECEIVE XT KB data The DETAILS of the above PORT DEFINITION ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ ｳ Port 60h Input/Output Buffer for Keyboard and Auxiliary Device ｳ ｳ (8042 only) ｳ ｳ ｳ ｳ * The output buffer is an 8-bit READ ONLY register at Port 60h. ｳ ｳ When the output buffer is read, the 8042 uses it to send informa- ｳ ｳ tion to the system microprocessor. ｳ ｳ THE INFORMATION CAN BE SCAN CODES RECEIVED FROM KEYBOARD, DATA ｳ ｳ FROM AN AUXILIARY DEVICE, or DATA BYTES THAT RESULT FROM A COMMAND ｳ ｳ FROM THE SYSTEM MICROPROCESSOR. ｳ ｳ ｳ ｳ * The input buffer is an 8-bit WRITE ONLY register at Port 60h. ｳ ｳ When the input buffer is written, a flag is set that indicates a ｳ ｳ data write.DATA WRITTEN TO PORT 60H IS SENT TO THE KEYBOARD UNLESS ｳ ｳ THE 8042 IS EXPECTING A DATA BYTE FOLLOWING A 8042 COMMAND. Data ｳ ｳ should be written to the 8042 input buffer only if the input ｳ ｳ buffer full bit (bit 1) of Status Port 64h = 0. ｳ ｳ ｳ ｳ Port 64h 8042 Command Port (WRITE) ｳ ｳ ｳ ｳ * 8042 commands written through port 64h : ｳ ｳ ｳ ｳ # common command ｳ ｳ @ 8041 command ｳ ｳ 8042 command ｳ ｳ ｳ ｳ . 21-3F read 8042 RAM ｳ ｳ # . 20 read 8042 command byte ｳ ｳ . 61-7F write 8042 RAM ｳ ｳ # . 60 write 8042 command byte ｳ ｳ . A4 test password installed ｳ ｳ . A5 load security ｳ ｳ . A6 enable security ｳ ｳ . A7 disable auxiliary device interface ｳ ｳ . A8 enable auxiliary device interface ｳ ｳ . A9 interface test for auxiliary device 'clock' ｳ ｳ and 'data' line ｳ ｳ # . AA self test ｳ ｳ # . AB interface test for keyboard 'clock'& 'data' line ｳ ｳ @ . AC diagonstic dump ｳ ｳ . AC reserved ｳ ｳ # . AD disable keyboard interface ｳ ｳ # . AE enable keyboard interface ｳ ｳ # . C0 read input port ｳ ｳ ｳ . C1 poll input port low - port 1 bit 0-3, in status bits 4-7 ｳ ｳ ｳ . C2 poll input port low - port 1 bit 4-7, ｳ ｳ in status bits 4-7 ｳ ｳ . C3 light panel LED ｳ ｳ # . D0 read output port ｳ ｳ # . D1 write output port ｳ ｳ NOTE: Bit 0 of output port is connected to ｳ ｳ system reset. This bit should not be ｳ ｳ written low ｳ ｳ . D2 write keyboard output buffer ｳ ｳ . D3 write auxiliary device output buffer ｳ ｳ . D4 write auxiliary device ｳ ｳ # . E0 read test inputs ｳ ｳ # . F0-FF pulse output port ｳ ｳ ｳ ｳ Note: ｳ ｳ (1) Definitions of the command byte (for command 20h & 60h): ｳ ｳ Bit For 8042 | For 8041 ｳ ｳ ------------------------------------+---------------------------ｳ ｳ 7 Reserved = 0 | the same as 8042 ｳ ｳ | ｳ ｳ 6 IBM translate mode | the same as 8042 ｳ ｳ = 1, 8042 translates the | ｳ ｳ incoming scan code to scan | ｳ ｳ code set 1. | ｳ ｳ = 0, 8042 passes the | ｳ ｳ keyboard scan codes | ｳ ｳ without translation. | ｳ ｳ | ｳ ｳ 5 Disable auxiliary device | IBM PC mode ｳ ｳ interface | = 1, PC keyboard interface ｳ ｳ = 1, disable | = 0, PC/AT keyboard ｳ ｳ = 0, enable | interface ｳ ｳ | ｳ ｳ 4 Disable keyboard | the same as 8042 ｳ ｳ interface | ｳ ｳ = 1, disable | ｳ ｳ = 0, enable | ｳ ｳ | ｳ ｳ 3 Reserved = 0 | Disable inhibit switch ｳ ｳ | = 1, disable ｳ ｳ | = 0, enable ｳ ｳ | ｳ ｳ 2 System flag | the same as 8042 ｳ ｳ | ｳ ｳ 1 Enable auxiliary interrupt | Reserved = 0 ｳ ｳ = 1, enable | ｳ ｳ | ｳ ｳ ｳ ｳ 0 Enable keyboard interrupt = 1, enable | the same as 8042 | ｳ ｳ ｳ ｳ (2) An interrupt occurs if the interrupt is enabled in the ｳ ｳ command byte. ｳ ｳ ｳ ｳ (3) Enable inhibit switch causes the KEY LOCK funtion to fail. ｳ ｳ ｳ ｳ ｳ ｳ Port 64h 8042 Status Port (READ) ｳ ｳ ｳ ｳ Bit For 8042 | For 8041 ｳ ｳ ----------------------------------+--------------------------ｳ ｳ 7 Parity error | the same as 8042 ｳ ｳ 6 General time out | Receive time out ｳ ｳ 5 Auxiliary output buffer full | Transmit time out ｳ ｳ 4 Inhibit switch | the same as 8042 ｳ ｳ 3 Command/data | " ｳ ｳ 2 System flag | " ｳ ｳ 1 Input buffer full | " ｳ ｳ 0 Output buffer full | " ｳ ｳ ----------------------------------+--------------------------ｳ ｳ ｳ ｳ * PROGRAMMING CONSIDERATION ｳ ｳ ｳ ｳ . port 64h (status register) can be read at any time ｳ ｳ . port 60h should be READ ONLY when the output buffer full ｳ ｳ bit in the status register is a 1 ｳ ｳ . the auxiliary output buffer full bit in the status register ｳ ｳ indicates that the data in port 60h came from the auxiliary ｳ ｳ device. this bit is VALID ONLY when the output buffer full ｳ ｳ bit is a 1 ｳ ｳ . port 60h and 64h should be written only when the status register ｳ ｳ input buffer full bit is 0 ｳ ｳ . the devices connected to the 8042 should be disabled before ｳ ｳ initiating a command that generates output. if output is ｳ ｳ generated, any value in the output buffer is overwritten ｳ ｳ . an external latch is used to hold the level sensitive IRQ until ｳ ｳ an I/O read from address 60h is executed by the system ｳ ｳ ｳ ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ COMMAND ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ ｳ#20 read 8042 command byte ｳ ｳ Read command byte and put it into output buffer. ｳ ｳ ｳ ｳ 21-3F read 8042 RAM ｳ ｳ Read 8042 RAM address 21h to 3fh and put it into ｳ ｳ output buffer. ｳ ｳ ｳ ｳ#60 write 8042 command byte ｳ ｳ The next byte written to port 60h will update the command ｳ ｳ byte. ｳ ｳ ｳ ｳ 61-7F write 8042 RAM ｳ ｳ The next byte written to port 60h will update content of ｳ ｳ 8042 RAM address 21h to 3fh accordingly. ｳ ｳ ｳ ｳ A4 test password installed ｳ ｳ Test if there is a password installed in the 8042 RAM, ｳ ｳ if installed, place FAh into output buffer, else ｳ ｳ place F1h into output buffer. ｳ ｳ ｳ ｳ A5 load security ｳ ｳ Load password into 8042 RAM, the password must be written ｳ ｳ to port 60h in scan code set 1 format, and will be ｳ ｳ terminated until a null(0) is written to port 60h. ｳ ｳ ｳ ｳ A6 enable security ｳ ｳ Enable the 8042 security feature, this command is VALID ｳ ｳ ONLY when a password is currently stored in 8042 RAM. ｳ ｳ When the security is enabled, the status byte(64h) bit 4 ｳ ｳ (inhibit switch) will become 0. ｳ ｳ ｳ ｳ A7 disable auxiliary device interface ｳ ｳ Set bit 5 of the 8042 command byte, this disable the ｳ ｳ auxiliary device interface by driving the CLOCK line low, ｳ ｳ data is not sent(received) to(from) auxiliary device. ｳ ｳ ｳ ｳ A8 enable auxiliary device interface ｳ ｳ Clear bit 5 of the 8042 command byte, this release the ｳ ｳ auxiliary device interface. ｳ ｳ ｳ ｳ A9 interface test ｳ ｳ Test auxiliary device clock and data line, and place test ｳ ｳ result in output buffer. ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ#AA ｳ ｳ ｳ ｳ#AB ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ@AC ｳ ｳ ｳ ｳ ｳ ｳ AC ｳ ｳ#AD ｳ ｳ ｳ ｳ ｳ#AE ｳ ｳ ｳ ｳ#C0 ｳ ｳ ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｺ Test Result Meaning ｺ ｺ ｺ ｺ 0 No error ｺ ｺ 1 AUX clock stuck low ｺ ｺ 2 AUX clock stuck high ｺ ｺ 3 AUX data stuck low ｺ ｺ 4 AUX data stuck high ｺ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ self test ｳ Perform 8042 internal diagnostic tests. 55h will be put ｳ into output buffer if no errors are detected. ｳ ｳ interface test ｳ Test KB clock and data line, and place test result in ｳ output buffer. ｳ ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｳ ｺ Test Result Meaning ｺ ｳ ｺ ｺ ｳ ｺ 0 No error ｺ ｳ ｺ 1 KB clock stuck low ｺ ｳ ｺ 2 KB clock stuck high ｺ ｳ ｺ 3 KB data stuck low ｺ ｳ ｺ 4 KB data stuck high ｺ ｳ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ ｳ ｳ diagonstic dump ｳ Send content of 8042 RAM address 0 to 0fh, ｳ current state of input port(P1), ｳ current state of output port(P2), ｳ 8041 program status word(PSW) to system sequentially. ｳ ｳ reserved ｳ ｳ disable keyboard interface ｳ Set bit 4 of the 8042 command byte, this disable the ｳ KB interface by driving the CLOCK line low, ｳ data is not sent(received) to(from) KB. ｳ ｳ enable keyboard interface ｳ Clear bit 4 of the 8042 command byte, this release the ｳ KB interface. ｳ ｳ read input port ｳ Read input port(P1), and place the data in output buffer. ｳ This command should be used ONLY IF the output buffer is ｳ ｳ ｳ ｳ EMPTY. NOTE: (1) 8042 input port(P1) definition: ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ C1 ｳ ｳ ｳ C2 ｳ ｳ ｳ C3 ｳ ｳ ｳ ｳ ｳ#D0 ｳ ｳ ｳ ｳ ｳ#D1 ｳ ｳ ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｺ Bit General Definition ｺ ｺ 7 Reserved ｺ 6 " ｺ ｺ 5 " ｺ ｺ 4 " ｺ ｺ 3 " ｺ ｺ 2 5V ｺ ｺ 1 PD data ｺ ｺ 0 KB data ｺ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ ｳ ｳ ｺ ｺ ｺ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ 8041 output port(P2) definition: ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｺ Bit General Definition ｺ ｺ ｺ 7 KEY LOCK -> 0:lock ｺ ｺ 6 Reserved ｺ ｺ 5 " ｺ ｺ 4 " ｺ ｺ 3 " ｺ ｺ 2 " ｺ ｺ 1 " ｺ ｺ 0 " ｺ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ * indicate conjugate of that signal ｳ ｳ ｳ ｺ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ poll input port low Place input port(P1) bits 0-3 in STATUS bits 4-7. ｳ ｳ ｳ poll input port high Place input port(P1) bits 4-7 in STATUS bits 4-7. ｳ ｳ ｳ light panel LED ｳ The next byte written to port 60h is defined as: ｳ set to high speed : data = 1 ｳ set to low speed : data = 0 ｳ ｳ read output port ｳ Read output port(P2), and place the data in output buffer.ｳ This command should be used ONLY IF the output buffer is ｳ EMPTY. ｳ ｳ write output port ｳ The next byte written to port 60h will be output to ｳ output port(P2). ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ ｳ D2 ｳ ｳ ｳ ｳ D3 ｳ ｳ ｳ ｳ D4 ｳ ｳ NOTE: (1) Bit 0 of output port is connected to system reset. This bit should not be written low ｳ ｳ ｳ ｳ (2) For AT model with PS2 mouse, i.e., 915V, 1100SX,ｳ ONLY bit 0 and 1 can be modified. ｳ ｳ (3) 8042 output port(P2) definition: ｳ ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｳ ｺ Bit General Definition ｺ ｳ ｺ ｺ ｺ 7 KB data* ｺ ｳ ｺ 6 KB clock* ｺ ｳ ｺ 5 IRQ 12 ｺ ｳ ｺ 4 IRQ 1 ｺ ｳ ｺ 3 PD data* ｺ ｳ ｺ 2 PD clock* ｺ ｳ ｺ 1 Gate A20 ｺ ｳ ｺ 0 Reset ｺ ｳ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ ｳ ｳ 8041 output port(P2) definition: ｳ ﾉﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｻ ｳ ｺ Bit General Definition ｺ ｳ ｺ ｺ ｺ 7 KB data ｺ ｳ ｺ 6 KB clock* ｺ ｳ ｺ 5 Reserved ｺ ｳ ｺ 4 IRQ 1 ｺ ｳ ｺ 3 Reserved ｺ ｳ ｺ 2 Reserved ｺ ｳ ｺ 1 Gate A20 ｺ ｳ ｺ 0 Reset ｺ ｳ ﾈﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍﾍｼ ｳ * indicate conjugate of that signal ｳ ｳ write keyboard output buffer ｳ The next byte written to port 60h is written to output ｳ buffer as if initiated by KB. ｳ ｳ write auxiliary device output buffer ｳ The next byte written to port 60h is written to output ｳ buffer as if initiated by PD. ｳ ｳ write auxiliary device ｳ The next byte written to port 60h is transmitted to PD. ｳ ｳ ｳ ｳ ｳ#E0 read test inputs ｳ ｳ Read T0 and T1, place in data bit 0 and 1 respectively, ｳ and place data byte in output buffer. ｳ ｳ ｳ ｳ#F0-FF pulse output port ｳ ｳ Bit 0 - 3 of the 8042 output port(P2) may be pulsed low ｳ ｳ for approximately 6 microseconds. ｳ ｳ Bit 0 - 3 of this command indicate which bits are to be ｳ ｳ pulsed. A 0 indicates that the bit should be pulsed, a 1 ｳ ｳ indicates that the bit should not be modified. ｳ ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ ｳ TIMING OF TRANSMITTING NOTE : The clock is provided by KB. The KB controller shall communicate with the AT KB using synchronous serial protocol. The following figure shows the function of each bit and timing. bit bit bit bit bit bit bit bit bit bit bit 10 9 8 7 6 5 4 3 2 1 0 ------------ stop (high) parity (odd) data bit7 (MSB) data bit6 data bit5 data bit4 data bit3 data bit2 data bit1 data bit0 (LSB) start (low) Figure 1-1 : function of each bit (code ED) ﾚﾄﾄﾄｿ ﾚﾄﾄﾄﾄﾄﾄﾄｿ ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ ﾚﾄﾄﾄﾄﾄﾄﾄﾄ data ﾄﾄﾄﾄﾄﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾚﾄﾄﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄ clock ﾄﾄﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ start 0 1 2 3 4 5 6 7 parity stop Figure 1-2 : Sending data to AT KB timing . If the AT KB does not start clocking the data out of KB controller within 15 milliseconds or complect that clocking within 2 milliseconds, the resend code(0feh) will be sent to system, and sets the transmit time-out bit in status byte. . The AT KB is resquired to response for all transmission data. If the AT KB doesn't complete to response data within 25 milliseconds, place hexFE in KB controller's output buffer, and sets the transmit time-out and receive time-out bits of status byte. . When the KB controller received the response data from the AT KB, and found the KB parrity error,a hexFE is placed in KB controller's output buffer, and parity error and transmit time-out bits of status byte will be set. The follwings are steps and notes of KB controller sending data to KB. . Set KB data and clock inactive, when KB controller start to communicate with AT KB. . Set KB clock active, then wait KB pull clock low within 15 ms. . Send data to KB from LSB to MSB synchronously during inactive period of clock(data bit 0 to data bit 7). Each bit(data bit 0 to data bit 7, parity bit and stop bit) must be complete sending within 0.3 ms. Else timer overflow. . Send parity bit with respect to ODD parity. . Pull KB data active, wait KB data transfer from low to high, then STOP CTNT, this end the transmission process. NOTE : (1) For 8742, all the transmit time-out or receive time-out in 8741 must be replaced by timeout error. (2) For 8742, the KB timing protocal is the same as 8741 KB. (3) For 8742, the auxiliary device timing protocal is similar to 8742 KB protocal. TIMING OF RECEIVING The following figure are AT keyboared synchronous serial protocol. (code AA) ﾄﾄｿ ﾚﾄﾄﾄｿ ﾚﾄﾄﾄｿ ﾚﾄﾄﾄｿ ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄ data ﾀﾄﾄﾄﾄﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾀﾄﾄﾄﾙ ﾄﾄﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄｿ ﾚﾄﾄﾄﾄﾄ clock ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ start 0 1 2 3 4 5 6 7 parity stop Figure 1-3 : AT keyboard timing . KB controller shall pull KB clock and data high when there is no data in DBBIN and DBBOUT and KB interface is enabled. . If KB controller cannot complect receiving KB data within 2 millisecond, a hexFF is placed in the DBBOUT, and set receive time-out bit of status byte. . If KB controller check the AT KB parity error occurs, then send a hexFE to KB, and wait for KB respond within 25 ms. . If the AT KB cannot complect response within 25 millisecond, a hexFE is placed in the DBBOUT, and set receive and transmit time-out bits of status byte. . If parity error occurs again, a hexFE is placed in the DBBOUT, and set parity error, receive time-out bits of status byte. The follwings are steps and notes of KB controller receiving data from KB. . Wait for KB clock change from high to low, then check if data is low; if it is, then continue, else ignore this noise. . Wait KB clock active, then receive the data bit 0 at the first falling edge of clock. . Receive data bit 1 to data bit 7 and parity bit at falling edge of the successive clock. . Check if there is parity error, if parity error, then set parity error flag. . If parity OK, then wait for falling edge of stop bit and STOP CTNT. . Inhibit KB(pull KB clock low), send data from KB to system. NOTE : The data from AT KB belong to scan KB controller must translate it to to command byte bit 6. Example: receive 0eh (make code) 0f0h ｿ 0eh ﾙ(break code) ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾙ scan code set 2 code set 2 format, scan code set 1 accoring -> send 29h to system -> 0a9h ﾀﾄﾄﾙ scan code set 1 RECEIVE XT KEYBOARD DATA The following figure are XT KB synchronous serial protocol. bit bit bit bit bit bit bit bit bit 8 7 6 5 4 3 2 1 0 ---------- data bit7 (MSB) data bit6 data bit5 data bit4 data bit3 data bit2 data bit1 data bit0 (LSB) start (high) Figure 1-4 : function of each bit (code 15) ﾚﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄｿ ﾚﾄﾄﾄﾄｿ ﾚﾄﾄﾄﾄｿ data ﾄﾄﾄﾄﾙ ﾀﾄﾄﾄﾄﾙ ﾀﾄﾄﾄﾄﾙ ﾀﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄﾄ ﾄﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿ ﾚﾄﾄｿﾚﾄﾄﾄ clock ﾀﾄﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾄﾙ ﾀﾙ start 0 1 2 3 4 5 6 7 Figure 1-5 : XT keyboard timing The follwing are steps and notes of KB controller receiving data from XT KB. . Receive XT KB data within 15 ms. . If timer overflow, then place hexFF in DBBOUT, and set receive time-out of status byte. . Wait KB clock inactive, then check if KB data is active. If it is inactive, then ignore this noise, else continue. . Receive start bit at the first rising edge of KB clock. . Receive data bit 0 to data bit 7 at rising edge of the successive clock. . Inhibit KB(pull KB data low), send data from KB to system. NOTE : (1) The data from XT KB belong to scan code set 1. (2) The reset KB command must pull KB clock low at least 12.5 ms, then pull KB clock high. (3) The KB controller places a hexEE in DBBOUT if system issues an echo(eeh) command to KB. (4) KB controller places a hexFA in DBBOUT for all the command to KB except RESET and ECHO.
