June 7-9, 2010 Hyatt Regency San Francisco Airport Hotel Burlingame, CA
http://www.ieee.org/conference/iitc
Editor Contacts:
Chris Burke or Garth Miller
BtB Marketing Communications
919.872.8172
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For Immediate Release
Tip Sheet For
2010 IEEE International Interconnect Technology Conference (IITC)
This Tip Sheet will provide an advance look at some of the papers to be given at
the 13th annual IITC, scheduled for June 7-9, 2010. The conference will begin with a
Short Course on Sunday, June 6, taught by experts in the field. Please contact us for
interviews with conference organizers, for images or for further information.
NOTE: See pages 5-7 for:
 Why 3D and interconnect technology is critical to electronics
 Definitions of technical terms
A) 3D Circuit Interconnections
3D circuits are stacks of chips or wafers that can offer powerful functionality in a
small package. IITC 2010 will feature numerous papers on 3D technology. Three
especially interesting papers describe impressive progress in 3D interconnect reliability
evaluation, materials and alignment technique. A fourth shows how 3D interconnects can
enable the heterogeneous integration of a sensor array and a signal processing CMOS IC.

Unperturbed Reliability: “Vias” are vertical holes filled with metal, used to
electrically and physically interconnect a chip’s various levels. Researchers are
trying to perfect through-silicon vias (TSVs), which pass completely through a
chip and connect it with other chips in the stack. But do TSVs embedded in ultrathin substrates influence the operation and reliability of adjacent transistors? In a
first, researchers from IMEC and KU Leuven explored the question. They used a
130-nm CMOS process technology to fabricate copper TSVs with 5.2-µm
diameters and 22-µm lengths. They placed them 1.1-µm away from NMOS and
PMOS transistors, singly and in groups, on either or both the source and drain
sides of the transistors, and in differing layouts. No performance degradation was
observed. Further, to determine whether stresses resulting from the thermal
mismatch between copper TSVs and silicon substrates had any impact, they
performed extensive thermal cycling. It turned out that while there was some
IITC 2010 Tip Sheet
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residual tensile stress, it had a negligible impact on carrier mobility. (Paper #9.4,
“Electrical Evaluation of 130-nm MOSFETs with TSV Proximity in 3D-SIC Structure,” Y.
Yang et al, IMEC and KU Leuven)

Low-Temperature TSV Barrier: Without a barrier layer, copper from a via
would diffuse into the silicon substrate and degrade transistors. Bonded 3D
circuits compound the problem because the high processing temperatures needed
to build TSV barrier layers can often damage the bond as well as the transistors.
Fujitsu researchers experimented with a relatively low-temperature plasmaenhanced chemical vapor deposition (PECVD) technique, in a series of wafer-onwafer experiments featuring damascene processing and 45-nm design rules.
Because a barrier layer’s thickness and density are both key to its performance
and reliability, the researchers built silicon-oxy-nitride (SiON) barrier films at
various densities and thicknesses, at processing temperatures as low as 150°C.
Their results showed no degradation in electrical characteristics or reliability.
(Paper #9.6, “Development of Low Temperature Dielectrics Down to 150°C for Multiple TSVs
Structure with Wafer-on-Wafer (WOW) Technology,” H. Kitada et al, Fujitsu/University of
Tokyo/Dai Nippon Printing/ATTO Co. Ltd.)

Practical Wafer Alignment: As circuit density increases, wafer-on-wafer
alignment accuracy becomes crucial. But the alignment techniques used in
laboratory settings aren’t necessarily practical for volume production. Sematech
researchers will describe a practical alignment scheme that achieved submicron
alignment accuracy for 300mm wafers. These were bonded face-to-face via
thermocompression bonding of the copper interconnects on each wafer. The
wafers were aligned using a first-of-its kind aligning/bonding tool which
researchers will describe at IITC. They also developed inspection techniques to
verify the integrity of the bonds and whether there were any voids. In particular,
in order to better observe specific bonding structures, they developed a prototype
integrated infrared high-speed focused ion beam (FIB) technique with CAD
overlay capabilities. While their work represents a practical approach to wafer
alignment for copper/copper thermocompression wafer bonding, they say
throughput needs to be improved before it can be declared truly productionworthy. (Paper #12.2, “Recent Advances in Submicron Alignment 300 mm Copper-Copper
Thermocompressive Face-to-Face Wafer-to-Wafer Bonding and Integrated Infrared, HighSpeed FIB Metrology,” W.H. Teh et al, SEMATECH/EV Group/FEI Co.)

3D Interconnects for Biosensor/CMOS IC Integration: Georgia Institute of
Technology researchers will describe two novel 3D interconnect technologies
useful for the integration of a large biosensor array with a signal-processing
CMOS IC. One is a TSV technology that can be used with relatively thick
substrates, such as those often needed for sensors. It enables the formation of a
seed layer in deep via holes and features a CMP-free planarization technique that
allows vias to be fabricated after the sensor is made, which allows maximum
material and process freedom for the sensor designers. The other technology is a
compliant interconnect architecture that allows low-force and low-resistance
temporary electrical contact between the sensor and the signal-processing IC. In
this way, should the sensor become contaminated by whatever it is measuring, it
can be removed and the CMOS IC can be reused. (Paper #2.2, “A 3D Interconnect
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System for Large Biosensor Array and CMOS Signal-Processing IC Integration,” H.S. Yang et
al, Georgia Institute of Technology)
B) Making Better Memories

Filling Gaps With Glass: Open spaces or gaps can occur during fabrication of
the interlayer dielectric (insulating layers) of a chip’s interconnect. If they’re not
filled with dielectric material, a contact bridge, or short circuit, between metal
lines could result. The problem is worsening as circuits get denser because the
gaps tend to have higher aspect ratios (they are taller and narrower) and are thus
harder to fill completely. Spin-on glass is used to fill gaps elsewhere on a chip,
and attempts have been made in post-curing to improve its gap-fill performance
for interconnects, but it hasn’t been effective to date. At IITC, Samsung
researchers will describe a technique they used with a 30-nm 1G DRAM memory.
First, they determined that the filling behavior of spin-on glass during spincoating is mainly dependent on the capillary effect. Then, they developed a
wettable surface treatment to enhance filling, and they optimized baking
temperatures to minimize the viscosity of the glass. They say these techniques
nearly eradicated the problem of contact bridges, and that spin-on glass may be
suitable for future memories. (Paper #10.1, “Robust Spin-on Glass Gap-fill Process
Technology for sub-30-nm Interlayer Dielectrics,” K-M. Byun et al, Samsung)

Double-Patterned Interconnect for Flash Memory: Photoresist patterning
starts to lose resolution at about 45-nm half-pitch, and the industry is moving
toward double-patterning (the use of physical spacers to create masks that can
double line densities) as a way to fabricate chips at smaller dimensions. It isn’t
restricted to interconnect applications, but is seen as promising for high-density
flash memory interconnects. IMEC and Applied Materials researchers will
describe a spacer-defined double-patterning approach incorporating 193-nm
immersion lithography. They used three masks to produce 20-nm half-pitch test
structures, including trenches for copper lines, in a silicon dioxide dielectric. The
team then successfully metalized them using an amorphous carbon layer and a
TiN metal hard mask. (Paper # 10.3, “Integration of 20-nm Half Pitch Single Damascene
Copper Trenches by Spacer- Defined Double Patterning (SDDP) on Metal Hard Mask
(MHM),” Y.K. Siew et al, IMEC and Applied Materials)
C) Advances in Core Interconnect Technology

Reduced Electromigration with Better Dielectric Reliability: At 45-nm and
smaller geometries, copper electromigration (EM) is a problem. A self-aligned
cobalt tungsten phosphide (CoWP) cap deposited on top of the interconnect
reduces EM, but unfortunately it also can degrade the reliability of the fragile,
porous ultra low-k dielectric which lies between the lines. IBM and Lam Research
conducted studies to determine whether this degradation can be prevented. Using
a CVD porous ultra-low-k dielectric (k=2.4) and 32-nm process technology on
300-mm wafers, they studied the dielectric’s conduction behavior and breakdown
characteristics under a wide range of temperatures and electric fields. They found
that adding a CoWP cap doesn’t change the dielectric’s fundamental leakage
IITC 2010 Tip Sheet
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conduction mechanism and kinetics, provided it is optimized. At IITC, they will
describe how they accomplished that, by selectively depositing the CoWP cap on
the copper but not on the low-k surface. (Paper # 7.3, “A Comparative Study of ULK
Conduction Mechanisms and TDDB Characteristics for Cu Interconnects with and without
CoWP Metal Cap at 32-nm Technology,” F. Chen et al, IBM and Lam Research Corp.)

Self-Forming Barriers Integrated with Extreme Low-K: The 28-nm
technology node and beyond will feature extremely low-k dielectrics. The
question is, can the barrier layer that isolates copper lines from the dielectric be
built in a self-forming fashion, so that both it and a copper seed layer can be
created simultaneously, thereby reducing fabrication complexity and creating very
thin layers? While self-forming layers have been investigated, TSMC researchers
performed exhaustive analyses of their interfaces and integration with low-k
dielectrics and capping layers. They looked at corrosion resistance, breakdown
voltage and electromigration lifetimes in various 28-nm, dual-damascene
structures with three extreme low-k dielectrics (k=2.2 to 2.8). They found selfformed barriers made from a CuMn alloy can indeed be integrated with extreme
low-k dielectrics effectively, but that doing so is complex and relies on the right
combination of dielectrics, interfaces and patterning approaches. (Paper # 3.3,
“Interface Effect on Mn-Containing Self-Formed Barrier Formation with Extreme Low-k
Dielectric Integration,” S-C. Pan et al, Taiwan Semiconductor Manufacturing Co.)

Hybrid Ti/TaN Barrier: Another approach is to fabricate hybrid barriers. Thin
barriers made from tantalum nitride (TaN) are in use now. However, 45-nm and
beyond technology will employ extremely low-k dielectrics, and TaN would
degrade their reliability because moisture from the dielectric will oxidize the
barrier, according to Panasonic and Renesas researchers. Meanwhile, titanium
(Ti) offers favorable interface properties with extreme low-k dielectrics, is
compatible with TaN and shows good wettability for copper. The researchers
investigated the interactions between Ti, TaN, low-k dielectrics and copper, and
found that a thin Ti/TaN multilayer barrier combining the materials’ desirable
properties can meet the needs of forthcoming technology generations. (Paper #13.4,
“Highly Reliable 45-nm-Half-Pitch Cu Interconnects Incorporating a Ti/TaN Multilayer
Barrier,” M. Hamada et al, Panasonic Corp. and Renesas Technology Corp.)
D) Other Noteworthy Developments

Interconnects For Graphene: Carbon-based materials like carbon nanotubes and
graphene nanoribbons have been viewed as contenders for the interconnects on
future ultra-high-density chips, because they have low resistivity and high
current-carrying properties. A team led by Fujitsu developed a multi-layer
graphene growth technology, using a photoemission-assisted plasma-enhanced
CVD technique, to grow networked nanographite wires on dielectrics without the
use of metal catalyst films. Their accomplishment is an initial step toward
building multilayer graphene interconnects. (Paper # 11.2, “Networked-Nanographite
Wire Grown on SiO2 Dielectric without Catalysts using Metal-Photoemission-Assisted PlasmaEnhanced CVD,” M. Sato et al, Fujitsu/Tohoku University/JASRI/CREST)
IITC 2010 Tip Sheet
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What is interconnect and why is it so important?
“Interconnect” is the wiring system that connects transistors and other
components on an integrated circuit, or computer chip. It may also refer to chip-topackage or chip-to-chip interconnections. Transistor speed used to be the limiting factor
for chip performance, but with today’s multi-million-transistor chips, the interconnect
itself has become a limiting factor. This is because the electrical resistance of the wires,
or lines, increases as they are made thinner to accommodate more transistors. It also
arises because capacitive coupling can occur among adjacent lines spaced very closely
together. Both inhibit the passage of signals.
The interconnect problem threatens to retard the development of chip technology,
which in turn threatens the progress of the electronics industry, one of the world’s largest.
IITC papers address this problem directly.
Copper lines offer less resistance and higher current-carrying capability than the
previously used aluminum lines, but at small geometries the standard silicon dioxide
insulator around the lines, called the dielectric, inhibits current flow. The search is on for
substitutes. A dielectric’s relative permittivity (i.e. its interaction with current flow) is
expressed as “k.” The lower the number, the faster the current flow. (Vacuum, the perfect
low permittivity material, has k=1; silicon dioxide has k~4.)
But dielectric materials with very low k-values are porous, fragile and absorb
moisture. They can be easily damaged by typical chip-making processes such as
exposure to harsh plasma during photoresist-stripping and to chemical-mechanical
polishing, used to planarize each interconnect layer.
The semiconductor industry has introduced 45/40nm and 32nm initial chips into
volume production. Many of these use non-porous, or dense, low-k dielectrics made
from carbon-doped oxide, or SiCOH, films (k~2.7-3.0). Next are chips at the 28nm
technology node expected to appear by 2010/2011, followed by 22nm technology chips
by 2012, assuming many technical challenges can be solved. 20nm and 15nm options are
also being discussed at this time. For these and future chips, porous low-k dielectrics may
be necessary, with k-values ranging from 2.5 to 2.0.
At the advanced technology nodes’ smaller dimensions, there is an increased
focus on new materials and processes to improve the reliability and manufacturability of
copper based interconnects. These include barrier, seed, copper filling, and capping
technologies.
3D Interconnects
The electronics industry continually strives to place more functions in the same
size or smaller packages. One way to do that is with 3D integrated circuits, where
individual chips are thinned (usually), stacked and then interconnected so they function
as a single unit. These stacks are challenging to fabricate, and despite much progress in
recent years the industry is still trying to determine the best ways to accomplish 3D
interconnect architecture.
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There are a variety of 3D techniques under consideration, but many of them
require the etching and filling of relatively large, deep holes through the backside of the
wafer, called through-silicon-vias, or TSVs. Processes such as deep etching, highly
conformal insulator deposition, and high-aspect-ratio metal fill are needed to create these
TSV structures. The demand for these types of applications warrants special
consideration in interconnect technology, and IITC has included this discussion in its
technical sessions.
Here are definitions of some technical terms used throughout this Tip Sheet:

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CMOS -- Most transistors today are FETs, or field-effect transistors. Most FETs
are built with CMOS manufacturing technology (complementary metal oxide
semiconductor).
CMP (chemical-mechanical planarization) -- The process of planarizing, or
making flat, the surface of an in-process wafer in preparation for the next
manufacturing step.
Electromigration -- A huge reliability problem. At tiny dimensions, copper tends
to physically move with current flowing through it, leading to gaps or outright
breaks in copper interconnect
Front-End/FEOL & Back-End/BEOL -- Transistors and other active devices
are built first on chips at the so-called “front end of the (manufacturing) line”
(FEOL), and the interconnect is built later on, at the “back end” of the
(manufacturing) line (BEOL).
Integrated Circuit -- A tiny electrical circuit built on a semiconducting substrate.
Low-k/Interconnect -- Interconnect refers to the copper lines that connect
devices on a chip. The tiny widths and close proximity of adjacent lines introduce
resistance and capacitance delays that can hinder chip performance. A low-k
dielectric is needed to insulate the copper lines, but these materials are fragile and
pose many challenges. The lower the “k” value, the better the insulating
properties.
Scaling/Integration -- Scaling is making circuitry such as transistors smaller so
that more will fit on a chip. Integration is combining more circuit elements on a
chip to add more functions at less cost.
Technology Generations/Nodes -- Each new generation of chip technology (or
“node”) is designated by half the distance (e.g. half the pitch) between the closest
adjacent printed lines it can produce. This is measured in nanometers (nm). Most
major semiconductor companies have introduced 90-nm chips and some have 65nm chips in volume production. The next generation, 45nm, has recently begun to
enter the marketplace.
How Interconnect Is Built-1. Horizontal trenches are etched into a thin film of insulating material on a
silicon substrate. Vertical holes called vias are patterned and etched as
well. The vias electrically connect copper lines in different layers.
2. The entire wafer, including the bottoms and sides of the trenches and vias,
is coated with a liner/barrier material and copper. Excess material is
removed via chemical-mechanical polishing (CMP), leaving the surface
flat.
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3. To finish a layer, an insulating capping material is deposited on top of the
copper lines. This surface then becomes the foundation for the next layer,
built in the same fashion.
4. Advanced chips contain six to 10 layers of copper lines, extending across
the chip in myriad pathways. Some lines carry electrical signals, others
conduct power.