EC 4102 : DIGITAL ELECTRONICS LABORATORY
LIST OF EXPERIMENTS:
COMPULSORY EXPERIMENTS:
1. Design and realization of Parity bit checker using IC 7486
2. Design and realization of 4:2 line encoder using IC 7432
3. Design and realization of 4-bit magnitude comparator using IC 7485
4. Assembling of a seven segment decoder using IC 7447 and IC 7404
5. Design and testing of SR and JK Flip-flop using IC 7400 & IC 7402
6. Design of a 2 bit binary parallel adder using IC CD4030 and IC CD4081
7. Design of an Astable Multivibrator (using IC 555 Timer) and observe the output
waveforms
8. Design of an Monostable Multivibrator (using IC 555 Timer) and observe the
output waveforms
9. Design and testing of 2 : 1 multiplexer and CMOS switch using IC CD4066
10. Design of a 4 bit serial in serial out shift register using IC CD4027 and 555 timer
11. Design of a Modulo-9 ripple counter using IC CD4029 and IC CD4091
12. Design of a Schmitt Trigger Circuit (using IC 741 OPAMP) & observation of the
output waveforms.
OPTIONAL EXPERIMENTS:
13.
i. Design and realization of Binary to Gray code converter using IC 7486
ii. Design and realization of Gray to Binary code converter using IC 7486
14. Design of an EX-OR gate using minimum number of 2 input NAND gates
IC7400
15. Design and realization of an odd parity generator using IC7486
16. Design of a 1 bit half substractor using IC CD4066
17. Design and realization of 4:16 Decoder using 1:4 De-multiplexer
18. Design of a modulo 256 ripple counter using IC7493
19. Design of a 4 : 16 line decoder using IC CD4514
20. Reading 8 specified address location of a programmed IC Intel 2716
21. Storing a nibble in an IC 2114 RAM and read it.
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORYORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A PARITY BIT CHECKER
USING IC 7486
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of Parity bit checker using IC 7486
APPARATUS REQUIRED:
1. Wish Board
2. D.C. Power supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENTS:
1. IC7486
2. Connecting Wires
3. LED with resistors
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7486
QUAD 2 INPUTS EX-OR GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON Power Supply, make sure that the connections are
correct.
3. Apply the input logic as per Truth Table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the output states.
5. Verify the result of truth ness.
6. Repeat steps from 3 to 5 for all possible combinations.
FUNCTION TABLE:
Sr. No
1
2
3
4
5
6
7
8
RESULT:
PRECAUTIONS:
INPUTS
PC
X
0
Y
0
Z
0
P
0
0
0
0
0
X
1
3
2
Y
9
10
8
12
Z
4
5
13
6
P
1
fig. PARITY CHECKER
11
O/P
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A 4:2 LINE ENCODER
USING IC-7432
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of 4:2 line encoder using IC 7432
APPARATUS REQUIRED:
1.
2.
Wish board
D.C. power supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1.
2.
3.
IC 7432
Connecting Wires
LED with resistors
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7432
QUAD 2 INPUTS OR GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power Supply, make sure that the connections are
correct.
3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the Output state.
5. Verify the result of truthness.
6. Repeat steps from 3 to 5 for all possible combination.
FUNCTION TABLE:
D0
D1
1
0
0
0
0
1
0
0
INPUT
D2
RESULT:
PRECAUTIONS:
0
0
1
0
OUTPUT
D3
0
0
0
1
X
Y
Not used
D0
D1
Y = D1+ D3
D2
X = D2 + D3
D3
Fig. 4:2 LINE ENCODER
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A 4-BIT MAGNITUDE
COMPARATOR USING IC-7485
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of 4-bit magnitude comparator using IC 7485
APPARATUS REQUIRED:
1. Wish board
2. D.C. power supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC7486
2. Connecting Wires
3. LED with resistors
PIN DIAGRAM:
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power Supply, make sure that the connection are
correct.
3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the Output state.
5. Verify the result of truthness.
6. Repeat steps from 3 to 5 for all possible combination.
FUNCTION TABLE:
Sl.
No.
1
2
3
4
5
A
B
A>B
A<B
A=B
A3
0
0
A2
1
1
A1
1
1
A0
1
0
B3
0
0
B2
0
1
B1
1
1
B0
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
6
7
RESULT:
PRECAUTIONS:
A3
B3
A2
B2
A<B
A1
B1
A>B
A0
B0
A=B
Fig. four bit magnitude comparator using IC 7485
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
ASSEMBLING OF A SEVEN SEGMENT DECODER
USING IC 7447 AND IC 7404
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design of a Seven-Segment display using IC-7447 & 7404
APPARATUS REQUIRED:
1. Wish Board
2. D.C. Power Supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC 7447 & IC 7404
2. Connecting Wires
3. Seven Segment display IC-LT543
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7404
HEX NOT GATE
Quad 2-in
puts NOR GATE
GPIN
DIAGRAM OF IC 7447
BCD TO 7 SEGMENT DISPLAY DRIVER
The appropriate outputs a-g become low to display the BCD (binary coded decimal) number supplied on
inputs A-D. The 7447 has open collector outputs a-g which can sink up to 40mA. The 7-segment display
segments must be connected between +Vs and the outputs with a resistor in series (330
with a 5V
supply). A common anode display is required.
Display test and blank input are active-low so they should be high for normal operation. When display
test is low all the display segments should light (showing number 8).
If the blank input is low the display will be blank when the count input is zero (0000). This can be used to
blank leading zeros when there are several display digits driven by a chain of counters. To achieve this
blank output should be connected to blank input of the next display down the chain (the next most
significant digit).
The 7447 is intended for BCD (binary coded decimal) which is input values 0 to 9 (0000 to 1001 in binary).
Inputs from 10 to 15 (1010 to 1111 in binary) will light odd display segments but will do no harm
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power supply, make sure that the connection are correct.
3. Apply the input logic state code mentioned in observation Table in terms of
+5 volts for state-1 and 0 volts for state-0.
4. Observe the output states.
5. Verify the displayed digit with decimal equivalent of applied input binary
code.
6. Repeat steps from 3 to 5 for all possible combination.
OBSERVATION TABLE:
Note: Show the combined output of seven-segment display in observation.
S.
No.
1
2
3
4
5
BINARY CODE
A3 A2 A1 A0
RESULT:
PRECAUTIONS:
a
b
c
d
e
f
g
Displayed
Digit
VCC
5V
U2
7
A
B
C
D
1
A
OA
2
B
OB
6
C
OC
D
OD
3
OE
5
LT OF
4
RBI OG
13
Com
U3
SEVEN_SEG_COM_K
12
11
10
9
A B CDE F G
15
14
BI/RBO
7447N
CIRCUIT DIAGRAM OF SEVEN SEGMENT DISPLAY USING IC 7447
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND TESTING OF SR AND JK FLIP-FLOP
USING IC 7400 & IC 7402
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and testing of SR and JK Flip-flop using IC 7400 & IC 7402
APPARATUS REQUIRED:
1. Wish board
2. D.C. power supply
Or
Trainer kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC7400, IC7402
2. Connecting wires
3. LED with resistor
PIN-DIAGRAM:
PIN DIAGRAM OF IC 7400
4 2-INPUTS NAND GATE
GPIN
DIAGRAM OF IC 7402
QUAD 2 INPUTS NOR GATE
7402
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power Supply, make sure that the connection are
correct.
3. Apply the input logic state as per Truth table / Function table in terms of +5
volts for state-1 and 0 volts for state-0.
4. Observe the output state.
5. Verify the result of truth ness.
6. Repeat steps from 3 to 5 for all possible combination.
FUNCTION TABLE:
(a) Testing of the Characteristic table of SR Flip-flop
Sr. No.
1
2
3
4
5
6
7
8
Present
state
Qn
0
0
0
0
1
1
1
1
S
R
Next State
Qn+1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q’n+1
(b) Testing of the Characteristic table of JK Flip-flop
Sr. No.
1
2
3
4
5
6
7
8
Present
state
Qn
0
0
0
0
1
1
1
1
RESULT:
PRECAUTIONS:
J
K
Next State
Qn+1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q’n+1
S
S
Q
Q
CLK
Q'
Q'
R
R
Fig-2 S-R Flip-Flop
Fig-1 S-R Latch
J
Q
CLK
J
Q
CLK
Q'
Q'
K
K
Fig.-3 J-K Flip-Flop
Fig.-4 J-K Flip-Flop
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A 2 BIT BINARY PARALLEL ADDER
USING IC CD4030 AND IC CD4081
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM:- Design of a 2-bit binary parallel full adder using IC CD4030 and IC CD4081.
APPARATUS REQUIRED:
1.
2.
3.
IC CD4030 & IC CD4081
MICROLABORATORY KIT
Connecting wires
PIN DIAGRAM
PIN DIAGRAM OF IC 4030
QUAD 2-INPUT EXOR GATE
I
PIN DIAGRAM OF IC 4081
QUAD 2-INPUT AND GATE
THEORY: A Full Adder is a combinational circuit that performs the sum of three
input bits Ai, Bi, and Ci. It consists of three inputs and two outputs. Ai, Bi are bits of 2 n
bit numbers and C represents the carry from the previous lower significant position. The
two output’s are Si (Sum) and Ci+1 (Carry).
A binary parallel adder is a digital function that produces the arithmetic
sum of two binary numbers in parallel. It consists of full adders connected in cascade,
with the output carry from one full adder connected to the input carry of the next full
adder.
PROCEDURE:
1. Connect the circuit a shown in fig.
2. Take all possible combination of two 2-bit numbers
OBSERVATION TABLE:
A2
A1
RESULT:
PRECAUTIONS:
B2
B1
S1
C2
S2
C3
B2 A2
B1 A1
C3
C2
C1
F.A.
F.A.
S2
S1
BLOCK DIAGRAM OF A 2 BIT BINARY PARALLEL FULL ADDER
X1
X2
2.5 V
1
A1
B1
3
2
5
4
6
4030BD
S1
2.5 V
1
A2
B2
3
2
5
4
6
4030BD
S2
4030BD
4030BD
X3
2.5 V
X4
1
2.5 V
5
3
2
4081BD
6
4081BD
1
2
4
C2
4081BD
5
3
6
4
4081BD
C1
(0)
Fig CIRCUIT DIAGRAM OF A 2 BIT BINARY PARALLEL FULL ADDER
C3
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF AN ASTABLE MULTIVIBRATOR
(USING IC 555 TIMER) AND OBSERVE THE OUTPUT
WAVEFORMS
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: - Design of an Astable Multivibrator (using IC 555 Timer) and observe the output
waveforms.
APPARATUS REQUIRED:
1. Wish board
2. D.C. Power Supply Or Trainer Kit.
3. C.R.O.
CIRCUIT COMPONENTS:
1.
2.
3.
4.
IC 555
Capacitor (0.01F)
Resistors
Connecting wires
PIN DIAGRAM OF THE 555 TIMER
GND
Trigger
output
Reset
+ Vcc
Discharge
IC 555
Threshold
Control voltage
Functions of pins:
1. Ground: All voltages are measured with respect to this terminal.
2. Trigger: It is the external input that will be applied to the inverting input of the lower
comparator & will be compared with Vcc/3 coming from the potential divider network.
3. Output: Complement of the output of the flip-flop acts as the final output of timer as it
passes through a power amplifier with inverter. Load can either be connected between pin
3 & ground or pin 3 & Vcc.
4. Reset : This is an input to the timing device which provides a mechanism to reset the
flip-flop in a manner which overrides the effect of any instruction coming to the FF from
lower comparator. This is effective when the reset input is less than 0.4V.When not used
it is returned to Vcc.
5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in
determining the timing interval. The control voltage at 5 can be used when it is required
to vary the time & also in such cases when the reference level at V- of the UC is other
than 2/3Vcc.
Generally when not used a capacitor of 0.01uF should be connected between 5 & ground
to bypass noise or ripple from the supply.
6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to
this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the
set input of FF thereby setting the FF making Q=1 & Q=0.
7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q
output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving
transistor into saturation.
When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any
external device connected to it.
8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.
THEORY:
PROCEDURE:
1. Connect the circuit diagram as shown in the circuit diagram.
2. Before switch ON the power supply, make sure that the connections are
correct.
3. Connect the C.R.O. probe at terminals 3 and ground.
4. Observe the output waveform for different RB.
5. Tabulate the reading of W and T in Observation Table.
6. Calculate Dm, Dt and % Error.
7. Plot the waveform observed at terminal no. 2 and 3.
OBSERVATION:
At VCC=5V/12V, RA=33 K
Sl
No
RB
(K)
1
2
30
60
W
(S)
RESULT:
PRECAUTION:
T
(S)
Measured Duty
Cycle
Dm=W/T X
100%
Theoretical Duty
Cycle
Dt=(RA+RB)/
(RA+2RB) X 100
% Error=
(Dt-Dm)/Dt
X 100
Vcc = 5V/12V
RA
33kohm
8
4
RST
RB
30-60Kohm
VCC
7
6
DIS
2
THR
OUT
3
Vout
555
TRI
TIMER
5
CON
GND
1
0.01uF
0.01uF
Fig. ASTABLE MULTIVIBRATOR USING TIMER 555
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF AN MONOSTABLE MULTIVIBRATOR
(USING IC 555 TIMER) AND OBSERVE THE OUTPUT
WAVEFORMS
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: - To design a Monostable Multivibrator using IC 555 and observe the output
waveform.
APPARATUS REQUIRED:
1.
2.
3.
4.
Wish board
D.C. Power supply
Function generator Or Trainer Kit
C.R.O
CIRCUIT COMPONENTS:
1.
2.
3.
4.
IC555
Capacitor (1000pF, 10000pF)
Resistors (10 to 30K variable)
Connecting wires
PIN DIAGRAM OF THE 555 TIMER
GND
Trigger
output
Reset
+ Vcc
Discharge
IC 555
Threshold
Control voltage
Functions of pins:
1. Ground: All voltages are measured with respect to this terminal.
2. Trigger: It is the external input that will be applied to the inverting input of the lower
comparator & will be compared with Vcc/3 coming from the potential divider network.
3. Output: Complement of the output of the flip-flop acts as the final output of timer as it
passes through a power amplifier with inverter. Load can either be connected between pin
3 & ground or pin 3 & Vcc.
4. Reset : This is an input to the timing device which provides a mechanism to reset the
flip-flop in a manner which overrides the effect of any instruction coming to the FF from
lower comparator. This is effective when the reset input is less than 0.4V.When not used
it is returned to Vcc.
5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in
determining the timing interval. The control voltage at 5 can be used when it is required
to vary the time & also in such cases when the reference level at V- of the UC is other
than 2/3Vcc.
Generally when not used a capacitor of 0.01uF should be connected between 5 & ground
to bypass noise or ripple from the supply.
6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to
this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the
set input of FF thereby setting the FF making Q=1 & Q=0.
7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q
output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving
transistor into saturation.
When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any
external device connected to it.
8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.
THEORY:
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
Connect the circuit diagram as shown in the circuit diagram.
Before switch ON Power Supply, make sure that the connections are correct.
Connect the C.R.O. probe at terminals 3 and ground.
Observe the output waveforms for different values of R.
Tabulate the reading of Pulse Width as Wo in observation table.
Calculate the Wt and % Error.
Plot the waveform observed at terminal no. 2, 3 and 6.
OBSERVATIONS:
At Vcc=10V, C=8.2nF
Sl
No.
1
2
3
R
(K)
30
40
50
RESULT:
PRECAUTION:
Wo
(S)
Theoretical Pulse Width
Wt=1.1 x Rx C
% Error=Wt-Wo X100
Wt
+Vcc
8
50%
4
RST
VCC
7
6
DIS
2
THR
OUT
3
Vout
TRI
C
8200pF
5
CON
GND
Trigger
C2
1
2200pF
Fig. MONOSTABLE MULTIVIBRATOR USING TIMER 555
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND TESTING OF 2 : 1 MULTIPLEXER
AND CMOS SWITCH USING IC CD4066
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and testing of CMOS switch and 2 : 1 multiplexer using IC CD4066
APPARATUS REQUIRED:
1.
2.
3.
IC CD4027 & IC 555 timer
MICROLABORATORY KIT
Connecting wires
PIN DIAGRAM OF IC 4066
QUAD 2 IN/OUTPUT DIGITAL AND ANALOG BILETERAL CMOS
SWITCH
THEORY:
IC CD4066 is bileteral CMOS Switch. It is the new class of logic circuits, which use the
TGs as their basic building blocks.
The TG consists of one NMOS and one PMOS transistor, connected in parallel. The gate
voltages applied to these two transistors are also set to be complementary signals. As
such, the CMOS TG operates as a bi-directional switch between the nodes A & B, which
is controlled by signal C.
C
A
B
C
A
GND
B A
TG
If the control signal C is at logic high (=VDD) then the PMOS & NMOS transistors are
turned ON and they provide a low resistance current path between A & B A
B
C=1
If the control signal C is low then both are off and there is no conduction path between A
& B.
A
B
C=0
Using the generalized MUX approach, each Boolean function can be realized with a TG
logic circuit.
The implementation of CMOS transmission gates in logic circuit design usually results in
compact circuit structure, which may even require a smaller number of transistors than
their standard CMOS counterparts.
2 * 1 MULTIPLEXER:
2 * 1 multiplexer having 2 input and 1 output. The two inputs of the multiplexer is A and
B. The data at a A or B is selected through control signal C, which acts as selection line
for it.
So output of the 2 * 1 multiplexer is F = AC + BC’
A
2*1
multiplexer
C
B
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switch ON the power supply, make sure that the connections are
correct.
3. Observe the A, C and output F. See Switching action of the CMOS Switch.
4. In Second of the fig observe A,B,C and output and verify F = AC + BC’
OBSERVATIONS:
(a) For CMOS switch
INPUT
Control
Signal
OUTPUT
A
C
F
0
1
1
0
0
1
1
1
(b) For 2 * 1 MULTIPLEXER
INPUT
RESULT:
PRECAUTIONS:
Control
signal
OUTPUT
F
A
B
C
0
0
1
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
A
C
U1
2
14
F
13
4
3
5
8
9
6
11
10
12
7
4066BD
Circuit for CMOS Bilateral Switch
A
C
B
1
14
U2
2
13
4
3
5
8
9
6
11
10
12
7
4066BD
Circuit for 1: 2 Multiplexer
F
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A 4 BIT SERIAL IN SERIAL OUT SHIFT REGISTER
USING IC CD4027 AND 555 TIMER
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM:- Design of a 4-bit serial in serial out shift register using IC CD4027 and 555
timer.
APPARATUS REQUIRED:
1.
2.
3.
IC CD4027 & IC 555 timer
MICROLABORATORY KIT
Connecting wires
THEORY:
Register:- A register is a group of binary storage cells suitable for holding binary
information. A group of flip-flop’s constitutes a register, since each flip-flop is a binary
cell capable of storing one bit of information so an n-bit register consists of n flip-flop’s
and is capable of storing any binary information containing n bits.
Shift Register:- A register capable of shifting its binary information either to the right or
to the left is called a Shift Register. Also we can feed data/information in shift register in
two manners –
1) Serial Input:- In this at a time only one bit of n bit information is feeded/loaded in
shift register firstly the least significant bit (leftmost bit) of the n-bit
information is loaded and at the end most significant bit is loaded. So
serial shift register needs n clock period (T) for feeding n bit data into
the register.
2) Parallel Input:- In this the whole n bits of a n-bit information is loaded into the
register in only one clock period (T). So all bits are loaded parallely.
Output also can be find from shift register in the same manner serially or parallely.
So we have 4 kindf of shift registers
1. Serial in Serial out
2. Serial in Parallel out
3. parallel in Serial out
4. parallel in parallel out
In serial in serial out, loading in and extracting out the data from shift register both
processes takes place in serial manner
PIN DIAGRAM OF THE 555 TIMER
GND
Trigger
output
Reset
+ Vcc
Discharge
IC 555
Threshold
Control voltage
Functions of pins:
1. Ground: All voltages are measured with respect to this terminal.
2. Trigger: It is the external input that will be applied to the inverting input of the lower
comparator & will be compared with Vcc/3 coming from the potential divider network.
3. Output: Complement of the output of the flip-flop acts as the final output of timer as it
passes through a power amplifier with inverter. Load can either be connected between pin
3 & ground or pin 3 & Vcc.
4. Reset : This is an input to the timing device which provides a mechanism to reset the
flip-flop in a manner which overrides the effect of any instruction coming to the FF from
lower comparator. This is effective when the reset input is less than 0.4V.When not used
it is returned to Vcc.
5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in
determining the timing interval. The control voltage at 5 can be used when it is required
to vary the time & also in such cases when the reference level at V- of the UC is other
than 2/3Vcc.
Generally when not used a capacitor of 0.01uF should be connected between 5 & ground
to bypass noise or ripple from the supply.
6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to
this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the
set input of FF thereby setting the FF making Q=1 & Q=0.
7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q
output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving
transistor into saturation.
When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any
external device connected to it.
8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.
PIN DIAGRAM OF IC 4027
2 adet JK FLIP FLOP
PROCEDURE:
1.
2.
3.
Connect the circuit as shown in fig.
Connect the output of the 555 timer output to clock 1 and clock 2 input of
all IC 4027B.
See the input and output waveform and observe the output.
RESULT:
PRECAUTIONS:
Q2
Q3
U5A
7
6
J1
Q1
1
3
J1
K1
1
~Q1
2
6
6
J1
Q1
K1
~Q1
4
2
1
CP1
5
5
K1
Q1
3
CP1
5
J1
1
3
CP1
4
CLOCK
Q1
3
5
SD1
SD1
6
CP1
7
7
SD1
Q0
U3A
U2A
7
SD1
Din
Q1
U1A
~Q1
4
CD1
CD1
CD1
4027BD
4027BD
4027BD
K1
2
~Q1
4
CD1
4027BD
2
O/P
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A MODULO-9 RIPPLE COUNTER USING IC
CD4029 AND IC CD4091
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: - Design of a Modulo 9-ripple counter using IC CD4029 and IC CD4091
.
APPARATUS REQUIRED:
1. Wish board
2. D.C. Power Supply Or Trainer Kit.
3. C.R.O.
CIRCUIT COMPONENTS:
1. IC CD4029, IC CD4091
2. Connecting wires
PIN DIAGRAM OF IC 4029 : IC 4029 Decade counter
4029 Ayarlanabilir synchronous yukari / asagi Counter
THEORY:
Modulo ‘n’ counter is a counters, which counts from 0000 to binary equivalent of ‘n’ and
then again start counting from 0000
(i.e. 0000 0001  ……. upto binary equivalent of ‘n’  0000  0001……. )
Modulo 9 ripple counter will start count from 0000 to 1001 than reset to 0000 after which
it again start counting from 0000 to 1001. This process repeated again and again.
To design of a Modulo 9 ripple counter using IC CD4029 (Decade counter) it has to be
reset to 0000 after counting 1001. This resetting after 1001 is done through a two input
AND gate. Input of AND gate is QA [least significant bit (LSB) of decade counter] and
QD [Most significant bit (MSB) of decade counter]. So only when output of the decade
counter IC 4029 will be 1001 then only the output of AND gate will be 1. Output of the
AND gate is connected to PRESET input of decade counter so decade counter will be
reset to 0000 and again start counting from 0000.
PROCEDURE:
5. Connect the circuit as shown in the circuit diagram.
6. Before switch ON the power supply, make sure that the connections are
correct.
7. Observe the Q1,Q2, Q3, Q4
8. Complete the observation table.
OBSERVATIONS:
S. No
RESULT:
PRECAUTION:
Q3
Q2
Q1
Q0
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A SCHMITT TRIGGER (USING IC 741 OPAMP)
OBSERVATION OF THE OUTPUT WAVEFORMS
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: - Design of a Schmitt Trigger Circuit (using IC 741 OPAMP) & observation of
the output waveforms.
APPARATUS REQUIRED:
4. Wish board
5. D.C. Power Supply Or Trainer Kit.
6. C.R.O.
CIRCUIT COMPONENTS:
3. IC741
4. Resistors ( 8.2K, 100)
5. Connecting wires
ABOUT IC 741:
The 741 is the godfather of all operational amplifiers (amplifiers on a chip).
Although most up-to-date designs beat it for speed, low noise, etc, it still works well as a
general purpose device. One of its advantages is that it is compensated (its frequency
response is tailored) to ensure that under most curcumstances it won't produce unwanted
spurious oscillations. This means it is easy to use, but the down-side of this is the poor
speed/gain performance compared to more modern op-amps.
The 741 is usually supplied in an 8-pin ‘DIL’ (Dual In Line) or ‘DIP’ (Dual Inline
Package, or sometimes Dual Inline Plastic) package with a pinout shown above. This has
proved so popular that many other competing op-amps have adoped the same
package/pinout. Hence for many applications the various op-amps are ‘drop in’
replacements or upgrades for one another. These days there is a large family of 741 type
devices, made by various manufacturers. Sometimes one manufacturer will make
different versions which work better than others in some respect. Each has a slightly
different part number, but it generally has “741” in it somewhere!
The values given below are ‘typical’ for an ordinary 741, better versions (more
expensive) may give better results...
Typical values of Basic Parameters:
Rail voltages : +/- 15V dc (+/- 5V min, +/- 18V max)
Input impedance: Around 2MegOhms
Low Frequency voltage gain: approx 200,000
Input bias current: 80nA
Slew rate: 0.5V per microsecond
Maximum output current: 20mA
Recommended output load: not less than 2kilOhms
Note that, due to the frequency compensation, the 741's voltage gain falls rapidly with
increasing signal frequency. Typically down to 1000 at 1kHz, 100 at 10kHz, and unity at
about 1MHz. To make this easy to remember we can say that the 741 has a gainbandwidth product of around one million (i.e. 1 MHz
THEORY:
PROCEDURE:
9. Connect the circuit as shown in the circuit diagram.
10. Before switch ON the power supply, make sure that the connections are
correct.
11. Select the sinusoidal input from function generator.
12. Connect the C.R.O. probe at terminal 3 and ground.
13. Observe the input waveforms.
14. Plot the waveforms observed at terminal no. 2 and 6.
15. Repeat the above procedure for triangular input waveform.
16. Calculate the loop gain for both observations.
OBSERVATIONS:
Waveforms
R1-=8.2k AND R2= 100
Vi
Vo
AV=VO/Vi
(Volts)
(Volts)
Sinusoidal
Triangular
L=Loop gain, = Feed back Factor, AV=Voltage Gain
RESULT:
PRECAUTION:
=R2/(R1+R2) L=- x AV
R2
R1
100ohm
8.2kohm
+Vcc(10)
7
1
5 U1
3
2
vin
50Hz
10v
741
4
6
741
_Vcc(10)
Fig. SCHMITT TRIGGER CIRCUIT
Vout
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A BINARY TO GRAY CODE
CONVERTER USING IC 7486
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of Binary to Gray code converter using IC 7486
APPARATUS REQUIRED:
1. Wish board
2. D.C. power supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC 7486
2. Connecting Wires
3. LED with resistors
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7486
QUAD 2 INPUTS EX-OR GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power Supply, make sure that the connection are
correct.
3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the Output state.
5. Verify the result of truthness.
6. Repeat steps from 3 to 5 for all possible combination.
FUNCTION TABLE:
Sr.
No
1
INPUT (BINARY CODE)
B3
B2
B1
0
0
0
B4
0
2
0
0
0
0
1
3
0
0
0
1
0
4
0
0
0
1
1
5
0
0
1
0
0
6
7
RESULT:
PRECAUTIONS:
B0
0
G4
OUTPUT (GRAY CODE)
G3
G2
G1
G0
B4
G4
1
B3
2
3
G3
6
G2
8
G1
11
G0
4
B2
5
B1
10
9
12
B0
13
Fig. BINARY TO GRAY CODE CONVERTER
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A GRAY CODE TO BINARY
CODE CONVERTER USING IC 7486
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of a Gray code to Binary code converter using IC7486.
APPARATUS REQUIRED:
1. Wish board
2. D.C. power supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC7486
2. Connecting Wires
3. LED with resistors
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7486
QUAD 2 INPUTS EX-OR GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power Supply, make sure that the connection are
correct.
3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the Output state.
5. Verify the result of truthness.
6. Repeat steps from 3 to 5 for all possible combination.
FUNCTION TABLE:
Sr.
No
1
INPUT (GRAY CODE)
G3
G2
G1
0
0
0
G4
0
2
0
0
0
0
1
3
0
0
0
1
1
4
0
0
0
1
0
5
0
0
1
1
0
6
7
RESULT:
PRECAUTIONS:
G0
0
B4
OUTPUT (BINARY CODE)
B3
B2
B1
B0
G4
B4
1
G3
2
3
B3
6
B2
8
B1
4
G2
5
G1
10
9
12
G0
13
11
B0
Fig. GRAY TO BINARY CONVERTER
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF AN EX-OR GATE USING MINIMUM NUMBER
OF 2 INPUT NAND GATES IC 7400
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design of an EX-OR gate using minimum number of 2 input NAND gates IC 7400
APPARATUS REQUIRED:
1. Wish board
2. D.C. Power supply
or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENTS:
1. IC7400
2. Connecting Wires
3. LED with resistors
PIN DIAGRAM:
PIN DIAGRAM OF IC 7400
4 2-INPUTS NAND GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON Power Supply, make sure that the connections are
correct..
3. Apply the input logic states as per Truth Table, in terms of +5 volts for state-1
and 0 volts for state-0.
4. Observe the output states.
5. Verify the results of truth ness.
6. Repeat steps from 3 to 5 for all possible combinations of function table.
OBSERVATION TABLE:
INPUT
RESULT:
PRECAUTIONS:
:
X
Y
0
0
1
0
1
0
1
1
OUTPUT
X.Y (X.Y)’.X (X.Y)’.Y X
Y
4
5
X
Y
6
12
1
2
13
3
9
10
8
Fig. CIRCUIT OF AN EX-OR GATE
11
F
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN AND REALISATION OF A PARITY BIT GENERATOR
USING IC 7486
BIRLA INSTITUTE OF TECHNOLOGY
MESRA RANCHI
AIM: Design and realization of an Odd Parity generator with IC 7486.
APPARATUS REQUIRED:
1. Wish Board
1. D.C. Power Supply
Or
Trainer Kit (MicroLABORATORY-II)
CIRCUIT COMPONENT:
1. IC7486
2. Connecting Wires
PIN DIAGRAM:
GPIN
DIAGRAM OF IC 7486
QUAD 2 INPUTS EX-OR GATE
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power supply, make sure that the connection are correct.
3. Apply the input logic state code mentioned in Observation Table in terms of +5
volts for state-1 and 0 volts for state-0.
4. Observe the output states.
5. Verify the result of truth ness.
6. Repeat steps from 3 to 5 for all possible combination.
OBSERVATION TABLE:
Sr. No
INPUT
Y
0
X
0
1
2
3
4
5
6
7
8
0
Podd
Z
0
0
1
RESULT:
PRECAUTIONS:
X
1
2
3
Y
9
Z
10
8
12
13
1
Fig. ODD PARITY GENERATOR
11
P