B.S. Anangpuria Institute of Technology &
Management
Branch: CSE/IT (4th SEM)
Session-2010
Computer Architecture and
Organization
CSE – 210-E
Unit -4
Basic Non pipelined CPU architecture
Lecture – 10:


CPU Architecture types
o Accumulator
o Register
o Stack
o Memory / Register
Detailed data path of a register based CPU
Submitted by:
Mr. Manoj Kumar Saini
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In Unit -3 we discussed the instruction set computer(ISA) which deals with the various
types of address instructions , addressing modes and different types of instructions in
various computer architectures.
In this chapter we will discuss the various type of computer organizations we have.
• In general, most processors or computers are organized in one of 3 ways
– Single register (Accumulator) organization
• Basic Computer is a good example
• Accumulator is the only general purpose register
– Stack organization
• All operations are done using the hardware stack
• For example, an OR instruction will pop the two top elements from
the stack, do a logical OR on them, and push the result on the stack
– General register organization
• Used by most modern computer processors
• Any of the registers can be used as the source or destination for
computer operations
Accumulator type of Organization:
In case of accumulator type of organizations, one operand is in memory and other is in
accumulator.
The instructions we can run with accumulator are :
AC  AC  DR
AC  AC + DR
AC  DR
AC(0-7)  INPR
AC  AC
AC  shr AC, AC(15)  E
AC  shl AC, AC(0)  E
AC  0
AC  AC + 1
AND with DR
Add with DR
Transfer from DR
Transfer from INPR
Complement
Shift right
Shift left
Clear
Increment
Circuit required:
2
1
6
1
From DR 6
From INPR
Adder and
logic
circuit
8
1
6
16
AC
Accumulator
LD
INR
CLR
To bus
Clock
Control
Gates
Stack Organization:
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
Stack type of organization is of two types
REGISTER STACK ORGANIZATION
Register Stack
Address
63
Flags
FULL
EMPTY
Stack pointer
SP
6 bits
C
B
A
4
3
2
1
0
D
3
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH
POP
SP  SP + 1
DR  M[SP]
M[SP]  DR
SP  SP  1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0
FULL  0
MEMORY STACK ORGANIZATION
Memory with Program, Data, and Stack Segments
1000
PC
Program
(Instructions)
AR
Data
(Operands)
3000
SP
Stack
3997
3998
3999
4000
4001
Stack grows
In this direction
A portion of memory is used as a stack with a processor register as a stack pointer
- PUSH: SP  SP - 1
M [SP]  DR
- POP: DR  M [SP]
SP  SP + 1
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Note: Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack)  must be done in software
Register type of organization:
In this we take the help of various registers , say R1 to R8 for transfer and
manipulation of data.
Detailed data path of a typical register based CPU
Input
Clock
R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELS1{
3x8
MUX
1
MUX
2
S1
bus
Decoder
SELD
OPR
} SELS2
S2
bus
ALU
Output/Result
To avoid memory access directly (as it is very time consuming and thus a costly
technique) , we prefer the register organization as it proves to be more efficient and time
saving organization.
In this we are using 7 registers. The two multiplexers and a decoder decide which
registers to be used as operands source and what register to be used as a destination for
the storage of result.
MUX 1 decides the 1st operand register which depends on the values of SELS1 (Selector
for source 1).Similarly, for MUX 2, SELs2 works as input for 2nd operand decision.
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These two inputs through S1bus and S2 bus reach ALU. OPR denotes the type of
operation to be performed and the computation or operation is performed on ALU. Then
the result is either stored back in one of the 7 registers with the help of decoder which
decides which is the resultant register with the help of SELD.
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