Design of a parametric outlier detection system
Project Proposal
by
Ronald Erickson
as part of the requirements for the degree of
Master of Engineering in Software Engineering
University Of Colorado, Colorado Springs
1 Committee Members and Signatures:
Approved by
Date
Advisor: Dr. Edward Chow
Committee member: Dr. Xiaobo Zhou
Committee member: Dr. Chuan Yue
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February 08, 2011
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2 Introduction
Background Information
In an increasingly competitive global market, microelectronics companies are designing
the integrated circuit in their facility and then utilizing a fab-less manufacturing system. These
companies design, manufacture, and test high reliability standard and custom integrated circuits
for the aerospace, high-altitude avionics, medical, networking, and other standard consumer
electronics. This type of business model the company does not own a wafer fabrication facility.
Therefore the company must employ least a single wafer fab, or many wafer fabs throughout the
world. Dependent on the product being manufactured and the required technology utilized within
the integrated circuit design. To mitigate a portion of the risk using differing wafer fabs
companies have installed standardized transistor cell structures [14].
This type of business model will design the integrated circuit, send the design to a wafer
fab, perform the package assembly on the wafers, and perform the electrical and environmental
testing of the integrated circuit prior to shipment to the end user. High reliability products are
electrically tested multiple times prior to shipment to ensure compliance to the device
specification. In some cases this testing is tailored to the specific industry for which they are
designed [14]. Companies must consistently monitor large amounts of test data at pre-defined
electrical test steps during the manufacturing process to ensure compliance [7]. Contained within
this test data are device specific electrical parametric readings that are composed of DC and AC
electrical parameters pertaining to the individual device performance.
In an effort to stay product price competitive and to maintain a highly reliable reputation
with the industry as the geometries continue to decrease. The importance of monitoring device
parametric data has become an increasingly important tool in discovering discrete product
defects [6]. However in this type of fab-less business model the microelectronic company does
not own a wafer fabrication facility. Therefore the wafer parametric acceptance criteria will be
based on less rigorous requirements set by the wafer fabrication facility within the contract. This
less restrictive wafer acceptance criterion is geared to increase fab starts and deliverables on a
statistical basis. It is certainly not geared to benefit the fab-less company because of large
deviations in material parametrics. Some companies have resorted to only electrical testing at the
wafer level used in consumer products [9]. Simply because it has become cheaper to replace the
device than to take the time to final test the device at package level. However, high reliability
devices must be tested at package level to ensure compliance
Wafer fab minor deviations within doping can create very different wafer structure
parametric data [12,13]. These types of deviations can be easily normalized and thus predicted if
there are many parametric wafer samples. But if a wafer device lot quantities are small and have
months in between starts, it becomes very difficult to a run a large sample normalized statistical
analysis. This is where a better system to predict yield, and detect outliers without many samples
is required to stay profitable.
General Circuit Manufacturing Techniques
The majority of all integrated circuit defects are discovered through the electrical test of the
integrated circuit at the wafer level. The re-tested at the packaged device level to detect
assembly, environmental and accelerated life-time infant mortality.
 Wafer fabrication defects
o transistor doping, oxide breakdown, interconnect and poly stringers
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February 08, 2011
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

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o opens, shorts, resistive metals, bridging materials
o metallization stability issues, dissimilar metals like aluminum and copper.
Potential device assembly defects
o wafer back-grind, wafer saw, die preparation
o device package defects including trace length, & integrity, package leads
o solder ball integrity, die attach, wire bond, hermetic lid seal
Environmental defects on the package and die are caused by simulating
o temperature cycle, temperature shock, mechanical vibration
o centrifuge, high humidity, salt environment
o accelerated and dynamic electrical burn-in causing infant mortality
o total ionizing dose (TID), gamma radiation effects on gate oxides
As a minimum the digital circuit DC parametric tests performed at electrical test are
o Continuity, power shorts, input leakage, output tri-state leakage
o quiescent power, active power, input and output thresholds
o minimum voltage operation
However, these digital circuit measurements usually include the AC electrical parameters
o data propagation, input set-up, output/input hold
o input rise, input fall, clock duty cycle
3 Design for Manufacturing Architectures
Existing Tools for Discovering Manufacturing Defects
All high reliability IC manufacturers must electrically test their product to ensure
compliance to the product specification and save package and assembly costs. Design for
manufacturing techniques (DfM) imply that device parametric data can potentially discover the
mismatches between the manufacturing process of the circuit and the circuit designer intent
within test structures in street locations of a die reticle [11]. Other parametric defect techniques
only detect limited parameters of quiescent current device sensitivity and are limited to a very
specific device function [10]. MARYL (Manufacturability Assessment and Rapid Yield
Learning) minimizes the risk of starting high volume manufacturing in a waferfab. Engineers
consistently study the relationships between the process parameters within the wafer fabrication
facility and the electrical parameters of the integrated circuit and predict a final yield of the
process [13]. Some tools utilize the circuit from a many building blocks approach. This tool
takes the knowledge of smaller building block circuits in an attempt to solve a part of a larger
problem. However it is only a simulation of a real world integrated circuit based upon the
performance or execution time of a particular product within a product line in a specific wafer
fab [6]. Standard DfM techniques work well within the commercial market because these
designs do not contain radiation implanting. Essentially a mature process wafer test structure will
deterministically behave as predicted without a radiation implant. However within a small fabless business model the wafer manufacturer will assume a no-liability stance to implanted wafers
due to the complexity and variance from one wafer lot to another. The high reliability
manufacturer includes a data pack for every testable parameter within the device specification
for each serialized device. A small fab-less company needs a tool that can process relatively
small amounts of individual device data and the effects of Commercial Radiation Hardened
(CRH) implants. This currently unavailable tool would allow this company to make quick
educated decisions and continue to provide their customers with the highest quality products for
at least the next 20 years.
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February 08, 2011
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4 Proposed Outlier Detection Design System
The current project investigates an automatic parametric outlier detection system design that
will utilize multiple existing algorithms like an Anderson-Darling with Shapiro-Wilk tests in
combination with affordable tools and a database into a user friendly automated system. The goal
of this design is to combine various existing outlier detection techniques and make necessary
improvements so that the small company outlier detection system is similar to other elaborate
expensive architectures but can make better manufacturing decisions using smaller data sets.
Specific software engineering approaches will be selected to aid in the implementation of the
automated outlier detections solution. The design of the parametric outlier detection system will
be sub-divided into four main areas:
1. Database
Although this project does will not focus on database design techniques, a database is the
foundation of the project because it contains the parametric device data that will be used
within the automated system. The widely-used and supported database must be utilized in an
effort to build a tool that will support use for the next 20 years.
2. Automatic Data Extraction
The automatic data extraction tool will overlap a minimum of two techniques to view the
data from more than one viewpoint.


Parametric historical data based on wafer manufacturer
- ON Semiconductor wafer fab 0.6u & TSMC Semiconductor wafer fab 0.25u.
Parametric historical data based on product identification code (PIC)
- This technique will be implemented on and individual product. SRAM (SRXX),
DRAM(DRXX)
3. Automatic Statistical Modeling
Automated data modeling and goodness-of-fit tests contained within a normalcy test of
Anderson-Darling, or Shapiro-Wilk, or Skewness-Kurtosis All will be selected. A quartile
analysis of this normalized data will then be performed on the center 50% of the data set to see if the
data is pulled together or spread out. This quartile analysis will not be affected much by outliers because
statistically few outliers can exist in the center 50% of the data [2].
If the data set is a bi-model or a non-normal distribution. The data set will be shown in a histogram
format and require user intervention to pick the data modeling performed on the data set [3,5].
Future enhancements to the outlier detection system on non-normal data sets will utilize machine
learning to track the type of data modeling that was performed by user, device type, and
distribution using a learning methodology [1 ,4].
.
4. Testing and Evaluation
The proposed outlier detection system design implementation will identify tests cases
within a test-bed. These tests can utilize only specific a single device parameter within a predetermined datasets that is loaded into the database and used as a testing criterion for initial
prototype.
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5 Thesis Plan & Schedule
1. Requirement Analysis (January 15, 2010 – February 08, 2011)
 Identify and understand the problem domain
 Evaluate possible prototypes
 Define requirements
 Define thesis project plan and schedule
 Present proposal and obtain official approval
2. Planning (February 9, 2011 –February 10, 2011)
 Identify and obtain resources needed
3. Design (February 11, 2011 – February 15, 2011)
 Design/Prototype initial test-bed and evaluate design effectiveness
 Refine and finalize test-bed design using cited paper
4. Implementation & Testing (February 15, 2011 –March 15, 2011)
 Create initial prototype
 Test-bed implementation
5. Project Closure (March 15, 2011 – April 15, 2011)
 Present final data and obtain approval.
 Create all necessary documentation
 Project defense
6 Deliverables
1. The outlier detection test-bed, including a device parametric data-log loaded into a
database and a data modeling response that resembles a real product manufacturing
scenario.
2. The outlier detection engine code that implements the various techniques/improvement
as mentioned in Section 4 of this proposal. The outlier detection system shall
demonstrate Anderson-Darling, or Shapiro-Wilk, or Skewness-Kurtosis All tests on a
provided data set contained within a data-log containing electrical device test data.
3. A project report documenting the outlier detection design and the results of
implementing the data-log within the outlier detection design prototype.
4. An analysis report describing the software engineering principles selected and how the
selected techniques are applied in the outlier detection implementation.
Ronald Erickson
February 08, 2011
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7 Bibliography
[]
Anil Kumar Jain, M Narasimha Murty, Patrick Joseph Flynn: Data clustering: a review. ACM Computing
Surveys: Volume 31, Issue 3, Pages: 264 – 323, September 1999.
[2]
Ronald Holsinger, Adam Fisher, Peter Spellerberg, : Precision Estimates for AASHTO Test Method T308
and the Test Methods for Performance-Graded Asphalt Binder in AASHTO Specification M320. National
Cooperative Highway Research Program, AASHTO Materials Reference Laboratory, Gaithersburg,
Maryland, February, 2005
[3]
Joao Gama, Pedro Pereira Rodrigues, and Raquel Sebastiao: Evaluating Algorithms that Learn from Data
Streams. ACM: SAC '09: Proceedings of the 2009 ACM symposium on Applied Computing, March 2009.
[4]
Jennifer G. Dy, and Carla E. Brodley: Feature Selection for Unsupervised Learning. JMLR.org: The Journal
of Machine Learning Research , Volume 5, December 2004.
[5]
Tony Jebara, Jun Wang, and Shih-Fu Chang: Graph Construction and b-Matching for semi-Supervised
Learning. ACM: Proceedings of the 17th ACM international conference on Multimedia, October 2009.
[6]
David Moran, Daria Dooling, Tom Wilkins, Ralph Williams, and Gary Ditlow:
Integrated Manufacturing and Development (IMaD). ACM: Supercomputing '99: Proceedings of the 1999
ACM/IEEE conference on Supercomputing, Jan 1999.
[7]
R.A Perez, J.T Lilkendey, and S. W Koh. Machine Learning for a Dynamic manufacturing Environment.
ACM: SIGICE Bulletin , Volume 19, Issue 3 , February 1994.
[8]
Khaled Saab, Naim Ben-Hamida, and Bozena Kaminska: Parametric Fault Simulation and Test Vector
Generation. ACM: Proceedings of the conference on Design, automation and test in Europe, January 2000.
[9]
Soumenda Bhattachatya and Abhijit Chatterjee. Optimized Wafer-Probe and Assembled Package Test
Design for Analog Circuits. ACM: Transactions on Design Automation of Electronic Systems (TODAES) ,
Volume 10 Issue 2, April 2005.
[0]
Wei-Shen Wang and Michael Orshansky: Robust Estimation of Parametric Yield under Limited Descriptions
of Uncertainty. ACM: ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on
Computer-aided design, November 2006.
[1]
Anne Gattiker: Using Test Data to Improve IC Quality and Yield. IEEE Press: ICCAD '08: IEEE/ACM
International Conference on Computer-Aided Design, November, 2008
[2]
Ashish Kumar Singh, Murari Mani, and Michael Orshansky: Statistical Technology Mapping for Parametric
Yield. IEEE Computer Society: ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on
Computer-aided design, May 2005.
[3]
Kees Veelenturf: The Road to better Reliability and Yield Embedded DfM tools. ACM: Proceedings of the
conference on Design, automation and test in Europe, January 2000.
[4]
Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Muller: Creating Value
Through Test: DATE '03: Proceedings of the conference on Design, Automation and Test in Europe Volume 1, March 2003.
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