ADVANCED TOPICS IN
CHEMICAL MECHANICAL PLANARIZATION
In response to a growing interest from the industry, NSF/SRC Engineering Research Center (ERC) for
Environmentally Benign Semiconductor Manufacturing and PTI Seminars, Inc. are co-sponsoring a 2 day,
short course on Advanced Topics of Chemical Mechanical Polishing (CMP). This interdisciplinary
comprehensive tutorial will give an advance overview of CMP fundamentals along with the latest developments
in this rapidly growing field. The course is designed to give participants the understanding necessary to effectively
develop or implement the CMP process.
October 9-10, 2000 - Santa Clara, CA
The Westin Hotel - 5101 Great American Parkway
Register now for the next session.
https://secure.hosting.swbell.net/www.pti-inc.com/registration.html
Deadline September 25, 2000!!
COURSE CONTENT
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Introduction to CMP
Business overview and market analysis
Definition of terms
Planarization applications
Process Fundamentals
Processing and metrology equipment and supply base overview
On-line metrology and process control
CMP consumables and supply base overview
Pattern dependencies,
Fluid dynamics
EHS issues and waste treatment
Summary and future trends
WHO SHOULD ATTEND?
Process Engineers
Personnel
EH & S Managers
IC Manufacturers
Buyers
Sales Engineers
Equipment Engineers
Manufacturing
Marketing Managers
Tool and Material Suppliers
Facility Managers
R & D Engineers
Quality Managers
INSTRUCTORS:
Duane Boning is currently the Robert N. Noyce Career Development Associate Professor of Electrical
Engineering and Computer Science at MIT, and is Associate Director of the MIT Microsystems Technology
Laboratories. His research focuses on variation modeling, sensors, control, and environmental issues in
semiconductor processes, with special emphasis on chemical mechanical polishing and plasma etch.
Additional interests include CAD tools for process and device design, and computer integrated manufacturing.
His degrees are all from MIT in electrical engineering and computer science, culminating in the Ph.D. degree
in 1991. From 1991 to 1993, he was a member of the technical staff at Texas Instruments in Dallas, TX,
where he worked on process/device simulation tool integration, semiconductor process representation, and
statistical modeling and optimization.
Srini Raghavan is Professor of Materials Science and Engineering at the University of Arizona in Tucson. He
obtained his Ph.D. in materials science and mineral engineering from the University of CA at Berkeley in 1976
and has been on the faculty of The University of Arizona since 1978. He teaches classes in applied surface
chemistry, corrosion and degradation of materials, and physical chemistry of materials. His research interests
are in the areas of wet processing of silicon, microcontamination, chemical mechanical polishing and applied
electrochemistry. He is associated with the Center for microcontamination control and the NSF/SRC
Engineering Research Center for Environmentally Benign Semiconductor Manufacturing at the University of
Arizona. He has published more than 80 technical papers and has three patents to his credit.
Ara Philipossian received his BS, MS and Ph.D. degrees in Chemical Engineering from Tufts University in
1983, 1985, and 1991. Since 1992, he has been a Materials Technology Manager at Intel Corporation
responsible for development, characterization, implementation and sustaining of new and existing CMP and
post cleaning consumables, and low k dielectrics and electroplating chemicals. In addition to his
responsibilities at Intel, Dr. Philipossian served as Lufkin Visiting Professor of Mechanical Engineering at
Tufts University in 1998, and is currently Adjunct Associate Professor of Chemical Engineering at the
University of Arizona. From 1986 to 1992, he was employed at Digital Equipment Corporation as a process
development manager focusing on thermal silicon oxidation, diffusion, LPCVD of dielectric and gate
electrodes, and wafer cleaning technology.
Dr. Philipossian has authored over 35 journal publications, and
over 55 articles in technical conference proceedings. He holds 12 patents in the area of semiconductor
processing and device fabrication.
Ronald Chiarello received his PhD in physics in 1990 from Northwestern University. He is currently Research
Program Manager for the Interface & Defect Science Laboratory at Stanford University, the Industrial Liaison
for the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing,
and a consultant to International SEMATECH on optimization of semiconductor processing. Dr. Chiarello
has published more than 40 journal articles in solid state physics, biophysics, electrochemistry, geochemistry
and semiconductor device processing.
Comprehensive class notes
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