University Of Hail
Community College
Electrical Engineering Department
Electronics Engineering and Instrumentation Program
PHYSICS OF APPLIED ELECTRONICS
(PHYS162)
Dr. Fawzy Hashem
Date:
FIELD-EFFECT TRANSISTORS
(FETs)
FETs are unipolar devices because, unlike BJTs that use both electron and hole
current, they operate only with one type of charge carrier.
The two main types of FETs are the junction field-effect transistor (JFET) and the
metal-oxide semiconductor field-effect transistor (MOSFET).
The term field effect relates to the depletion region formed in the channel of a FET, as
a result of a voltage applied on one of its terminals (gate).
Recall that a BJT is current-controlled; device that is the base current controls the
amount of collector current. A FET is different; it is a voltage-controlled device,
where the voltage between the two terminals (gate and source) controls the current
through the device.
THE JFET
The JFET (junction field-effect transistor) is a type of FET, that is, operates with a
reverse-biased pn junction to control current in a channel. Depending on their
structure, JFETs fall into two categories, n channel or p channel.
Two p-type regions are diffused in the n-type material to form a channel, and both are
connected to the gate lead. Also, wire leads are connected to each end of the channel;
the drain is at the upper end, and the source is at the lower end, as shown below:
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Basic Operation
The following figure shows dc bias voltage applied to an n-channel device.
VDD provides a drain-to-source voltage and supplies current from drain to source.
VGG sets the reverse-bias voltage between the gate and the source.
The JFET is always operated with the gate-source pn junction reversed-biased.
Reverse-biasing of the gate-source junction with a negative gate voltage provides a
depletion region along the pn junction, which extends into the n channel and thus
increases its resistance by restricting the channel width.
The channel width and thus the channel resistance can be controlled by varying the
gate voltage, thereby controlling the amount of drain current ID.
JFET Characteristics and Parameters
Consider the case when the gate-to-source voltage is zero (VGS = 0).
As VDD (and thus VDS) is increased, ID will increase proportionally between points A
and B, as shown below:
In this area, the channel resistance is essentially constant because the depletion region
is not large enough to have significant effect. This is called the ohmic region, because
VDS and IDS are related by Ohm’s law.
At point B, the curve levels off and enters the active region where ID becomes
essentially constant. As VDS increases from point B to point C, the reverse-bias
voltage from gate to drain (VGD) produces depletion region large enough to offset the
increase in VDS, thus keeping the ID relatively constant.
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Pinch-off Voltage
For VGS = 0, the value of VDS at which ID becomes essentially constant (point B) is
the pinch-off voltage (VP). An increase in VDS above VP produces an almost constant
drain current, IDSS (drain to source current with gate shorted) and is always specified
on the JFET datasheets.
Breakdown
Breakdown occurs at point C, where ID begins to increase vary rabidly with any
further increase in VDS. The JFETs are always operated below breakdown and within
the active region.
VGS controls ID
As VGS is set to increasingly more negative values by adjusting VGG, a family of
drain characteristic curves is produced, as shown below:
Notice that ID decreases as the magnitude of VGS increases to larger negative values
because of the narrowing of the channel. Therefore, the amount of drain current ID is
controlled by VGS.
Cutoff Voltage
The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off). The
JFET must operate between VGS=0 and VGS(off). For this range of gate-source
voltages, ID will vary from a maximum IDSS to a minimum of almost zero.
Notice that VGS(off) and VP are always equal in magnitude but opposite in sign. A
datasheet usually will give either VGS(off) or VP but not both. However, where you one,
you have the other. For example, if VGS(off) = -5 V, then VP = +5 V.
Universal Transfer Characteristic
Because of VGS does control ID, the relationship between them is very important. The
following figure is a general transfer characteristic curve that illustrates graphically
the relation between VGS, ID.
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This curve shows that:
ID = 0
when
ID = IDSS when
and
ID = IDSS / 2 when
ID = IDSS / 4 when
VGS = VGS(off)
VGS = 0
VGS = 0.3 VGS(off)
VGS = 0.5 VGS(off)
The transfer characteristic curve can also be developed from the drain characteristic
curves by plotting values of ID for the values of VGS taken from the family of drain
curves at pinch-off, as illustrated below:
The JFET transfer characteristic curve is expressed by the equation:
ID = IDSS ( 1- VGS/VGS(off) )2
Values of ID can be determined for any given VGS if VGS(off) and IDSS are known.
Example
For a 2N5459 JFET with IDSS = 9 mA and VGS(off) = -8 V, determine the drain current
ID for VGS = 0, -1V, -4V.
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Solution
For
For
VGS = 0 V,
VGS = -1 V,
ID =IDSS = 9 mA
ID = IDSS ( 1- VGS/VGS(off) )2
(9mA) (1- 0.125)2 = 6.89 mA
For
VGS = -4 V,
ID = IDSS ( 1- VGS/VGS(off) )2
(9mA) (1- 0.5)2
= 2.25 mA
JFET Biasing
Just as with BJT, the purpose of biasing is to select the proper dc gate-to-source
voltage to establish a desired value of drain current, and thus a proper dc operating
point (Q-point).
Self-bias is the most common type of JEFT bias. Recall that a JFET must be operated
such that the gate-source junction is always reverse-biased. This condition requires a
negative VGS for an n-channel JFET and a positive VGS for a p-channel JFET. This
can be achieved using the self-bias arrangement shown below:
For the n-channel JFET in part (a), IS produces a voltage drop across RS and makes
the source positive with respect to the ground.
Since
IS = ID, and VG = 0
Then
VS = ID RS
The gate-to-source
VGS = VG - VS = - ID RS
For p-channel JFET
VGS = + ID RS
Setting the Q-point for a Self-Biased JFET
The basic approach to establish a JFET bias point is to determine ID for a desired
value of VGS or vice versa. Then calculate the required value of RS using the following
relation:
RS = │VGS / ID│
where, │ │, means absolute value.
For a desired value of VGS, ID can be determined in either two ways: from the
transfer characteristic curve for particular JFET, or more practically, from the
equation* :
ID = IDSS ( 1- VGS/VGS(off) )2
Using IDSS and VGS(off) from the datasheet.
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Midpoint Bias
It is usually desirable to bias a JFET near the midpoint of its transfer characteristic
curve where ID = IDSS / 2. Under signal conditions, midpoint bias allows the
maximum amount of drain current swing between IDSS and 0.
Using the equation* above, will prove that ID = 0.5 IDSS , when VGS = VGS(off) / 3.4
So, by selecting VGS = VGS(off) / 3.4, you should get a midpoint bias in terms of ID.
To set the drain voltage at midpoint (VD = VDD / 2), select a value of RD to produce
the desired voltage drop. Choose RG arbitrarily large to prevent loading on the driving
stage in cascaded amplifier arrangement.
Example
Looking at the datasheet of 2N5457 JFET, select values for RD and RS, in the circuit
shown below, to set up an approximate midpoint bias. Use minimum datasheet values
when given otherwise. VD should be approximately one half VDD.
Solution
From the datasheet IDSS = 1mA, VGS(off) = -0.5 V
At the Q point:
and
thus
also
then
ID = IDSS / 2 = 0.5 mA
VGS = VGS(off) / 3.4 = -147 mV
RS = │VGS / ID│= 147 mA / 0.5 mA = 294 Ω
VD = VDD – IDRD
RD = (VDD- VD) / ID = (12 V – 6 V) / 0.5 mA = 12 kΩ
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THE MOSFET
The MOSFET (metal-oxide semiconductor field-effect transistor) is another category
of FET. The MOSFET, different from the JFET, has no pn junction structure. Instead,
the gate of the MOSFET is insulated from the channel by a silicon dioxide (SiO2)
layer. The two basic types of MOSFET are enhancement (E), and depletion (D). Of
the two types, the enhancement MOSFET is more widely used. Because
polycrystalline silicon is now used for the gate material instead of metal, these devices
are sometimes called IGFETs (insulated-gate FETs).
Enhancement MOSFET (E-MOSFET)
The E-MOSFET operates only in the enhancement mode and has no depletion mode.
It differs from D-MOSFET, in that it has no structural channel.
The following figure shows representation of the basic n-channel E-MOSFET
construction:
Notice that the substrate extends completely to the SiO2 layer. For an n-channel
device, a positive gate voltage above a threshold value induces a channel by creating
a thin layer of negative charge in the substrate region adjacent to the SiO2 layer, as
indicated in part (b).
The conductivity of the channel is enhanced by increasing the gate-t-source voltage
and thus pulling more electrons into the channel area. For any gate voltage below the
threshold value, there is no channel.
The schematic symbol for the n-channel and p-channel E-MOSFET, are shown
below:
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The broken line symbolizes the absence of a physical channel. An inward-pointing
substrate arrow is for n-channel, and the outward-pointing arrow is for p-channel.
Some E-MOSFET devices have a separate substrate connection.
Depletion MOSFET (D-MOSFET)
The following figure illustrates the basic structure of the D-MOSFET.
Notice that, the drain and source are diffused into the substrate material and then
connected by a narrow channel adjacent to the insulated gate. The D-MOSFET can
operate in either two modes - the depletion mode or the enhancement mode – and
sometimes called a depletion/enhancement MOSFET.
Depletion Mode
Visualize the gate as one plate of a parallel-pate capacitor and the channel as the other
plate. The SiO2 layer is the dielectric. With a negative gate voltage, the conduction
electrons are repelled from the channel, leaving positive ions in their place. Thereby,
the n-channel is depleted of some of its electrons, thus decreasing the channel
conductivity. The greater the negative voltage, on the gate, the greater the depletion
of n-channel electrons. At a sufficiently negative gate-to-source voltage, VGS(off), the
channel is totally depleted and the drain current is zero.
Enhancement Mode
With a positive gate voltage, more electrons are attracted into the channel, thus
increasing (enhancing) the channel conductivity.
The schematic symbols for both n-channel and p-channel D-MOSFET are shown
below:
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Notice that, the substrate is indicated by the arrow, which is normally connected
internally to the source. The solid substrate line indicated the existence of a narrow
channel between the source and the drain.
E-MOSFET Transfer Characteristic
The E-MOSFET uses only channel enhancement. Therefore, an n-channel device
requires a positive gate-to-source voltage, and a p-channel device requires a negative
gate-to-source voltage, as shown below:
As you can see, there is no drain current when VGS = 0, moreover there is no drain
current until VGS exceeds its threshold value VGS(th).
The equation* for the parabolic transfer characteristic of the E-MOSFET is:
ID = K (VGS – VGS(th))2
Notice that the equation of the E-MOSFET differs from that of the JFET because the
curve starts at VGS(th) rather than VGS(off) on the horizontal axis and never intersects
the vertical axis.
The constant K depends on the particular MOSFET and can be determined from the
datasheet by taking the specified value of ID, called ID(on), at given value of VGS and
substituting the values into the above equation*.
Example
The datasheet for a 2N7002 E-MOSFET gives ID(on) = 500 mA (minimum) at
VGS = 10 V and VGS(th) = 1 V. Determine ID for VGS = 5 V.
Solution
Using the above equation* calculate the value of the constant K
K= ID(on) / (VGS – VGS(th))2 = 500mA / (10 V – 1 V)2 = 6.17 mA/V2
Then, use the value of K to get ID for VGS = 5 V by the same equation*
ID = K (VGS – VGS(th) )2 = 6.17 (5V – 1 V)2 = 89.7 mA.
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E-MOSFET Bias
Because E-MOSFETs must have a VGS greater than the threshold value, VGS(th), zero
bias cannot be used. The figure below shows two ways to bias an E-MOSFET
In either the voltage divider or drain-feedback bias arrangement, the purpose is to
make the gate more positive than the source by an amount exceeding the threshold
voltage VGS(th).
In part (a):
VGS = R2 / (R1 + R2) VDD
VDS = VDD – ID RD
Where, ID = K (VGS – VGS(th))2
In part (b): there is negligible gate current; therefore there is no voltage drop across
RG. This makes
VGS = VDS
Example
Determine VGS and VDS for the E-MOSFET circuit shown below. Assume that the
minimum value of ID(on) = 200 mA at VGS = 4 V, and VGS(th) = 2 V.
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Solution
VGS = R2 / (R1 + R2) VDD = (15 kΩ /115 kΩ) 24V = 3.13 V
To determine VDS, first calculate K using the given values of ID(on),VGS, and VGS(th)
K= ID(on) / (VGS – VGS(th))2 = 200mA / (4 V – 2 V)2 = 50 mA/V2
Now calculate ID for VGS= 3.13 V
ID = K (VGS – VGS(th))2 = (50 mA/V2) (3.13 V – 2 V)2 = 63.8 mA
Finally
VDS = VDD – ID RD = 24 V – (63.8 mA) (200Ω) = 11.2 V
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