Development of a Preamplifier ASIC for the GlueX DriftChamber System
April 10, 2006
1. Introduction
Building on the work started by the GlueX collaboration members from the University of
Alberta last year, we have defined below the scenario for “stage-2” of a contribution to the
GlueX detector electronics. The main thrust of the stage-2 work is the development of a
preamplifier ASIC for the GlueX drift-chamber systems, based on the ASDBLR (Amplifier,
Shaper, Discriminator, Base-Line Restorer) ASIC used in the ATLAS-TRT (Transition
Radiation Tracker). This work will be carried out by the University of Alberta in
collaboration with the University of Pennsylania, although the University of Alberta has the
overall responsibility for the design, construction and delivery of the final GlueX preamp
system.
We have chosen the 8-channel ASD-BLR chip as a basis for the GlueX pre-amp ASIC
design, for four main reasons: 1) the analog signal processing used for this chip is arguably
the most suitable for adaptation to GlueX requirements; 2) this chip may be realized in
either CMOS or bi-polar technology; and 3), last but not least, the designer of the existing
ASD ASIC technology has agreed to work with us on the design of a prototype GlueX
preamp chip.
We foresee that this work will take place over a two year period and proceed in three
phases:



Stage I Design of Prototype ASIC (year one);
Stage II Test and Measurement of Fabricated Devices (year one);
Stage III Revision, final design and acceptance tests (year two) + design of pre-amp
board for chambers (year two) .
This document provides a detailed funding for the first year only. However, the current
estimated second year funding requirements are also included for completeness.
2. Description of proposed work
We envisage that the work needed to produce the design for the final production version of
the GlueX ASD ASIC will extend over two years (200608). The first year program,
(2006-07) described below, will produce one set of 40 prototype chips (the least costly
chip run available from MOSIS using the CMOS (TSMC) 0.25 mm process).In year one we
only expect to: perform acceptance tests of the produced ASICS; characterize the board;
and, perform initial tests on chambers using simple test boards. It is assumed that a second
and final prototype chip run will be necessary in year two, to incorporate the lessons learned
in the first year of prototyping. In this case ~120 chips (~1000 channels) will be produced
for testing, using MOSIS. These ASICs will be acceptance tested at Penn using the the
IMS-tester. The design and production of the first (and hopefully final) version of the
chamber mounted pre-amp boards will take place in year two. Subsequently, the ASICs
produced in the final run will be mounted on ~ 60 (assuming 2 x 8 channels per board)
preamp boards that will be utilized for large scale tests on GlueX drift chamber prototypes.
2.1 Phase I
Design of Prototype ASIC
We intend to develop an Amplifier/Shaper/Differential Driver Application Specific
Integrated Circuit (ASIC) consistent with the objectives of the front end electronics for the
GLueX drift chamber trackers. This chip will be based on signal processing used in the
existing ASD-BLR ASIC. The prototype chip will be designed and fabricated utilizing a fast
CMOS (TSMC) 0.25 mm (baseline), or a Silicon-Germanium (Si-Ge), process using a
suitable foundry under the auspices of MOSIS. It is expected that the prototype (and final)
preamp chip will have an area of ~12 mm2. In Stage 1 we will:
1. Select a target technology based on expected performance and cost. (immediate);
2. Chose a preamplifier and shaper topology based on existing designs and optimize
performance for the Gluex Design goals.
3. Perform a complete (test) design cycle to demonstrate and confirm the status of
CAD software and ensure that we are familiar with the complete ASIC design cycle;
4. Report achievable design goals for the Preamp and Shaper based on simulation
studies;
5. Initiate a partial layout of critical circuit elements, extract & simulate circuit with
parasitics;
6. Organize a design review with known experts, probably at BNL. Implement or
respond to reviewer comments;
7. Complete Layout of a 4 or 8 channel Preamp/Shaper/Driver;
8. Deliver a foundry compatible MPW (Multi Piece Wafer) prototype layout of
A/S/Driver chip. (Stage I primary objective.);
Our objective is to complete step 8 by the end of August. If time permits design and
fabricate a comparator circuit to be added as a pad selected connection option.
2.2 Phase II Test and Measurement of Fabricated Devices
1.
2.
3.
4.
Bench tests at the University of Pennsylvania;
Arrange for RF packaging suitable for operation with chamber load.
Prototype Chamber tests with boards produced at the University of Alberta..
Revision objectives/list.
2.3 Phase III Revision of Pre-amp ASIC and Finalize the Design of the 1st Iteration of
the Production Preamp Board
1. Revise schematic and layout to reflect updated design goals and circuit
improvements;
2. Run production level cross-checks on layout extracted (with parasitics) circuit
including: expected process, voltage and temperature;
3. Design first iteration of production board for pre-amp deployment;
4. Continue testing on chambers.
3. Responsibilities
As stated above, the Alberta-GlueX group has the overall responsibility to the GlueX
collaboration for the pre-amp system design development and production for the drift
Chamber system. The design of the GlueX pre-amp ASIC will be the responsibility of Mitch
Newcomer of the University of Pennsylvania. The Penn group will also be responsible for
the acceptance testing of the produced chips in Phase II and Phase III of the project. The
Alberta group will be responsible for the design and production of the final version preamp
boards – although the Penn group will provide important input on the design and testing of
the preamp board. The Alberta and Pennsylvania groups will work with the groups
responsible for the drift chamber system, on which the pre-amps will be deployed, to ensure
an effective design for the GlueX preamp system as a whole (ASIC and chamber board).
4. Deliverables
This proposal covers Phase I & II and estimates Stage III requirements.
4.1 Phase I Deliverables:
1. Schematic Level Design Progress report with updated Preamp/Shaper/Driver with
design Goals based on target CMOS technology performance - May ‘06;
2. Finalized design goal review - simulation results with extracted parasitic- July ‘06
3. Prototype amplifier/shaper/driver ASIC design for MPW run – we will use MOSIS
and produce a run of ~40 chips – completion September ‘06.
4.2 Phase II - Deliverables:
The Penn Instrumentation group will help set design goals, bench test the produced ASIC
chips and review chamber test prototype boards. The Alberta group will design, produce
and test all chamber test prototype boards.
1. Construction of hand wired test boards for bench tests (U. of Penn.) and chambers
tests (U. of Alberta) – September ‘06;
2. Summary report on bench and chambers tests of fabricated devices – December ‘06.
4.3 Phase III - Deliverables
Redesign ASIC prototype (if necessary) and submit for second prototype or production run.
It should be noted that a significant redesign effort is not expected to be necessary. This
expectation may be incorrect if the pre-amp ASIC is intended for the readout of detector
systems that are not at fully characterized prior to phase-1 of the project. All produced
ASICS will be tested using the Penn IMS-tester. During, phase III the Alberta group will
design and produce the first iteration of the preamp board for deployment on the drift
chambers system. The Penn group will also provide input to the design of the prototype
board and, it will take part in some testing and assessment of populated preamp boards
5. Budget
The current prices obtained from MOSIS for the CMOS process with a 12mm2 chip-size
are: a) first run of 40 is $27K; b) 100 chips $30K; c) 500 chips $50K; d) 2400 chips $100K.
Phase I/II (2006-07):
ASIC US design manpower (65 man days at $60/hour
$30,000 (US)
ASIC production ( MOSIS CMOS (TSMC) 0.25mm process)
$27,000 (US)
The packaging cost for initial 40 prototype chip
run ($50/chip)
$ 2000 (US)
The cost of producing boards for bench tests (plus
sorted components, sockets, connectors, etc.)
$ 2,500 (US)
The cost of producing boards for chamber tests (plus
sorted components, sockets, connectors, etc.)
$ 3,500 (US)
Consultation travel for U. of Penn. Group.
$ 3,000 (US)
TOTAL
$ 68,000 (US)
Phase III (2007-08):
Minor ASIC layout revisions and
Process/Voltage/Temperature tests
$10,000 (US)
OR Revise major block/chip footprint
$30,000 (US)
ASIC board design + population + testing
Manpower (140 man days @ $45(US)/hr)). In this case
we will be utilizing the electronics engineers/techs at the
U. of Alberta for most of the design and production manpower.
$50,400 (US)
The cost of up to 500 ASIC prototype (12mm2) chips.
Production using MOSIS foundries accessible (NB
price obtained from MOSIS – the cost of a minimum
of 1000 channels of pre-amps using MOSIS.
$50,000 (US)
The testing of the preamp ASIC at Penn, using the IMS-tester
$ 5,000 (US)
The cost of 60 bare prototype preamp boards
(assume 2 x 8 channels per board)
$12,000 (US)
The packaging cost for 120 prototype chips ($10/chip)
$ 1,200 (US)
The cost of assorted components, sockets, connectors, etc
$ 4,000 (US)
TOTAL
$132,600 or $152,600 (US)
6. Summary & Deliverable Payment Schedule
6. 1 Budget Summary
ALBERTA - ELECTRONICS
REQUEST
Description of project item
Initial Preamp ASIC design
Preamp ASIC production using
MOSIS( 40 chips  320 channels)
Chip packaging
Boards for ASIC bench tests
Boards for ASIC chamber tests
Consultation travel (U.of Penn.)
TOTAL
$
2006-07
30,000
$
$
$
$
$
27,000
2 ,000
2 ,500
3 ,500
3 ,000
$
68,000
6.2 Phase 1 and II Deliverables and Payment Schedule
Phase I & II (2006-07)
Phase 1a) April 15th - Initial schematic Level Design Progress report
with updated Preamp/Shaper/Driver design Goals based on target
CMOS technology performance.
$13,000
Phase 1b) May 30th - Report on Design Goals based on target CMOS
technology performance
$13,000
Phase 1c) July 1st - Finalized Design Goal Review with Simulation
Results with extracted parasitic
$13,000
Phase 1d) September 1st - Prototype Amplifier/Shaper/Driver ASIC
design for MPW run – using MOSIS and produce a run of
~40 chips.
$13,000
Phase 2a) November 1st - Construction of hand wired test boards for
Bench tests (U. of Penn.) and chambers tests (U. of Alberta)
$13,000
Phase 2b) December 31st - Summary report on bench tests and chambers $ 3,000
tests of fabricated devices.
TOTAL
$68,000