The purpose of this tutorial is to provide the reader with a brief insight on Mosis’s
chip submission process. First and foremost, don’t be discouraged if you need to submit
the chip more than 20 times or more, I can assure you that it is quite normal. Finally, I
am only providing one method of Mosis’s chip submission as there are others.
To start off this tutorial, I would like to note that the Cadence’s version is IC5141
and the technology used is 0.18 IBM CMRF7SF. With other versions of Cadence, the
steps might differ slightly, but should be the same. Also, I might wish to point out that
IBM has its own menu for exporting and importing of cell views therefore upon
completion of the IBM’s steps, I will briefly touch on steps of using Cadence’s own
exporting and importing steps. Finally, this tutorial assumes that the final cell layout
view has passed DRC and LVS. With that, let’s start the tutorial…
To simplified things, we will submit a chip of an AND gate.
Fig. 1 shows the
“AND_CHIP” library which contains the following cell views: and2 (Fig. 2), inverter,
nand2. Also note that there were other libraries, but it had been cropped to simplified
things.
Fig 1. Library Manager
Fig. 2 AND2 Layout
Exporting
The first step of is to export the layout into a gds file where it can be submitted to
Mosis.org. To export, select IBM_PDKGDS2/GL1 Translation from the CIW window
(Fig. 3).
A new window will pop where each fields need to be filled with the
corresponding project to be submitted. Refer to Fig. 4 to see the filled fields with this
tutorial, but make sure that “Cadence into GDS2” is selected.
Click OK and the
translation should begin automatically. Once completed, it will ask if you wish to view
the PIPO.LOG file, click Yes (Fig. 5). Scroll down to near the end of the log file to verify
that there were 0 errors (Fig. 6). The warnings can usually be ignored, but it is good to
check what the warnings are. For this tutorial, we will ignore the warnings. With that,
the exportation part of the chip submission is completed and the created gds file (in this
case, it would be and2.gds) is stored at the directory which Cadence was ran.
Fig. 3 CIW
Fig. 4 Data Translation
Fig. 5 Data Translation Completion Prompt
Fig. 6 PIPO.LOG File
Importing & Verifying
Once the project has been exported, we wish to verify that all layers are exported
correspondingly and that all valid/used layers are presented in the gds file. To do this, the
exported file will need to be imported to a new library where each layer will be checked.
First, start off by creating a new library with the same technology attached (Fig. 7 – Fig.
11). Generally, it is a good idea to use same library name with “_import” append to its
name. This eliminates confusion among libraries when you have a ton of them.
Fig. 7 CIW Screen
Fig. 8 New Library (Enter Name & Click OK)
Fig. 9 Technology Selection (Select Library & Click OK)
Fig. 10 Library Properties (Use Default)
Fig. 11 New Library Manager Showing Newly Created Library
Now that the new library has been created, the exported gds file will be imported into the
library. To import, select IBM_PDKGDS2/GL1 Translation from the CIW window
(Fig. 12). Since we wish to import the gds file into the newly created library, the fields
were filled out as shown in Fig. 13, but make sure to select “GDS2 into Cadence.” When
import completes, make sure to view the PIPO.LOG file to verify that there are no errors
just as in exporting of the project. If you check the library manager window, you should
see all the used cell views (including the CMRF7SF library) for the project. Note that if
your original library has other cell views that were not used in the project (top cell view),
it will not be exported in the first place therefore upon importation, the new library won’t
reflect such cell views.
Fig. 12 CIW Screen
Fig. 13 Data Translation
The next part is to verify that the imported project is correct. First, we check to make
sure that the sizes of the transistors are correct. Therefore, open the top cell view layout
(AND2) and take few measurements using the ruler (hotkey k) and compare to the
original layout (Fig. 14). They should be the same, otherwise, the translation rule file
need to be check or modified. Next we wish to check all the layers of the layout to be
correctly translated. Using the IBM design kit, it is quite easy to only enable the present
layers in the project. From IBM_PDKLSWPresent Layers Only and it should look
like Fig. 15. If not using the IBM design kit, then one might need to manually enable the
used layers for the project. This can be done be EditSet Valid Layers… in the LSW
window. Once the valid layers are set, we will check each layer individually. First we
disable all the layers except for RX layer. This can be done be selecting the RX layer and
click on “NV” button on the LSW window and the result is shown in Fig. 16.
Check the
layout with only RX layer to make sure that RX is in its rightful place and that it is not
translated into a different layer. Each valid layers of the project will need to be check
individually. When you finish with the individual check, then you will need to run a
DRC and LVS check on the imported design. If everything passes, then you will have a
gds file that is good to be submitted for fabrication.
Fig. 14 Layout Measurement
Fig. 15 Present Layers Only
Fig. 16 RX Layer of Layout Only
GDS File Submission to Mosis.org
With a fully passed gds file, the next step is to submit it to Mosis.org for fabrication.
This step assumes that a Mosis project account has been created by the professor/advisor
and the design number and password are known. First, you need to run the Mosis CRC
checksum on the gds file. The program that computes the checksum is provided in two
formats:
 mosiscrc.c (C source code) (http://www.mosis.org/Customer/Email/mosiscrc.c)

mosiscrc.exe
(Windows
executable)
(ftp://ftp.mosis.com/pub/mosis/info/mosiscrc.exe)
If you’re using the UNIX system, you have to compile the C code provided. A sample
of the program ran at UNIX is shown in Fig. 17. Make sure to set the switch –b at
the command line to denote that it’s a binary file. Also, you will need to find out the
IP address from where the submission is going to be sent from. Next we will have to
file
out
the
fabricate
web
form
https://www.mosis.com/Webforms/fabricate.html
which
can
be
found
at
Fill out the fields of the form
where it is boxed by red (Fig. 18), the rest can generally be ignored. The form is
pretty much self-explanatory, but make sure to select GDS, Uncompressed, and CRC.
Enter the numbers from the CRC checksum program just as show in our case. Once
completed, click “Submit Form” at the bottom of the page and you’re ready to ftp the
gds file. In a terminal window, we will ftp into Mosis server and upload the gds file.
This is shown in Fig. 19. Due to this being a sample submission, the steps beyond
this cannot be shown. But after the ftp, you will be asked for name and password.
The name is your design number and the password is the “FTP Send Password” that
you’ve created when you filled out the fabrication form. Once inside, you will have
to change the mode to binary and then you can upload the file using the put
command. Once that’s completed, you can quit the program and wait for an e-mail
from Mosis.org.
The first submission is bound to have errors.
You have to read
through the e-mail and check to see what the errors are. A lot of times, it has to do
with the density failure, but can easily be fixed by adding fillers. Either way, you will
have to fix the problems and resubmit the project until you have no errors at all. In
the future, let’s say you change something in your project or let’s say your initial
chip size does not match of the actual chip size, you can update your project by
going to https://www.mosis.com/Webforms/update.html and fill out the needed field
of change. Finally, let’s say you need to resubmit your project due to errors in the
initial submission or changes, you will have to cancel the fabrication of previous
submission before you can submit another one.
You can cancel your project
fabrication by going to https://www.mosis.com/Webforms/cancel_fabrication.html.
Also, all these web forms can be found at https://www.mosis.com/Webforms/menuwebforms.html.
Fig. 17 CRC Checksum Program (UNIX)
Fig. 18 Project Fabrication Form
Fig. 19 FTPing Design to Mosis
Exporting and Importing Using Cadence Tools
To export, from the CIW select FileExportStream… A new window will pop up
shown in Fig. 20. Fill out the fields accordingly to your project and click OK. Once
completed, make sure to check the PIPO.LOG file to ensure that there’s no errors.
Fig. 20 Exporting
To import, from the CIW select FileImportStream… A new window will pop up as
shown in Fig. 21. Fill out the fields accordingly to your project and click OK. Once
completed, make sure to check the PIPO.LOG file to ensure that there’s no errors.
Fig. 21 Importing
On final note, remember that most likely you’re going to have to submit more than once
therefore good luck and have fun…^_^