Laboratory Short Course
The Timer - Pulse Accumulator
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Document Number: LABS12CINTRO21 /REV 0
Reading this Document
Answers provided to the Instructor assume that the reader is using Freescale HCS12C Family Student Learning Kit,
and CodeWarrior development software.
This short course has been created using an adapted version of the Process Oriented Guided Inquiry Learning (POGIL)
method. For more information visit www.pogil.org
Freescale Semiconductor
LABS12CINTRO21, Rev 0
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Overview
In addition to needing to generate accurate time intervals in our microcontroller programs, we
frequently need to count external events. The timer circuit includes a pulse accumulator system that
allows our programs to do this.
Learning Objectives
In this module you will extend your knowledge of the timer by investigating the pulse accumulator
features. You will see the hardware involved and understand what has to be initialized to use this
device. We will also learn about its interrupt capabilities.
Success Criteria
At the conclusion of this module you will be able to write a program using the input capture features
to measure the width of a pulse or the frequency of a signal.
Prerequisites
Before undertaking this module you should be able to start the timer and to understand the basic
components of the timer subsystem. You must also understand the operation of the interrupt system.
More Resources and Further Information
Cady, Fredrick M., Software and Hardware Engineering: Assembly and C Programming for the
Freescale HCS12 Microcontroller, 2nd edition. (New York: Oxford University Press, Inc., 2008),
Chapter 12 HCS12 Interrupts and Chapter 14 HCS12 Timer
CPU12 Reference Manual, S12CPUV2.PDF, Freescale Semiconductor, Inc.
TIM_16B8C Block User Guide, S12TIM16B8CV1/D.PDF, Freescale Semiconductor, Inc.,
October 2001.
Timer Pulse Accumulator Basics
Teach:
Figure 1 shows the pulse accumulator system. A 16-bit counter (PACNT) counts pulses on the Port T
bit 7 (PT7) input pin. The input edge (rising or falling) is selected by the PEDGE bit in PACTL. When
the selected edge occurs, the pulse accumulator input edge flag (PAIF) is set and can generate an
interrupt if the PAI bit in PACTL is set and interrupts are unmasked. If the 16-bit PACNT counter
overflows the pulse accumulator overflow flag (PAOVF) is set and it, too, can generate an interrupt.
The students should be
able to inspect the
figure and see what bits
in which registers are
needed to control the
various features. They
will be required to find
in their documentation
details such as register
addresses and the
operation of control
bits.
'CCR'
I
'PACTL'
PAI
PT7
Input
Edge
Select
Port
Pin
PEDGE
'PACTL'
PAIF
16-bit Counter
PAOVF
'PACNT'
'PAFLG'
Event Counting Mode
PAEN = 1, PAMOD = 0
'PACTL'
PAOVI
Pulse
Accumulator
input
Edge
Interrupt
Pulse
Accumulator
Overflow
Interrupt
'PACTL'
Figure 1. Timer Pulse Accumulator.
Freescale Semiconductor
LABS12CINTRO21, Rev 0
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Explore 1.
1.
2.
Answers:
What is the address of the following registers?
1a) $0060
a.
PACTL
1b) $0060
b.
PACNT
1c) $0061
c.
PAFLG
2) Set the PEDGE (bit
4) in PACTL.
How would you select a rising edge on PT7 to increment the pulse accumulator?
Resources:
See the HCS12
Register I/O Module for
a quick reference.
Timer Gated Accumulator
The pulse accumulator operates in a gated timer mode when PAMOD = 1. In this case, when the
selected edge on Port T bit 7 (rising or falling) is detected, the Bus Clock divided by 64 is gated into
the 16-bit PACNT counter. When the subsequent falling or rising edge occurs on PT7, the pulse
accumulator input edge flag (PAIF) is set. Pulse accumulator overflows are detected by the PAOVF.
Each of these events can generate an interrupt request. See Figure 2.
'CCR'
Bus Clock
I
'PACTL'
Divide
by 64
PAI
PAIF
PT7
Port
Pin
Input
Edge
Select
16-bit Counter
'PACNT'
PEDGE
Gated Accumulator Mode
PAEN = 1, PAMOD = 1
'PACTL'
'PACTL'
PAOVF
'PAFLG'
PAOVI
Pulse
Accumulator
input
Edge
Interrupt
Pulse
Accumulator
Overflow
Interrupt
'PACTL'
Figure 2 Timer Gated Accumulator.
Stimulate 1.
Answers:
1.
Write a small section of code, either in assembly or C, that will select a negative edge to start the
gated clock in gated accumulator mode.
1) bset PACTL,BIT4
2.
For a Bus Clock of 8 MHz, what is the maximum duration of the gate pulse before the PACNT
counter overflows?
2) 64 x 8.192 ms =
524.3 ms
Skill Exercise 1
1.
Set up an experiment using a signal generator connected to PT2 and demonstrate the following:
a.
Using the pulse accumulator in event counting mode.
b.
Using the pulse accumulator in gated accumulator mode.
Communication – Inter-Group
Join another laboratory group and compare your solutions to Skill Exercise 1.
Reflection on Learning
Freescale Semiconductor
LABS12CINTRO21, Rev 0
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How does your group's solution to Skill Exercise 1 compare with another group? Can you see
improvements to make to your program to make it more efficient or more easily understood by
somebody else?
Freescale Semiconductor
LABS12CINTRO21, Rev 0
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Revision History
Revision
Comments
Author
0
Initial Release
Fred Cady
Freescale Semiconductor
LABS12CINTRO21, Rev 0
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© Freescale Semiconductor, Inc. 2006.
Document Number: LABS12CINTRO21 /REV 0