ECE3801 Tutorial – 1
Introduction to Xilinx Webpack
Using Schematic Capture
Updated 28 October 2011 – S. Jarvis
Originally created by Ahmad Hatami, 2005
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Objective
After completion of this tutorial you will be able to use Xilinx Webpack to capture,
simulate, test, and download a logic schematic design to a Nexys2 Starter Kit Board. The
tutorial also provides an overview of design flow, in general, as you implement a
hierarchical project -- a half adder, then a full adder and then a multi-bit adder.
Design Flow Overview
Design flow for gate array devices (CPLD or FPGA) can be divided in three steps, as
depicted in Figure 2.
Design Entry: You enter your design into the system by a schematic editor or through a
HDL (Hardware Description Languages such as VHDL or Verilog). Your design may
include different gates, combinational blocks, and/or sequential blocks.
Implementation: Design tools translate your design to an optimized format suitable to
your target device. The output of this step is a bit stream file that can be downloaded into
the hardware.
Verification: Simulators are used for functional and timing verification of the design.
Functional simulation verifies the behavior of the system without any knowledge of the
underlying target and does not provide timing parameters. Timing simulation provides
various timing analysis after the design has been compiled for a specific target device.
Figure 3 shows a more detailed design flow diagram for FPGA or CPLD devices. Our
projects are targeted for Xilinx Spartan 3E FPGA. For more information Nexys2 board
refer to [1].
Half Adder
Half adder adds two binary inputs (a and b) and generates two outputs Sum and Cout
Figure 1. In the following sections you will implement a half adder.
a
0
0
1
1
b
0
1
0
1
Sum Cout
0
0
1
0
1
0
0
1
Figure
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Figure 1
Figure 2
1. Start Xilinx Project Navigator by clicking on Xilinx ISE icon and then selecting
New Project from the file menu.
2. Create a new project as shown in Figure 4. Try to use your “M:” drive as the
project location for your files. Make sure there are no spaces in the folder name
that you create for your work. If you must create you project on the local disk be
sure to save it to your M: drive when you’re done or it will probably be lost or
possibly copied!
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Figure 3
3. Select the device parameters as should in Figure 5. These are specified on the chip
itself. Select the ISim simulator.
Figure 4
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Project:
Project Name: tut1
Project Path:
E:\ece3801_B08\lab0\lab0\tut1
Top Level Source Type: Schematic
Device:
Device Family:
Device:
Package:
Speed:
Spartan3E
xc3s500e
fg320
-4
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: VHDL
Enhanced Design Summary: enabled
Message Filtering: disabled
Display Incremental Messages: disabled
Figure 5
Design Entry
4. Click if Finish to complete the project creation
5. Under the Project Menu, select New Source to begin designing your new project.
Select schematic as the type of the source file (Figure 7). After you've created the
file, double click on your newly generated source file. This opens the schematic
editor (Figure 8)
6. Use the magnifying glass zoom button to make the editor view more readable.
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Figure 6
Figure 7
7. Add a wire to your design by clicking on
icon.
8. Click on
to add an IO marker at the end of the newly generated wire.
9. Right click on the newly generated IO marker and change the name to a
10. Repeat the same process to add a second wire with an associated IO marker and
name the marker b. You can also change the name in an Object Properties
window (right click on the object).
Figure 8
11. Click on the “Symbols” tab and add an and2 gate (in the logic category) to your
schematic (Figure 10). You can zooming on the view of your schematic using F8.
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12. Connect input a, and b to the inputs of the and2 gate.
13. Add a wire and an output marker to the output of the and2 gate and change its
properties (Figure 11).
Figure 10
Figure 11
14. Add an XOR gate to your design and add three wires two for inputs and one for
its output.
15. Add an output IO marker to the output of the XOR gate and changes its name to
Sum.
16. Right click on one of the input wires select Rename Selected Net and enter 'a' and
'Yes' for merge the nets1.
17. Similarly, name the second XOR input pin ‘b’.
18. Your design should be similar to Figure 12.
19. Save your file and click on ‘Check Schematic’ in the “Tools” menu. If any errors
are detected, they will need to be corrected.
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Each wire is called a net. Two nets with the same name are connected although there is no
connecting line between them. Mousing over a net will pop up an info box containing its name, etc.
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Figure 12
Generating a Test-bench Waveform for Functional Verification
Functional Simulation for Design Verification
In this section you will learn how to create and use a VHDL or Verilog Test Bench to
verify the functional behavior of your design. VHDL and Verilog are simulation
languages as well as synthesis languages. In a HDL simulation, the schematic design you
want to test (i.e. the Unit Under Test – UUT) is instantiated in the simulator (Isim). Xilix
will take care of the VHDL or Verilog that associates the test bench with the schematic.
You will need to add the VHDL or Verilog that asserts all input combinations you want
to test. For our half adder there are only 4 possible input combinations so you will
complete an “exhaustive test” of all possible input combinations.
20. First implementing VHDL test bench. On project navigator add a new source file
through the project pull down menu selecting either VHDL Test-bench as the file
type. Associate the test bench with your half adder schematic.
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Figure 13
21. Xilinx will generate the VHDL Test Bench framework depicted in Figure 15. In
the Process block type the assignment commands shown in Figure 15 to assert
each of the possible input combinations. Save All.
22. On the bottom Tabs in the side panel select Design then select your half adder test
bench then Simulation. Now in the lower side pane click on “ISim Simulator”
then ‘Simulate Behavioral model’ on the project navigator.
23. When the ISim window pops up it defaults to showing 1 microsecond with pico
sec resolution which is much to fine for our simulation. Change the time scale to
5-10 ms and press the > go button. Then press the full scale view button.
24. Are the outputs of the simulation as you expected then to be? Save a screen shot
of this simulation result to show the TA.
25. Alternatively you can implement the test bench using Verilog. Instead of adding
a VHDL Test Bench add a Verilog Test Fixture file and associate it with your half
adder. You do NOT have to do both a VHDL and a Verilog test bench. Just
choose 1 language.
26. Again Xilinx will generate the framework for the test fixture. You must endit the
file to add the test input similar to whats shown in Figure 17. Then run the ISim
Simulator as discussed above. Here however set the time window to 10
microseconds.
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Figure 14
BEGIN
-- Assert each of the possible inputs
a <= '0';
b <= '0';
WAIT FOR 1ms;
a <= '1';
b <= '0';
WAIT FOR 1ms;
a <= '0';
b <= '1';
WAIT FOR 1ms;
a <= '1';
b <= '1';
WAIT; -- will wait forever
END PROCESS;
Figure15
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Figure 16
initial begin
// initialize variables
a = 0;
b = 0;
#1000; // wait 1000 ns for global reset to
finish
// enter input values here
a = 1;
#1000;
// wait 1000 ns
a=0;
b = 1;
#1000;
a = 1;
#10000;
end
Figure 17
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Xilinx, Nexys2 Starter Kit Board
Reference [1] provides the detail information about the Nexys2 Starter board. Figure 18
provides the overall architecture of the board with its major components. Nexys2 board
provides eight sliding switches (SW0-SW7) and four push buttons (BTN3-BTN0) that
can be used as inputs. Each of these switches is connected to an associated IO pin of the
FPGA. Figure 8 in the Nexys2 Reference Manual [1] shows to which pins these digital
IO devices are connected. Both Slide switches and push buttons are active high, in other
words when they are in on status they connect VCCO to the FPGA IO pin. Note that there
is no de-bouncing circuitry for these inputs. There eight surface mounted LED’s on the
board that can be used as an output for your design (LD7-LD0). The LED’s are all active
high, so to turn an LED ON you need to apply a logic high to the corresponding IO pin of
the FPGA.
Figure 18
Synthesis
You have completed your design entry and functional verification of a Half Adder (HA)
in previous steps without any assumptions about the underlying target. In this section you
will compile your design targeted for Nexys2 FPGA device by assigning input ports a, b,
to SW1-SW0 and outputs Sum, and Cout to LD1-LD0 on the board respectively. The
following steps show you 2 ways you can create a user constraint file that assigns these
mappings. Be sure to select the Implementation button again. Only add ONE .ucf file to
your project!
27. Click your half adder schematic file. Then under New Sources select
Implementation Constraint file and enter a file name. The file name must end in
.ucf. The new file will appear under your half adder file. Double click of the .ucf
file and a (blank) editor window will open. Copy the following into the window
and save.
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#The contents of tut1.ucf
NET "a" LOC = "H18" ;
NET "b" LOC = "G18" ;
NET "Cout" LOC = "J15" ;
NET "Sum" LOC = "J14" ;
Simulation for Synthesis and Timing Verification
First make sure the pull-down menu in the Sources pane is set to Behavioral Simulation
again. In the project navigator session make sure that the HA test bench waveform that
you had generated before is selected and double click on ‘Simulate Behavioral Model’ on
the process panel. This will launch the simulator again
28. Click on
button again so you can see the entire time span of the
simulation. This waveform simulates the behavior of the systems as the inputs a
and b change. Note that any change on input ports causes an immediate effect at
the outputs. In other words, like your initial design simulation, there is no
propagation delay in this simulation. Close the simulator.
29. In the project navigator select your half adder schematic. Make sure that Source
pane is set to Implementation and that the schematic view is up. Under the
Processes pane double-click on Implement Design. This will take several seconds
to run.
30. Now set the Sources for pull-down menu to Post-Route Simulation.
31. Click on you test bench waveform. Then under the Processes pane double click
on the Simulate Post-Place & Route Model. This simulator will model the
expected propagation delays resulting from the lay-out of the gates and pin
connections on the FPGA.
32. When the simulator results are shown use the zoom and the cursor measuring
tools on the toolbar to measure the propagation delay of your design as it is
actually laid out for implementation on the Spartan 3E FPGA. Zoom in to one of
the transitions of each output.
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Figure 19
Implementation and Downloading
33. In the project navigator session make sure that the HA schematic file is selected
and the Sources For pull-down is set to Implementation. You are ready to
generate the bit file but you need to set the clock to JTAG CLOCK to avoid
an annoying error box in Adept. Right click on Generate Programming File and
then select Startup Options on the left. Switch the FPGA Startup Clock option
to JTAG Clock and click Apply. Then under the Processes pane, double click on
Generate Programming File. This generates the downloadable bitstream file
(*.bit).
34. From the Windows Start menu open the Digilent/Adept file and click the Initialize
Chain button
35. Select the *.bit file for you half adder and associate that with the first chip.
(Figure 20).
36. Click on the first chip Program button.
37. Now you can test your design by toggling SW0 and SW1 and see the Sum, and
Cout output on LD1-LD0. Try different combination of inputs and make sure that
your design works properly. Print the Sign-Off sheet from the Lab web page
then demonstrate your half adder to the TA for Sign-off CREDIT!!
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Figure 20
Hierarchical Design and Symbols
In most projects it is desirable to design components that can be reusable in your future
projects. In this section you will create a symbol for your HA that can be used in the rest
of the project.
38. Open the schematic file that you have designed for your HA circuit.
39. Start the symbol wizard through the ‘Tools’ pull down menu.
40. Follow the dialogue boxes as appear in Figure 21.
41. By completing this process you have created a new symbol for your HA design
(that should appear in your symbols library) which can be reused in future.
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Figure 21
Full Adder
In this section you will design a full adder. Figure 22 shows the input-output interface of
a full adder. Three single bit inputs (a, b, Cin) are added together and the result appears as
Sum, and Cout on the output ports. Obviously you can design such a circuit using basic
gates, but here you want to use your previous HA as the main building block
a
Sum
b
F.A
Cin
Cout
Figure 22
42. Open the project navigator and add a new source file to your project through the
project pull down menu (Figure 23), and open the new file.
43. Note that on the category subsection of the symbol tab there is file associated to
the symbols that you have generated. Click on that and you should see HA as one
of the symbols. Add a HA symbol to your design.
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44. Right click on the HA symbol and select Symbol/Push Into Symbol. You will see
your original HA design.
45. Close the HA schematic and complete the FA (Full Adder) circuit as depicted in
Figure 24. Check the schematic and save the file.
Figure 23
Figure 24
46. Create a new test bench (myFA_tb) and associate it with your FA schematic.
47. Apply all possible input combinations for inputs (a, b, Cin) and click on ‘Simulate
Behavioral Model. Make sure that generated simulation outputs are correct.
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48. Open the user constraint file that you had generated for HA before. Save a copy as
your FA ucf. Remove the UCF associated withe the half adder.
49. Add in and edit the FA constraint file. Note that for a FA you need another input
(Cin), thus add a new line in your constraint file and assign SW2 as the Cin input.
The resulting constraint file should be similar to Figure 25. (You can also create
the full adder ucf file by editing the HA ucf in a text editor.)
50. Save the constraint file, select FA schematic file and click on ‘Configure Device’
on the process view.
Figure 25
51. You will observe some errors on the console. Scroll through the errors and you
will notice that the compiler is complaining that there is not an IO marker with the
name ‘Sum’ in your FA design. It was called S instead. To correct this error you
need to either rename the output port in your schematic or change your constraint
file so that the match.
52. Save all. Do the Post Route simulation.
53. Generate the bit file and download it to the board and make sure that it works
correctly. Demonstrate your Full- Adder to a TA for sign-off CREDIT.
54. Create a new symbol for your FA implementation and add it to your personal
library, as you did for the HA (Figure 26).
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Figure 26
Multi-bit Full Adder
55. Continuing with hierarchical methods presented for the Full Adder. Use you
myfulladder component to create a 4 bit adder.
56. Just like decimal addition the Carry Out from one digit is the Carry in for the next
most significant digit.
57. You will need to use SW0-SW3 for A0 to A3 and SW4-SW7 for the B0 to B3.
Display your output result Sum0 to Sum3 on LD0 toLD3 with LD4 displaying the
Cout of the MSB. See page 8 of the Nexys2 Reference Guide for the pin
designations.
58. Create an appropriate User Constraint file by editing the ucf file from your fulladder
59. Demonstrate your Multi-bit Adder to a TA for sign-off CREDIT.
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Summary




You should be able to describe a Design flow for digital systems
You learned how to use Xilinx Webpack tools to enter a design, synthesize and
download your implementation to a target board
You learned how to use ISE Simulator to create stimulus signals, verify functional
and timing behavior of a digital system.
You learned how to use a hierarchical strategy in your designs in order to be able
to reuse your work
ALL TEAM MEMBERS SHOULD SAVE THIS PROJECT TO YOUR M:/
DRIVES RIGHT NOW!!!
References
[1]
Xilinx, ‘Nexys2 Starter Kit Board Reference Manual’
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