ECE3434
Simulation Exercise 1
Current mirrors
Version 1.4
The current mirror is a subcircuit that finds use in the more advanced circuits topologies. It may serve as
a bias source, as an active load, or as a transconductance conveyor. It provides an improved performance
stability to the supported circuit as a fixed source with low output conductance, not inconsistent with that
of the ideal current source
The basic current mirror construct is represented by figure 1.1. In this figure, R1 and Q1 represent a
reference string, carrying current IR. Since the collector and base of Q1 are connected Q1 acts as a ‘diode
equivalent’ with a VBE bias that can be shared with Q2. Since the VBE is the same for both Q1 and Q2,
then the current through Q2 is a “mirror” of that through Q1.
Figure 1.1 The simple BJT current mirror
An identical topology exists for FETs. The current mirror is an integral subcircuit within almost all
CMOS analog integrated circuit designs. The simplest of these topologies is indicated by figure 1.1, and
as such it is usually called the ‘simple current mirror’.
The current through Q1 is usually identified as
I R  (VS  0.7) / Rx
(1.1)
where it is assumed that the voltage across Q1 is approximately 0.7V, the nominal junction diode level.
The value VJUNCTION = 0.7V is an approximation. Reality (or simulation) will likely reflect a mildly
different voltage level, and so equation (1.1) is not precise, but is ‘good enough’. If Vs >> 0.7V, then IR
would be approx VS/Rx.
If transistor Q2 is a size factor K relative to Q1, then the current (IO = IC2) sourced by Q2 is
I C 2  K  I R (1   )  KI R
(1.2)
where  is defined as the defect factor, and is of value
  (1  K )  F
(1.3)
for which  F is the forward current gain of the (BJT) transistor(s). Since  F is nominally large, (on the
order of 100), the defect factor is usually small.
Since the output is taken at the collector node of Q2, the output resistance is
R0  r0  V AF / I C 2
(1.4)
An additional constraint on the current mirror as a functional subcircuit is the minimum voltage at the
output, sometimes called the compliance floor V = VCE(min), or sometimes just referred to as the voltage
compliance. For the BJT this is nominally 0.3V.
1. (a) (10 pts) As your first exercise, set up the simple current mirror of figure 1.1, using the transistor
and values indicated by the figure. Make a screen snapshot of your schematic (similar to that represented
by figure 1.1 above) and identify it as your figure 1.1.
(b) (10 pts) With Rx = 100k and  F = 135 (nominal value at current level of interest), calculate IO,
RO, , and the compliance V as identified by the formulae (1.) thru (1.4). Note that K = 1 in this
instance. Indicate these (analytical) results in a short table as your Table 1.1. For the value of VAF
associated with the Q2n3904, (1) highlight the transistor, and (2) pull up the menu Edit > Model > Edit
instance Model, and you will see the complete set of SPICE parameters for the 2n3904 transistor, to
include VAF (the forward Early voltage).
(c) (20 pts) Under the Analysis > setup menu set up the DC sweep for linear sweep of VDC source
Vtest, and sweep Vtest linearly from 0 to 5.0V at a .01V increment. Execute the simulation and make a
screen snapshot (figure 1.1a) of the plot of outputs IR (current through R1)and IC2. Using your cursor
measure IO as the level of current IC2 at VCE approx 0.3V, and determine the defect factor  from this
measurement and the value of IR (take ratio IR/IC2 and subtract 1.0). Add these to your table 1.1 as a
second line of entries, as your simulated results, for comparison to the analytical results.
Delete the traces for IR and IC2 and call forth a trace of D(Vtest)/D(IC2). Using your cursors determine
the compliance V and the output resistance RO, and enter these values in your table 1.1 for comparison to
the analytical values. Make a screen snapshot of this figure (including your cursor coordinates) as your
figure 1.1b.
2. (30 pts) Set up a modified form of figure 1.1, as represented by figure 1.2. Note that this figure is
essentially the same as that of figure 1.1 except that the output transistor is 5 times (K = 5) the size of the
reference transistor Q1. Repeat the same sequence of measurements as accomplished by part 1, except
with IO = -I(Vtest) (note that your are treating the transistor string Q2 – Q6 as a single transistor when
you do so.) You should end up with three more figures (please be concise) and another table.
Figure 1.2 Simple BJT current mirror with K = 5.
3. (30pts) With figure 1.2 as your (continued) test platform, invoke the Analysis >Parametric option
with Rx set as a global parameter. Step Rx from 100 ohms to 10Meg, one point per decade (be sure to set
the decade option). Then repeat the measurements of part 1, representing your results as a comprehensive
table (your Table 1.3). Show screen snapshots of your outputs as curve families, with the levels on a
logarithmic scale (accomplished by toggle of the appropriate icon). If you can find a technique to display
the characteristic quantities IO, RO, , and the compliance V on a set of pspice plots, then do so (Hint:
Make use of the ‘Performance Analysis’ option.
*Note: In order to show I(Vtest) on a logarithmic scale it may be necessary to sweep Vtest from .05V to
3.0V to avoid zero or negative values of I(Vtest).