Suggesting a Method for Determinig Switching
Angles of Multilevel Inverters to eliminate
Selected Current Harmonics of 3-Phase Induction
Motor
Bahram Ramezani
ramezani@m-iau.ac.ir
Islamic Azad University Miyaneh Branch, Miyaneh, Iran

Keywords: Multilevel Inverter, Total Harmonic
Elimination, Selective harmonic Elimination
Abstract
I. Introduction
Current harmonics has attracted growing interest
with the increase in use of static power converters.
These converters produce distorted current and
voltage waveforms. The result is harmonic
pollution that degrades the power quality. One of
the biggest problems in power quality aspects is the
current harmonic contents in the electrical system.
Current harmonics is usually generated by
harmonics contained in voltage supply and depends
on the type of load such as resistive load, capacitive
load, and inductive load (Bhagwat and Stefanovic,
1983; Salzman et al., 1993; Zeng, 2001; Zhang,
2000; Dahidah and Agelidis, 2009). Load
harmonics can cause the overheating of the
magnetic cores of transformer and motors. Source
harmonics are mainly generated by power supply
with non-sinusoidal voltage waveform. Voltage and
current source harmonics imply power losses,
Electromagnetic Interference (EMI) and pulsating
torque in AC motor drives. There are two practical
ways by which the harmonic content can be
brought down to a low value or at least within
acceptable limits. One method is to use a filter
circuit on the output side of the inverter. The filter
Recently, multilevel inverter technology has
emerged as a very important alternative in the area
of high-power medium-voltage energy control. In
this paper, the 3 and 5-level Voltage Source Inverter
(VSI) is designed and simulated. This Paper
contributes towards the detailed design, simulation
and analysis of 3 and 5-level Diode Clamped
Inverter (DCI). This paper presents speed control of
three phase induction motor fed by 3 and 5-level
VSI. Then the Current waveform, speed waveform
and Electromagnetic Torque waveform are shown.
Moreover the current harmonics is simulated and
analysed. This paper offers the Selective Harmonics
Elimination Pulse With Modulation (SHEPWM)
technique to control multilevel DCI switching. By
applying this method, the current selective
harmonics are eliminated. Also, using this technique,
the Total Harmonics Distortion (THD) of current
waveform is reduced. It is shown that by using the
suggested switching strategy within 3 and 5-level
inverter, the THD of current would be very low
than condition we use traditional two-level inverter.
1
circuit will, of course, have many disadvantages
like, it should handle the large power output from
the inverter, and it has to carry high currents so the
cost and size will be more. The second scheme
employs a pulse width modulation strategy that will
change the harmonic content in the output voltage
in such a way that the filtering needed will be
minimal or zero depending on the type of
application (Lai and Peng, 1996; Meynard and
Foch, 1993; Rodriguez, 2002). This technique
based on a suitable designed switching strategy
within inverter. Traditional 2-level high-frequency
pulse width modulation (PWM) inverters for motor
drives have several problems associated with high
frequency switching, which produce commonmode voltages and high voltage change (dv / dt )
rates to the motor windings. Some other noticeable
drawbacks of conventional 2-level PWM inverter
are:
1. Switching losses will be more,
2. Switches must have very low turn-on and
turn-off times,
3. Large (dv / dt ) rating,
4. Problem in voltage sharing in series
connected devices, and
5. Higher order harmonics will be introduced.
9. elimination of the problem of unequal
device ratings,
10. capacitor voltage balancing along with
significant reduction in Device Count.
Another important feature of multilevel
converters is that the semiconductors are wired in a
series-type connection, which allows operation at
higher voltages. However, the series connection is
typically made with clamping diodes, which
eliminates overvoltage concerns. Furthermore,
since the switches are not truly series connected,
their switching can be staggered, which reduces the
switching frequency and thus the switching losses.
Fig.1 shows the general structure of the multilevel
converter system. In this case, a three-phase motor
load is shown on the AC side of the converter.
Generally, variable-speed induction motor employs
the inverter as power-varying component
(Tipsuwanporn et al., 2006; Carbone and
Scappatura, 2005).
Because of these shortcomings of conventional 2level inverter, there is need to develop more
efficient and high power inverter. Multilevel
inverters have found better counterpart to the
conventional 2-level pulse width modulated
converter. Multilevel power conversion, introduced
in 1981 (Nabe et al., 1981). Main features of
multilevel inverters are (Tolbert and habetler, 1998;
Lalla, 2003; Li et al., 2000):
1. less switching stress on devices,
2. high voltage & high power capability,
3. reduced harmonic contents without
increasing switching
frequency or
decreasing the inverter power output,
4. no need of extending the device rating,
5. reduced switching losses,
6. reduced (dv / dt ) ,
7. reduced (or even eliminated) common
mode voltages,
8. good electromagnetic compatibility (EMC),
Fig.1: Multi Level Inverter Structure.
The fundamental multilevel inverter topologies
are diode-clamped, flying capacitor, cascaded Hbridge and multilevel H-bridge (Hosseini and Fathi,
2006; Corzine and baker, 2002). Diode clamped
multi-level inverter is a very general and widely
used topology for real power flow control and is
considered for investigation purpose in this paper.
The three-level diode clamped inverter is shown in
Fig. 2(a). Comparing this topology with that of a
standard two-level converter, it can be seen that
there are twice as many GTOs as well as added
2
diodes (Choi et al., 1991; Corzine and Wielebski,
2003). When three level compared with the twolevel converter, the additional voltage level allows
the production of line-to-ground voltages with
lower harmonic distortion. Selective harmonic
elimination pulse-width modulation methods
remain of great interest for the control of highvoltage high-power voltage-source converters (Xu
and Agelidis, 2007; Agelidis, 2005). This paper
presents a method to control of inverter that by
applying it we can reduce the THD of current and
the switching losses.
D1
S 2
S 2
balances out the voltage sharing between S1 and
with S1 blocking the voltage across C1 and
blocking the voltage across C2 . Notice that
output voltage van is ac, and vao is dc. The
difference between van and vao is the voltage
across C2 , which is Vdc / 2 . If the output is removed
out between a and o , then the circuit becomes
a dc/dc converter, which has three output voltage
levels: Vdc , Vdc / 2 , and 0 (Rodriguez, 2002). In
this paper, a three-level DCI was designed and
simulated using Matlab/Simulink. This simulated
waveform is shown in Fig. 3. The switching pulses
II. Three Level Diode – Clamped Inverter
A three-level diode-clamped inverter is shown in are shown in Fig. 4, and the output waveform is
Fig. 2(a). In this circuit, the dc-bus voltage is split shown in Fig. 5.
into three levels by two series-connected bulk
capacitors, C1 and C2 . The middle point of the two
capacitors n can be defined as the neutral point. The
output voltage has three states:  Vdc / 2 , 0 , and
 Vdc / 2
For voltage level  Vdc / 2 , switches S1 and
S 2 need to be turned on; for  Vdc / 2 , switches
S1 and S 2 need to be turned on; and for the 0
level, S 2 and S1 need to be turned on. The key
components that distinguish this circuit from a
conventional two-level inverter are D1 and D1 .
These two diodes clamp the switch voltage to half
the level of the dc-bus voltage.
Fig. 3: The simulated waveform of 3-level DCI
using Matlab/Simulink
Fig. 2: (a) Three Level DCI, (b) Five Level DCI.
When both S1 and S 2 turn on, the voltage
across a and 0 is V , i.e., vao  Vdc . In this case,
dc
3
Fig. 4: The switching pulses of: (a)
S1 , (d) S 2 .
lower switches S1  S 4 .
S1 , (b) S 2 , (c)
In this paper a five-level DCI was design and
simulate in Matlab/Simulink. The out put
waveform of inverter is shown in Fig. 6.
Fig. 5: The out put waveform of three level DCI.
III. Five Level Diode – Clamped Inverter
Fig. 2(b) shows a five-level diode-clamped
converter in which the dc bus consists of four
capacitors, C1 , C2 , C3 and C4 . For dc-bus
voltage Vdc , the voltage across each capacitor is
Fig. 6: The output waveform of five level DCI.
Vdc / 4 , and each device voltage stress will be
limited
to
one
capacitor
voltage
IV. Selective Harmonic Elimination Method
level
Pulse width modulation (PWM) techniques are
utilized to achieve high quality output voltage
waveforms of desired amplitude and frequency
which are as close as possible to sinusoidal wave.
Any deviation from the sinusoidal wave shape will
results in harmonic currents in the load which result
in electromagnetic interference (EMI), harmonic
losses and torque pulsation in case of motor drives.
The quality of the output waveform will improve
with increase in switching frequency. Higher
switching frequency can be utilized only for low
power levels, as managing the switching losses at
high power levels will be a difficult task. SHE is an
off-line method that the suitable switching angels
should be calculated.
Vdc / 4 through clamping diodes (Rodriguez, 2002).
To explain how the staircase voltage is synthesized,
the neutral point n is considered as the output phase
voltage reference point. There are five switch
combinations to synthesize five level voltages
across a and n .
1.
2.
For voltage level
upper switches S1
Van  Vdc / 2 ,
turn on all
 S4 .
For voltage level Van  Vdc / 4 , turn on
three upper switches S 2  S 4 and one
3.
lower switch S1 .
For voltage level
Van  0 ,
turn on two
upper switches S 3 and S 4 and two lower
4.
5.
V. Applying Selective Harmonic Elimination
Method to Design & Simulate ThreeLevel DCI
Selective
Harmonic Elimination (SHE) is an offone upper switch S 4 and three lower
line (precalculated) non carrier based PWM
switches S1  S 3 .
technique. In this method the basic square-wave
For voltage level Van  Vdc / 2 , turn on all output is "chopped" a number of times, which are
obtained by proper off-line calculations. The
switches S1 and S 2 .
For voltage level Van  Vdc / 4 , turn on
4
b3  cos 31  cos 3 2  cos 3 3  0
SHEPWM technique is used to synthesize an
output waveform of 3-level diode clamped
multilevel inverter (Fig. 7).
b5  cos 51  cos 5 2  cos 5 3  0
( eq.3 )
b7  cos 71  cos 7 2  cos 7 3  0
The obtained angles after solving the equations,


by using the Matlab program are 22 , 38 and 47 .
The statuses of output waveform are Shown in eq 4.
0  t  1

for : 
  t  
3
 2
 1  t   2

for : 
  t    
3
 3
   3  t     2

for : 
    t  
1

Fig. 7: The output voltage waveform of a threelevel DCMI with SHEPWM technique.
Now fourier series is being developed for the
above waveform. Let N be the number of switching
angles per quarter-cycle. The output waveform is
assumed to be odd quarter wave symmetry, whose
amplitude equals E. Because of odd quarter-wave
symmetry, the dc component and the even
harmonics are equal to zero. Fourier series of the
SHEPWM is as follows (Li et al., 2000):
( eq.4 )
In this paper, for controlling exact inverter
switches, 4 blocks in Matlab/Simulink program
were designed. Using these blocks, we could
switch the switches ( S1 , S2 , S1 , S2 ) correctly. The
4E N
 (1) K 1 cos(nak ) ; for odd n
n k 1
 k is the switching angles, which must satisfy the
blocks that generate switching pulses for S1 and
following condition:
1   2   3  ....   N   / 2
S 2 are shown in fig. 8 and Fig. 9. Also, the blocks
For S 2 and S 2 switches were designed.
E is the amplitude of the dc source, and n is the
harmonic order. The nonlinear equation system of
SHEPWM waveform can be written as follows:
cos( 1 )  cos( 2 )  .........  cos( N )  ( / 4)  M
cos(3 1 )  cos(3 2 )  ....  cos(3 N )  (3 / 4)  (h3 / E )
( eq.2 )
cos(5 1 )  cos(5 2 )  ...  cos(5 N )  (5 / 4)  (h5 / E )
M is the modulation index, and
E
V out 0
( eq.1 )
n 1
an 
V out  E
   1  t     2

for : 
V out  E
    t  2  
3
3

2   3  t  2   2

for : 
V out 0
2    t  2
1


VOUT (t )   a n sin( nt )
V out 0
M  h1 / E
,
Vdc
m 1 ,
where Vdc is supply voltage and 'm' is
number of levels. For eliminating the 3rd, 5th and 7th
harmonics of phase current the equation 3 should
be solved.
5
Fig. 10: The output phase waveform of three level
inverter applied with SHEPWM technique.
Fig. 8: The block that generates switching pulses for S1 .
Fig. 11: The output line-line waveform of three
level inverter applied with SHEPWM technique.
Utilizing this three level inverter applied with
SHEPWM technique, as power supply to feed a
three phase induction motor, the current waveform
improved. Also, the THD of current decreased
considerably. The phase current waveform and
THD of it are shown in Fig. 12.
Fig. 9: The block that generates switching pulses
for S1 .
Applying 2 / 3(rad ) and 4 / 3(rad ) phase shifting
to these blocks, we could use them as switching
pulses for phases (b) and (c). By generating and
applying these blocks to control inverter, we could
eliminate the 3rd, 5th and 7th current harmonics. The
output waveform of the three level inverter applied
with SHEPWM technique, is shown in Fig. 10. The
line to line output waveform is shown in Fig. 11.
Fig. 12: (a) The phase current waveform of Induction
Motor Fed by 3-level Diode Clamped Inverter
6
(SHEPWM technique), (b) The THD of current
Waveform
The phase current waveform (ias ) , Speed of rotor
waveform (r ) and Electromagnetic Torque
waveform
(Tem )
Method to Design & Simulate Five-Level
DCI
Also, as mentioned in section V, Fourier series of
the SHEPWM is as follows:

are shown in Fig. 13.
VOUT (t )   a n sin( nt )
( eq.1 )
n 1
an 
4E N
 (1) K 1 cos(nak ) ; for odd n
n k 1
The half waveform of five level inverter is shown
in Fig. 15.
Fig. 15: The output voltage waveform of a fivelevel DCMI applied with SHEPWM technique.
Fig. 13: (a) The phase current waveform, (b) Speed
For eliminating the 3rd, 5th, 7th, 9th, 11th and 13th
of rotor waveform (c) Electromagnetic Torque
harmonics of phase current, the equation 5 should
waveform.
be solved.
According to the Fig. 12, the THD of current
waveform could be reduced 17.6%. This amount
b3  cos 3 1  cos 3 2  cos 3 3  cos 3 4  cos 3 5
was achieved 46% for two level inverter. Fig. 14
 cos 3 6  0
shows
the
amounts
of
b  cos 5  cos 5  cos 5  cos 5  cos 5
5
( Mag .( H n ) / Mag .( H1 )), ( for 1  n  60) . Fig.
1
2
3
4
5
 cos 5 6  0
14
shows that the 3rd, 5th and 7th harmonics were
eliminated.
b7  cos 7 1  cos 7 2  cos 7 3  cos 7 4  cos 7 5
 cos 7 6  0
b9  cos 9 1  cos 9 2  cos 9 3  cos 9 4  cos 9 5
 cos 9 6  0
b11  cos 11 1  cos 11 2  cos 11 3  cos 11 4  cos 11 5
 cos 11 6  0
b13  cos 13 1  cos 13 2  cos 13 3  cos 13 4  cos 13 5
 cos 13 6  0
( eq.5 )
The obtained angles after solving the equations,
by
using
the
Matlab
program,
are






5 , 11 , 20 , 49 , 58 and 64 . Applying these
switching angles for controlling inverter switches,
the 3rd, 5th, 7th, 9th, 11th and 13th harmonics were
eliminated. The output waveform of the five level
inverter applied with SHEPWM technique, is
shown in Fig. 16. The line to line output waveform
is shown in Fig. 17.
Fig. 14: The amounts of ( Mag .( H n ) / Mag .( H1 ))
( for 1  n  60)
VI. Applying Selective Harmonic Elimination
7
waveform could be reduced to 7.1%. This
amount achieved 46% for two level and 17.6% for
three inverter. Fig. 19 shows the amounts of
( Mag .( H n ) / Mag .( H1 )), ( for 1  n  60)
. Fig. 16 shows
that the 3rd, 5th, 7th, 9th, 11th and 13th harmonics
were eliminated.
Fig. 16: The output phase waveform of five level
inverter applied with SHEPWM technique.
Fig. 19: The amounts of ( Mag .( H n ) / Mag .( H1 ))
Fig. 17: The out put line - line waveform of five
level inverter applied with SHEPWM technique.
The phase current waveform and THD of it, are
shown in Fig. 18.
( for 1  n  60)
VII. Conclusions
In this paper, the 3 and 5-level VSI were designed
and simulated. The paper contributed towards the
detailed design, simulation and analysis of 3 and 5level DCI. This paper presented speed control of
three phase induction motor fed by 3 & 5-level VSI.
Then the Current, speed and Electromagnetic
Torque waveforms were shown. The current
harmonics was simulated and analysed. In addition
to, this paper suggested the SHEPWM technique to
control Multilevel DCI switching. This strategy
was applied within 3 and 5-level inverter. In a
condition that the improved 3-level DCI fed the
three phase induction motor as power supply, the
3rd, 5th and 7th current harmonics were eliminated
and the THD of current waveform was reduced to
Fig. 18: (a) The phase current of Induction Motor Fed 17.6%. Also, in a case that induction motor fed by
by 5-level Diode Clamped Inverter (SHEPWM
improved 5-level inverter, the 3rd, 5th, 7th, 9th, 11th
technique), (b) The THD of current Wave form
and 13th harmonics of phase current were
eliminated and the THD of current waveform was
According to the Fig. 18, the THD of current reduced to 7.1%. The THD of current became 46%
8
in a condition that the traditional 2-level inverter
was used. With respect to the mentioned results, it
is concluded that by using this technique, the THD
of current waveform is reduced and also, according
to the decreasing of switching frequency the
switching losses is reduced.
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