SINGLE CHIP QPSK DEMODULATOR
Abstract:
This report is an honest attempt to elaborate the
method of digital implementation of coherent QPSK
Demodulator on single chip. The combination of
complexity and speed in designing QPSK
Demodulator is finding ready applications for VLSI
system. A single chip QPSK Demodulator is of great
interest in Wireless Communication, High frequency
space Communication and Set top boxes. Utmost
Care has been taken to reduce complexity & area of
the chip and to minimize required power &
probability of bit error by use of convolution coding.
The QPSK modulation scheme has been studied
thoroughly and the simulation results of MATLAB
implementation of QPSK Demodulator and Verilog
code for FPGA implementation of High speed
multipliers and Viterbi Decoder have been given for
the verification.
Fig.1 QPSK Modulation scheme
These waveforms correspond to phase shifts of 0º,
90º, 180º, and 270º between each other as shown
in the phasor diagram below:
Keywords:
1. QPSK Demodulation: It is the process of Digital
modulation in which two different stream of data
are transmitted simultaneously over the same
channel instead of single data stream as in the
case of binary phase shift keying (BPSK).
2. VLSI: Very Large Scale Integration.
3. Verilog: Commonly used Hardware Description
Language.
4. FPGA: Field Programmable Gate Array is a
method of implementing the VLSI design.
5. Booth Multiplier: Multiplier designed using
Booth’s Algorithm
6. CSD Multiplier: Multiplier designed using CSD
Algorithm.
7. Root Raised Cosine Filter: RRC filters are the
Match filters implemented using CSD multiplier.
8. Viterbi Decoder: It decodes the convolution
coded message using Viterbi Algorithm.
1.
Introduction:
Due to high Bandwidth efficiency of QPSK
modulation system it is preferred over other
system. In fact bit error rate is also at
considerable level. This QPSK scheme of
Modulation can be understood clearly by the
following diagram:
In four-phase PSK, one of four possible waveforms
is transmitted during each signaling interval Ts.
These waveforms are:
S1 (t) = A cos (ωct +/4)
S2 (t) = A cos (ωct +3/4)
S3 (t) = A cos (ωct +5/4)
S4 (t) = A cos (ωct +7/4)
for 0≤ t ≤Ts
For the above signal receiver requires two local
reference waveforms Acos (ωct + 45) and Acos (ωct
– 45) that are derived from a coherent local carrier
reference A cos(wct). For purposes of analysis, let
us consider the operation of the receiver during the
signaling interval (0,Ts). Let us denote the signal
components at the output of the correlators by S01
and S02, respectively, and the noise component by
N0(t). If we assume that S1(t) was the transmitted
signal during the signaling interval (0,Ts), then we
have
S01(Ts) = ∫ 0 to Ts(A cos ωct) A cos (ωct + П /4) dt
= A2/2 Ts cos(П /4) = L0
S02(Ts) = ∫ 0 to Ts (Acos ωct) A cos (ωct – П/4) dt
= A2/2 Ts cos П/4 = L0
OUTPUT
S01 (k Ts)
S02 (k Ts)
S1 (t)
L0
L0
INPUT
S2 (t)
S3 (t)
-L0
-L0
L0
-L0
S4 (t)
L0
-L0
SINGLE CHIP QPSK DEMODULATOR
two's complement numbers; the result is considered
as 2n-bit two's complement value. The overflow bit
(outside 2n bits) is ignored. Following flow-chart
describes the booth’s algorithm:
Fig.2 Block diagram of QPSK Demodulator
The digital implementation of QPSK demodulator is
achieved by sampling the coming modulated signal
using ADC of 8-bit precision. This digitized data is
given to high speed multiplier. Here we have used
the Booth’s Multiplier as the high speed multiplier
.The other multiplier input will come from the carrier
recovery circuit .this is also 8-bit data. This will pass
through the LPF filter which also digitally
implemented. The output of LPF will pass through
the Matched Filters. All the filters can be
implemented using the FIR filters. For that we have
designed Constant coefficient multiplier (CSD
multiplier). At last symbol timing recovery block
samples the output of match filter at a specific time
and hence we get the demodulated output.
Following diagram give functional details of QPSK
Demodulation scheme:
Fig.3 Booth’s Algorithm
Here is an example:
4 bits
0110 <- 6
x 0010 <- 2
-------------00000000
- 0110
-------------11110100
+ 0110
-------------(1)00001100 <- 12
8 bits
(overflow bit ignored)
3. RRC Filter
2. Booth’s Multiplier
High-speed multipliers are essential to design a
QPSK Demodulator with high data output rate. Here
we have used the Booth’s algorithm to implement to
design our multiplier. Booth's algorithm is a
multiplication algorithm, which worked for two's
complement numbers. It is similar to paper-pencil
method, except that it looks for the current as well
as previous bit in order to decide what to do. If the
time required for an addition or a subtraction is
sufficiently large, then a considerable gain in
performance can be obtained by keeping the
number of the additions to a minimum. In Booth's
algorithm, if the multiplicand and multiplier are n-bit
Inter-symbol interference (ISI) is an unavoidable
consequence of both wired and wireless
communication systems.
Amplitude
Time
Symbol Time
Amplitude
Time
Delay Spread
Fig.4 Inter symbol Interference
SINGLE CHIP QPSK DEMODULATOR
The main problem is that energy, which we wish to
confine to one symbol, leaks into others. So one of
the simplest things we can do to reduce ISI is to just
slow down the signal. Slowing down the data rate is
an easy but an unacceptable solution. The secret
lies in the digital demodulation process used. When
the timing pulse slices the signal to determine the
value of the signal at that instant, it does not care
what the signal looked like before or after it. So if
there was some way we could keep the symbols
from interfering in such a way that they do not affect
the amplitude at the slicing instant, we can counter
ISI successfully. For correcting the above said
problem we used Raised cosine filter. On going for
the digital implementation of raised cosine filter of
roll off factor 0.3 we have to go for the FIR model.
The impulse response sampled and stored in the
ROM in the 16 bit representation. This known as the
filter coefficients of the raised cosine filter. Now the
input 16-bit number will convolve with the impulse
response and 16 -bit number. Here the convolution
will be implementing by the delay, adder and high
speed multiplier.Using the Canonical Signed Digits
(CSD) number representation for filter coefficients is
a very effective way to increase the filter's speed
while reducing complexity in the digital filter
hardware design.
A. Binary to CSD conversion: In CSD form any
number is represented in ternary number system
that is [-1, 0, 1]. If B = (bn-1………………..b1b0) is
binary number than it’s CSD representation:
D = (dn-1…………….d1d0)
where di = bi + Ci – 2Ci+1 ;
Always we take C0 = 0;
And Ci+1 = bi + bi+1 + Ci ;
B. CSD Multiplier: In CSD multiplier only
multiplicand changes so first a RAM is used to store
multiplier data (16 bit). Because CSD system is a
ternary system so we have to use two-bit
combination for each ternary symbol.
Here we used
00 for 0
01 for 1
11 for –1
So we have to use a 2*16 RAM. Multiplicand data
are feed parallel in shift register. The clocks of both
shifters are same. After one clock address of
memory & multiplicand bit shift. These shifted bits
(from R.S.R) come to adder.
 If there is a combination of ‘01’ in RAM than
these shifted bit will be added in previous bit.
 If there is a combination of ‘11’ in RAM than
these shifted bit will be subtracted from previous
bit.

If there is a combination of ‘00’ in RAM than
these shifted bit will not be added or subtracted
in previous bit.
The ease of multiplying a number in a power of 2
makes it so much applicable for DSP. This
eliminates the need of multipliers, thus increasing
the speed of operation and reducing the power
consumption and space requirement.
4. Viterbi Decoder
Convolution coding with Viterbi decoding has been
the predominant FEC technique used in space
communications, particularly in geostationary
satellite communication networks, such as VSAT
(very small aperture terminal) networks. With this
code, we can transmit binary or quaternary phaseshift-keyed (BPSK or QPSK) signals with at least 5
dB less power than we'd need without it. This is
very useful in reducing transmitter and/or antenna
cost or permitting increased data rates given the
same transmitter power and antenna sizes. But
there's a tradeoff-the same data rate with rate 1/2
convolution coding takes twice the bandwidth of the
same signal without it, given that the modulation
technique is the same. That's because with rate 1/2
convolution encoding, we transmit two channel
symbols per data bit. However, if we think of the
tradeoff as a 5 dB power savings for a 3 dB
bandwidth expansion, we can see that we come out
ahead. If the modulation technique stays the same,
the bandwidth expansion factor of a convolution
code is simply n/k. Specification for the 5.4 dB gain
decoder:
 ½ Rate
 7 Constrained length
 64 state trellis diagram.
 35 decoder depth
 G0 (x) = 1 + x^1 + x^2 + x^3 + x^6.
 G1 (x) = 1 + x^1 + x^2 + x^3 + x^5
5. Verilog and design flow of HDL
Verilog is the Hardware description language
commonly used for the VLSI system design. VLSI
design for the high speed multipliers and viterbi
decoder was done in Verilog and XILINX was used
in order to generate the bit code for the FPGA
implementation of above system. Following is the
HDL design flow:
1. Code in Verilog is written.
2. Project is created.
3. Add HDL files to a project and analyze HDL
files.
4. Implement the design.
SINGLE CHIP QPSK DEMODULATOR
5. Enter Constraints.
6. Optimize the Design.
7. Write Out Detailed Design Report.
8. Write Out an XNF File, Place & Route.
6. Results & discussion
Matlab was used to check algorithm of full system. Following is the modulated output generated in
Matlab. After Matlab output are the waveform viewer for the CSD multiplier and Booth multiplier
respectively. The results displayed by the waveforms states the right functionality of our design.
7. Conclusion
QPSK demodulator design aspect is discussed
here. MATLAB simulation under gone for the
functionality check of different blocks of
communication system. XILINX is used here to
implement two high-speed multiplier in FPGA.
The simulation results are verified quiet with the
expectation. Though all blocks are not
implemented in this project. Only a part of Viterbi
Decoder is implemented. Different blocks like
SINGLE CHIP QPSK DEMODULATOR
DPLL and Timing recovery circuit can be
implemented in XILINX. This will give single chip
implementation of QPSK demodulator. Viterbi
decoder can be improved by the 3-bit soft
decoding. This will give the larger decoding gain
hence better performance.
8. References
1. G. Proakis, “Digital Communication “, Fourth
edition, 2001, McGraw – Hill International
Edition.
2. Gorden L Stuber,” Principles of Mobile
Communication”, Second Edition, 2001
3. Kamilo Feher,” Digital Communication,
Satellite and Earth Stations Engineering “,
1983, PHI
4. Jhon. B. Anderson, “ Digital Transmission
Engineering “, 1988, IEE press, Prentice Hall
5. Robert vs. Wall, “ QPSK and BPSK
Demodulator
Chip
set
for
Satellite
applications” IEEE transaction on Consumer
Electronics, pg: 30-41, Vol. 41, NO.1,
February, 1995
Single Chip QPSK Demodulator
Ashutosh Mundra, M.N.I.T. Jaipur
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