Creating a 12 x 8 MAC Using the
Xilinx CORE Generator
For Academic Use Only
Creating a 12 x 8 MAC Using the Xilinx CORE
Generator
Introduction
In this lab, you will create a 12-bit x 8-bit MAC (Multiplier Accumulator) using the Xilinx CORE
Generator and instante the MAC in a top-level VHDL file. This lab helps familiarize you with the
Xilinx CORE Generator and the Xilinx implementation tools by having you generate the MAC as
an IP core. This lab is completed using the Xilinx ISE 6 software. You will use a typical VHDL
flow to black-box (instantiate) the core into a top-level piece of VHDL code, run a functional
HDL simulation, synthesize your design with XST, and take the synthesized design through the
Xilinx implementation tools.
Note: For this lab, you do not need to know VHDL because the top-level VHDL file is provided.
There is a completed example in c:\xup\dsp_flow\labs\lab2\lab2_soln.
Objectives
After completing this lab, you will be able to:
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Generate a CORE Generator macro
Simulate a piece of VHDL containing a CORE Generator macro
Synthesize the VHDL and black-box instantiations using XST
Implement a synthesized design through the Xilinx implementation tools
Design Description
Use a CORE Generator to create a 12 x 8 MAC using VHDL that has the following behavior:
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Multiplier input data widths of 12-bits and 8-bits of signed data
Multiplier output width of 20 bits
Accumulator output width of 27-bits
Procedure
This lab comprises six primary steps: you will start the project navigator and open the project;
generate a 12x8 MAC core using the CORE Generator System; add the CORE Generator macro
into the provided VHDL code; simulate the design using ModelSim simulator; synthesize the
design using XST, and implement the design using ISE 6. Below each general instruction for a
given procedure, you will find accompanying step-by-step directions and illustrated figures
providing more detail for performing the general instruction. If you feel confident about a specific
instruction, feel free to skip the step-by-step directions and move on to the next general instruction
in the procedure.
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
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Note: If you are unable to complete the lab at this time, you can download the lab files for this
module from the Xilinx University Program site at http://university.xilinx.com
Start the Project Navigator and Open the Project
Step 1
Launch the ISE Project Navigator and open the mac_cgen project.
 Open the Xilinx ISE 6 software: Go to Start Menu  Programs  Xilinx ISE 6 
Project Navigator
 Open the mac_cgen project: In the Project Navigator, select File  Open Project
 Browse to c:\xup\dsp_flow\labs\lab2 using the pull-down arrow
 Open the mac_cgen folder and select the mac_cgen.npl project file
 Click OK
Generate a 12 x 8 MAC Using the CORE Generator
Step 2
Generate a 12 x 8 MAC by invoking the CORE Generator through the project.
Make sure that the input data are signed data and the output width is 27 bits
 Create a new source: select Project  New Source, or right-click, and choose New Source
Figure 12-1. Adding a New Source to an ISE Project
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
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 Select IP(CoreGen & Architecture Wizard), type my_mac in the File Name field, and
click Next
Figure 12-2. Adding a CORE Generator to Your ISE Project.
 Select Core Type dialog box will be displayed. Select Math Functions
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
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Figure 12-3. Selecting Core Type.
 Expand Math Functions
 Expand Multiply Accumulators
Figure 12-4. Selecting Multiply Accumulators function.
 Select second multiplier entry which is for version 3.0 MAC and click Next button
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
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Figure 12-5. Selecting correct version of the Multiplier Accumulator.
 Fill in the following options on Page 1 of 3 for the Multiply Accumulators GUI and click
Next to continue
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Component Name: my_mac
Number MAC Cycles: 92
Clock Rate: 100.0
Port A Width: 12 bits, Type: Signed
Port B Width: 8 bits, Type: Signed
Select Display Core Footprint (bottom right of the GUI)
Figure 12-6. Multiplier Accumulator Options Page 1 of 3.
 Fill in the following options on Page 2 of 3 and click Next to continue
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Result Width: 27
Output Register: deselect
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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Rounding Operation: select Truncation
Reset: select
Clock Enable: deselect
Create RPMs: select
Figure 12-7. Multiplier Accumulator Options Page 2 of 3.
 Select the following parameters on Page 3 of 3 and click Generate
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Pipeline Control: select Automatic Pipelining
Multiplier Implementation: select LUT Based
Display Core Footprint: checked
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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Figure 12-8. Multiplier Accumulator Options Page 3 of 3.
 You will see a pop-up window indicating that the my_mac core was generated successfully.
Click OK to invoke the Core Viewer
Fill in the following information from the Core Viewer window
 The shape of the generated core should look like the following
Figure 12-9. Core Viewer of the Multiplier Accumulator.
?
1. Fill in the following information from the Core Viewer window:
Number of CLB wide:
Number of CLB tall:
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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Number of slices:
 Close the Core Viewer and the Core Generator by clicking the DISMISS button
Note: For a detailed explanation of the output files, please see the documentation Help 
Online Documentation  CORE Generator Guide, Chapter 3 Using the CORE Generator.
The section listing inputs and outputs will thoroughly describe the input and output files
Note: A my_mac.xco file will be added to your project in the mac_cgen hierarchy
Adding the CORE Generator Macro into VHDL Code
Step 3
Using the ISE Language Template, instantiate the multiply accumulator macro,
my_mac, into the supplied top-level VHDL file mac_cgen.vhd
 Double-click the VHDL file mac_cgen.vhd in the Sources in Project window
 Open the Language Template by clicking on icon
Template
or select Edit  Language
 Expand the Coregen  VHDL folder, and select the my_mac template
The template similar to shown below appears:
Figure 12-10. Selecting the my_mac template.
 Using the template, add the component declaration between the architecture and begin
statements as indicated in the mac_cgen.vhd file
 Using the template, add the instance of the my_mac in the mac_cgen.vhd file
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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 Change the instance name to U2
 Connect RST and CLK pins of my_mac to appropriate signals
 Check the syntax and correct any errors before proceeding to the next step
Simulate the Design Using MTI
Step 4
Simulate your core using the provided testbench to verify it is functioning
correctly. You should not have any errors, though warnings are okay.
 Select the mac_cgen_tb.vhd file in the Sources in Project window
 Expand ModelSim Simulator in the Processes for Current Source window
 Double-click Simulate behavioral VHDL Model
 Verify the operation of the MAC by viewing in the wave window, the input and output
signals of the testbench *_tb
 After verifying that the MAC is operating properly, close ModelSim Simulator
Synthesize the Design Using XST
Step 5
Synthesize the mac_cgen.vhd design using Xilinx Synthesis Technology (XST)
tool with default options
 Remove the my_mac.xco file from the project.
 Select the mac_cgen.vhd file in the Sources in Project Window
 Run synthesis: Right-click Synthesis in the Processes for Current Source window and
select the Run option
 If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click
and choose the View option
 Fix any errors and re-synthesize, otherwise continue on to the next step
Implement the MAC design
Step 6
Implement your mac_cgen.vhd design using Xilinx implementation tools and
view the Post-place & Route Static Timing Report. Make sure that the settings
are as follows
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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Device Family: Virtex2P
Device: xc2vp4
Speed Grade: 7
Package: FG456
 Right-click Implement Design, and choose the Run option, or double left-click Implement
Design
?
2. Which netlist files do the Xilinx implementation tools use for the my_mac black
box?
 View the placed design in the FPGA Editor by selecting View/Edit Routed Design (FPGA
Editor) under the Place and Route
Figure 12-11. Opening the FPGA Editor.
 Close the FPGA Editor when you are finished
 Use the place and route report and Text Based Post Place & Route Static Timing Report
files:
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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?
3. Fill in the information requested below.
Number of Slices:
Number of BUFGMUXs:
Number of external IOBs:
Maximum clock frequency:
We will be using this information to compare with the results of the VHDL and the System
Generator results.
Creating a 12 x 8 MAC
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Conclusion
In this lab, you learned the basic design flow involved in incorporating the CORE Generator
macros into a VHDL code. You generated a CORE Generator macro, and then simulated a design
that contains CORE Generator macros, and then synthesized a design that contains CORE
Generator macros using synthesis using XST. You ran a synthesized design that contains CORE
Generator macros through the Xilinx implementation tools, and viewed how the core is
implemented using the FPGA Editor.
A
Answers
The Core Viewer Result:
Figure 12-10. Core Viewer Results.
1. Fill in the following information from the Core Viewer window:
Number of CLB wide:
Number of CLB tall:
Number of slices:
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
5
8
84
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2. Which netlist files do the Xilinx implementation tools use for the my_mac black
box?
my_mac.edn (EDIF) netlist file which is generated by the CORE Generator
3. Fill in the information requested below.
Number of Slices:
Number of BUFGMUXs:
Number of external IOBs:
71
1
52
Maximum clock frequency:
~ 180 MHz
Creating a 12 x 8 MAC
Using the Xilinx CORE Generator
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For Academic Use Only
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