Embedded Design Flow Workshop

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README
v9.1 DSP Design Flow Workshop
Spartan-3E Starter Kit
COURSE DESCRIPTION
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and
implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions
focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator
software, and design implementation tools. Through hands-on exercises, you will implement a design from
algorithm concept to verification.
PREREQUISITES
 Fundamentals of MATLAB/Simulink and Xilinx FPGAs
 Basics of digital signal processing theory for functions such as FIR (Finite Impulse Response) filters
WORKSHOP GOALS
 Learn how to implement a DSP design without having to be an FPGA expert
 Become comfortable using System Generator to develop lectures & labs, or implement research
projects.
SKILLS GAINED
 Understand the strengths and weaknesses of three design flows (HDL, CORE Generator, System
Generator)
 Make a decision regarding which design flow is more appropriate based on needs and FPGA expertise
 Understand the impact of some decisions made in the Simulink environment based on the resulting
size of the FPGA design
 Debug and optimize a design in the Simulink environment
REQUIREMENTS
The workshop has been tested on a PC running the Windows XP Professional operating system.
Software
V9.1 System Generator for DSP
V9.1i ISE Foundation Software + latest SP
Additional System Requirements


1-2 Gigabytes of RAM
Write permissions to project
directories and ISE installation
Mathworks release r2006a or r2006b
(includes Matlab/simulink)
Mathworks Signal Processing blockset
Hardware
Spartan-3E Starter Kit (includes power
supply)
Standard USB cable for FPGA configuration
Xilinx Donation
Yes
Yes
No
No
Additional System Requirements
USB port on PC
COURSE OUTLINE
Day 1 Agenda
Introduction
DSP Design Flows in FPGA
Lab 1: Creating a 12x8 MAC using System Generator for DSP
Lab 2: MAC FIR Filter Verification using HDL Co-Simulation
Day 1 Materials
01intro.ppt
02flows.ppt
11lab01.doc (lab 1 instructions)
/labs/lab1 (lab 1 “user” directory)
/labsolutions/lab1 (lab 1 solutions)
12lab02.doc (lab 2 instructions)
/labs/lab2 (lab 2 “user” directory)
README
Digital Filters
Lab 3: Designing an FIR filter
Day 2 Agenda
Looking under the hood
Lab 4: Looking under the hood
Controlling the system
Lab 5: Controlling the system
/labsolutions/lab1 (lab 1 solutions)
03filters.ppt
13lab03.doc (lab 3 instructions)
Day 2 Materials
04hood.ppt
14lab04.doc (lab 4 instructions)
05control.ppt
15lab05.doc (lab 5 instructions)
Multi-rate systems
Lab 6: Designing a MAC FIR
06multirate.ppt
16lab06.doc (lab 6 instructions)
LAB DESCRIPTION
Lab 1: Brief introduction to Simulink; Overview of quantization and overflow; Create a 12 X 8 MAC using
System Generator for DSP
Lab 2 : Generate an HDL function using Core Generator; Import the function into System Generator for
DSP using the black box block; Perform HDL co-simulation using the ISE Simulator; Test the function in
hardware on the XUP board via JTAG co-simulation
Lab 3: Use the FDA Tool to generate coefficients for a low-pass filter; implement low-pass filter using DA
FIR filter block from System Generator; simulate with white noise and test in hardware via JTAG cosimulation
Lab 4: Observe the effects in hardware when changing quantization and overflow parameters
Lab 5: Create an address generator using 1) basic System Generator blocks, and 2) m-code block
Lab 6: Using the design in lab 5, you will create a 92-tap MAC based FIR filter; you will simulate the filter
with white noise and verify in hardware via JTAG co-simulation
DIRECTORY STRUCTURE
Description
Directory
Lecture Slides
C:/xup/dsp_flow/slides/ (.ppt files listed in course outline)
Lab Exercises
C:/xup/dsp_flow/lab_docs/ (.word docs listed in course outline)
“user” directories
C:/xup/dsp_flow/labs/(lab1, lab2, lab3, lab4, lab5, lab6)
Lab solutions
C:/xup/dsp_flow/labsolutions/(lab1, lab2, lab3, lab4, lab5, lab6)
XUP SPARTAN-3E BOARD SUPPORT
To enable hardware-in-the-loop support via JTAG co-simulation with the Spartan-3E Starter Kit, unzip the
plugins.zip file in the plugins directory of the System Generator for DSP install path as follows
Unzip to C:\MATLAB704\toolbox\xilinx\sysgen\plugins
So that the following sub-directory is created
%MATLAB%\toolbox\xilinx\sysgen\plugins\compilation\Hardware Co-Simulation\xup\sp3e_starter_kit
The following files appear in this new subdirectory:
 spartan_3e_starter_kit.ucf
 spartan_3e_starter_kit.xml
 spartan_3e_starter_kit _libgen.m
 spartan_3e_starter_kit _postgeneration.m
 spartan_3e__starter_kittarget.m
 xltarget.m
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