8
Timing Reports
Learning Objectives
After completing this lab, you should be able to:
• Interpret various timing reports generated by
report_timing
Lab Duration:
45 minutes
Timing Reports
Synopsys 31833-000-S38
Lab 8-1
Lab 8
Timing Reports Exercise
Task 1.
1.
Start dc_shell-t, and read the mapped/PRGRM_CNT_TOP.db file you saved
from the previous lab.
Task 2.
1.
Load Mapped PRGRM_CNT_TOP Design
Generate and Interpret Four Timing Reports
Answer the following questions regarding PRGRM_CNT_TOP.
Question 1.
Are there any unconstrained timing paths in
PRGRM_CNT_TOP? (Use the command check_timing to
verify unconstrained timing paths. Look up a man page for
this command.)
....................................................................................................
Question 2.
How many path groups are in PRGRM_CNT_TOP? (Use the
command report_path_group)
....................................................................................................
2.
At the dc_shell-t prompt, run the following reports:
redirect reports/default_timing.rpt {report_timing}
redirect reports/pins_timing.rpt \
{report_timing -input_pins –sig 6}
The switch –significant_digits 6(shorten to –sig 6)
increases the number of digits in the timing report.
redirect reports/nets_timing.rpt {report_timing –nets}
redirect reports/min_timing.rpt \
{report_timing -delay min}
Because the design is rather small, you might consider running the
reports interactively without redirecting them into a file.
Lab 8-2
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8
3.
Open the first report file, reports/default_timing.rpt, and answer the
following questions:
Question 3.
Is this a setup time or hold time timing report?
....................................................................................................
Question 4.
What is the start point? (input port or clk pin of internal
register?)
....................................................................................................
Question 5.
What is the end point?
....................................................................................................
Question 6.
Under what operating conditions was this timing report
generated?
....................................................................................................
Question 7.
Did this timing path meet or violate its constraint?
....................................................................................................
Question 8.
What is the clock period for Clk?
....................................................................................................
Question 9.
What is "input external delay", and where did this number
come from?
....................................................................................................
Question 10.
What can you say about the design’s partitioning?
....................................................................................................
Question 11.
What is the setup time requirement of the capture register?
....................................................................................................
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8-3
Lab 8
Question 12.
What does the clock uncertainty number represent?
....................................................................................................
4.
Open the report file reports/pins_timing.rpt and answer the following
questions.
Question 13.
What is different in this timing report from the default timing
report?
....................................................................................................
5.
Open the report file reports/nets_timing.rpt and answer the following
questions.
Question 14.
What delay is associated with each net and why is the delay
zero?
....................................................................................................
Question 15.
What does the "Fanout" column represent?
....................................................................................................
The incremental timing of the line with the net name is always zero.
6.
Analyze the report file reports/min_timing.rpt, and answer the
following questions.
Question 16.
Is this a setup or hold time report?
....................................................................................................
Question 17.
What is the start point?
....................................................................................................
Question 18.
What is the end point?
....................................................................................................
Question 19.
Did this timing path meet or violate its constraints?
....................................................................................................
Lab 8-4
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8
Question 20.
Under what operating conditions was this report generated?
....................................................................................................
Question 21.
Is this an appropriate operating condition for hold time
calculations?
....................................................................................................
Question 22.
What is the hold time requirement of the end point?
....................................................................................................
Question 23.
What is the delay through the launching register?
....................................................................................................
Question 24.
Is this delay enough to satisfy the hold time requirement?
....................................................................................................
Additional Review Questions
Question 25.
How would you use report_timing to get reports on the 10
worst setup timing paths?
....................................................................................................
Question 26.
How would you get just a summary of every violating timing
path?
....................................................................................................
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8-5
Lab 8
Answers / Solutions
Question 1.
Are there any unconstrained timing paths in
PRGRM_CNT_TOP?
No. check_timing returns no warnings.
Question 2.
How many path groups are in PRGRM_CNT_TOP?
One: my_clk. The entire design is constrained relative to my_clk.
Question 3.
Is this a setup time or hold time timing report?
This is a setup time report. Look at the Path Type at the top of the
report. Max indicates setup, min indicates hold.
Question 4.
What is the start point?
The timing path starts at an input port. This is indicated by the
Startpoint.
Question 5.
What is the end point?
The timing path ends at an internal register. This is indicated by the
Endpoint.
Question 6.
Under what operating conditions was this timing report
generated?
slow_125_1.62.
Question 7.
Did this timing path meet or violate its constraint?
MET. Look at the bottom of the report to see the word MET, and that
the slack is positive.
Question 8.
What is the clock period for Clk?
4 ns. The data is launched by Clk at 0 and captured by Clk at 4.
Question 9.
What is "input external delay", and where did this number
come from?
The input delay is 1 ns, and the input delay was set in
constraints.tcl, by a set_input_delay command. You are
over-constraining, because you assumed that the input data was
coming from a flip-flop, which might have a Clk-to-Q delay of
roughly 0.6ns. If this assumption is false, then after the top-level
design is linked, this timing path may actually violate timing.
Lab 8-6
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8
Question 10.
What can you say about the design’s partitioning?
The partitioning breaks a combinational path (that’s bad!). The path
starts at an input port, traverses through combinational logic in
PRGRM_DECODE, through some combinational logic in PRGRM_CNT
and then ends at a register in PRGRM_CNT. DC was still able to
optimize the path to meet the timing constraints.
Question 11.
What is the setup time requirement of the capture register?
Look at the Library Setup Time in the “Path Information Section” of
the report. The flip-flop’s setup time should be between 0.3-0.6 ns,
depending on the exact flip-flop synthesized.
Question 12.
What does the clock uncertainty number represent?
Skew between the clock branches. This was set by a
set_clock_uncertainty command.
Question 13.
What is different in this timing report from the default
timing report?
This report separates the net and cell delay numbers. The report is
broken down into pin to pin timing arcs.
In the report below, the second line indicates the timing between the
input pin of a XOR gate (pin B), and the output pin of the same XOR
gate (pin Y). It takes the capacitances on the output pin into account.
The third line shows the delay between the output pin of the XOR gate
and the input pin of the next cell (AND). Since the only thing between
the output pin of a cell and the input pin of the next cell is a net, the
third line in the report shows the time-of-flight of the net.
I_PRGRM_DECODE/U330/B (xor2a2)
I_PRGRM_DECODE/U330/Y (xor2a2)
I_PRGRM_DECODE/U336/B (and2b3)
Question 14.
0.000069
0.249299
0.000036
1.244150 f
1.493448 r
1.493484 r
What delay is associated with each net and why is the delay
zero?
The command “report_timing –net” displays the net names only.
That is why the delay number in the column Incr shows always 0ns.
Question 15.
What does the "Fanout" column represent?
The Fanout column indicates fanout number of the net. (Not the
Design Rule fanout load.)
Timing Reports
Synopsys CHIP Synthesis Workshop
Lab 8-7
Lab 8
Question 16.
Is this a setup or hold time report?
Hold time. Look at the Path Type.
Question 17.
What is the start point?
The timing path starts at an internal register.
Question 18.
What is the end point?
The timing path ends at an output port.
Question 19.
Did this timing path meet or violate its constraints?
Violated. Look at the bottom of the report to see the word
VIOLATED, and that the slack is negative.
Question 20.
Under what operating conditions was this report generated?
slow_125_1.62.
Question 21.
Is this an appropriate operating condition for hold time
calculations?
The worst-case operating conditions are appropriate for hold time
reports before layout.
Question 22.
What is the hold time requirement of the end point?
Look at the line "output external delay" in the “required time" section
of the report. 0.30 ns was specified with set_output_delay command
using –min switch.
Question 23.
What is the delay through the launching register?
The delay should be approximately 0.51 ns, depending on the actual
register synthesized.
Question 24.
Is this delay enough to satisfy the hold time requirement?
At least 0.55 ns is required to satisfy the hold time requirement.
Question 25.
How would you use report_timing to get reports on the 10
worst setup timing paths?
report_timing –max_paths 10
Question 26.
How would you get just a summary of every violating
timing path?
report_constraint -all
Lab 8-8
Timing Reports
Synopsys CHIP Synthesis Workshop