MSP430F20xx Device Erratasheet (Rev. L
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Errata SLAZ026L – October 2005 – Revised January 2010 MSP430F20xx Device Erratasheet TA12 TA16 TA22 XOSC5 XOSC8 ü ü ü ü ü ü ü ü D ü ü ü ü ü ü ü ü MSP430F2002 D ü ü ü ü ü ü ü ü ü ü MSP430F2012 D ü ü ü ü ü ü ü ü ü ü MSP430F2003 E ü ü ü ü ü ü ü ü ü ü ü MSP430F2013 E ü ü ü ü ü ü ü ü ü ü ü USI5 FLASH16 D MSP430F2011 USI4 CPU4 MSP430F2001 Devices SDA3 BCL12 Current Version Rev: 1 Note: See Appendix for prior versions ü The checkmark means that the issue is present in that revision. SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated MSP430F20xx Device Erratasheet 1 Package Markings 2 www.ti.com Package Markings N14 PDIP (N), 14 Pin PW14 TSSOP (PW), 14 Pin RSA16 QFN (RSA), 16 Pin 2 MSP430F20xx Device Erratasheet SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Detailed Bug Description www.ti.com 3 Detailed Bug Description BCL12 Basic Clock Module Function Switching RSEL can cause DCO dead time Description After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 μs. In some instances, the DCO may completely stop, requiring a power cycle. Workaround • When switching RSEL from >13 to <12, use an intermediate frequency step. The intermediate RSEL value should be 13. CURRENT RSEL TARGET RSEL 15 14 Switch directly to target RSEL 14 or 15 13 Switch directly to target RSEL 14 or 15 0 to 12 Switch to 13 first, and then to target RSEL (two step sequence) 0 to 13 0 to 12 Switch directly to target RSEL • RECOMMENDED TRANSITION SEQUENCE When switching RSEL from <12 to >13, ensure that the maximum system frequency is not exceeded during the transition. This can be achieved by clearing the DCO bits first (DCOCTL control register, bits 7–5), then increasing the RSEL value, and finally applying the target frequency DCO bit values. For more details, see the examples in the "TLV Structure" chapter in the MSP430F2xx Family User's Guide (SLAU144). CPU4 CPU Module Function PUSH #4, PUSH #8 Description The single operand instruction PUSH cannot use the internal constants (CG) 4 and 8. The other internal constants (0, 1, 2, –1) can be used. The number of clock cycles is different: PUSH #CG uses address mode 00, requiring 3 cycles, 1-word instruction PUSH #4/#8 uses address mode 11, requiring 5 cycles, 2-word instruction Workaround Workaround implemented in assembler. No fix planned. FLASH16 Flash Module Function Modifying INFOA addresses when LOCKA = 1 modifies main flash memory Description When attempting to write to an address location or perform a segment erase of INFOA while the LOCKA bit is set, flash memory beginning at main memory location 0xFC40 and extending for 64 bytes to address 0xFC7F is modified erroneously. These 64 bytes are addressed and modified in place of the INFOA addresses when writes or erases are performed within the INFOA address space and LOCKA = 1. Workaround Prior to modifying (writing or erasing) any address within the INFOA flash memory segment, properly clear the LOCKA control bit as described in the MSP430x2xx Family User's Guide (SLAU144) to unlock the segment. After the modification is complete, setting the LOCKA bit is recommended. SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated MSP430F20xx Device Erratasheet 3 Detailed Bug Description www.ti.com SDA3 SD16_A Module Function The interrupt delay function can result in incorrect conversion data Description The interrupt delay operation can result in incorrect conversion data when SD16INTDLYx = 01, 10, or 11. Workaround Use SD16INTDLYx = 00 setting (interrupt generated after fourth conversion). This applies to the first conversion in Continuous mode and to each conversion in Single mode. TA12 Timer_A Module Function Interrupt is lost (slow ACLK) Description Timer_A counter is running with slow clock (external TACLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_A counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TA16 Timer_A Module Function First increment of TAR erroneous when IDx > 00 Description The first increment of TAR after any timer clear event (POR/TACLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TACLK). This is independent of the clock input divider settings (ID0, ID1). All following TAR increments are performed correctly with the selected IDx settings. Workaround None TA22 Timer_A Module Function Timer_A register modification after watchdog timer PUC Description Unwanted modification of the Timer_A registers TACTL and TAIV can occur when a PUC is generated by the watchdog timer (WDT) in watchdog mode and any Timer_A counter register TACCRx is incremented/decremented (Timer_A does not need to be running). Workaround Initialize TACTL register after the reset occurs using a MOV instruction (BIS/BIC may not fully initialize the register). TAIV is automatically cleared following this initialization. Example Code MOV.W #VAL, &TACTL Where VAL = 0, if Timer is not used in application; otherwise, user defined per desired function. 4 MSP430F20xx Device Erratasheet SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Detailed Bug Description www.ti.com USI4 USI Module Function I2C slave mode can generate a glitch on SCL Description Applies to USI I2C slave operation at slow communication rates (less than 20 kbps). During I2C bus active operation, if USICNT is written while SCL is high, the USI I2C module generates a glitch on SCL that can corrupt the I2C bus sequence. Workaround Verify that SCL is low prior to updating the USICNT register. USI5 USI Module Function SPI master generates one additional clock after module reset Description Initializing the USI in SPI MASTER mode with the USICKPH bit set generates one additional clock pulse than defined by the value in the USICNTx bits on the SCLK pin during the first data transfer after module reset. For example, if the USICNTx bits hold the value eight, nine clock pulses are generated on the SCLK pin for the first transfer only. Workaround Load USICNTx with a count of N – 1 bytes (where N is the required number of bytes) for the first transfer only. XOSC5 LFXT1 Module Function LF crystal failures may not be properly detected by the oscillator fault circuitry Description The oscillator fault error detection of the LFXT1 oscillator in low-frequency mode (XTS = 0) may not work reliably, causing a failing crystal to go undetected by the CPU; that is, OFIFG is not set. Workaround None XOSC8 LFXT1 Module Function ACLK failure when crystal ESR is below 40 kΩ Description When ACLK is sourced by a low-frequency crystal with an ESR below 40 kΩ, the duty cycle of ACLK may fall below the specification; the OFIFG may become set or, in some instances, ACLK may stop completely. Workaround See the application report XOSC8 Guidance (SLAA423) for information regarding working with this erratum. SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated MSP430F20xx Device Erratasheet 5 www.ti.com ü ü ü ü ü ü ü ü ü ü ü ü ü ü D MSP430F2011 C ü ü ü ü ü ü ü ü ü B ü ü ü ü ü ü ü ü ü A ü ü ü ü ü ü ü ü ü ü ü ü D MSP430F2002 ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü A ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü C ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü B ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü A ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü D ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü C ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü B ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü E MSP430F2013 ü B E MSP430F2003 ü ü C D MSP430F2012 ü XOSC8 ü ü ü ü USI5 ü ü ü ü USI4 ü ü ü ü USI3 ü A ü ü USI2 B XOSC5 MSP430F2001 ü USI1 ü TA22 ü TA17 ü TA16 ü TA12 PORT10 ü SDA3 FLASH22 ü ü SDA2 FLASH16 ü D SBW1 CPU4 ü BCL13 BCL11 ü ü BCL12 BCL10 ü C Rev: Devices BCL9 Appendix A Prior Versions D ü ü ü ü ü ü ü ü ü C ü ü ü ü ü ü ü ü ü B ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü The checkmark means that the issue is present in that revision. 6 Prior Versions SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Detailed Bug Description www.ti.com A.1 Detailed Bug Description BCL9 Basic Clock Module Function ACLK divider modifications require delay before entering LPM3 Description After modifying the DIVAx bits, immediately entering LPM3 can cause the modification to be ignored and the divider settings not to take effect. Reading back the DIVAx bits indicates the intended setting even when the divider has not been correctly applied. Workaround When the DIVAx bits are modified, a delay of one complete ACLK (VLO or LFXT1CLK) period must elapse before entering LPM3. The delay is necessary only the first time LPM3 is entered after the DIVAx bits are modified. After the one-period delay, LPM3 may be entered and exited normally without additional delays. BCL10 Basic Clock Module Function MCLK = ACLK and P2SEL control bits Description When using ACLK as the CPU MCLK clock source, the oscillator failsafe feature does not automatically switch MCLK to the DCO if the P2SEL6 or P2SEL7 bit is cleared. This applies when ACLK = LFXT1 (external low-frequency clock source). The CPU halts operation, because no MCLK signal is present. Workaround None BCL11 Basic Clock Module Function Watchdog failsafe when using ACLK Description When using ACLK as the WDT+ clock source, the WDT+ oscillator failsafe feature does not automatically switch to the DCO if the P2SEL6 or P2SEL7 bit is cleared. This applies when ACLK = LFXT1 (external low-frequency clock source). The WDT+ halts operation, because no clock signal is present. Workaround None BCL13 Basic Clock Module Function Exiting reset state with slow VCC rise time Description When subject to very slow VCC rise times, the device may enter a state in which the DCO does not oscillate. No JTAG access or program execution is possible, and the device remains in the reset state until the supply voltage is disconnected. Workaround Apply a VCC power-on ramp ≥10 V/s under all power-on/power-cycle scenarios. SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Prior Versions 7 Detailed Bug Description www.ti.com FLASH22 Flash Module Function Flash controller may prevent correct LPM entry Description When ACLK (or SMCLK) is used as the flash controller clock source and this clock source is deactivated due to a low-power mode entry while a flash erase or write operating is pending, the flash controller keeps ACLK (or SMCLK) active even after the flash operation has been completed. This results in an incorrect LPM entry and increased current consumption. Note that this issue can only occur when the flash operation and the low-power mode entry are initiated from code located in RAM. Workaround Do not enter low-power modes while flash erase or write operations are active. Wait for the operation to complete before entering a low-power mode. PORT10 Digital I/O Module Function Pullup/pulldown resistor selection when module pin function is selected Description When the pullup/pulldown resistor for a certain port pin is enabled (PxREN.y = 1) and the module port pin function is selected (PxSEL.y = 1), the pullup/pulldown resistor configuration of this pin is controlled by the respective module output signal (Module X OUT) instead of the port output register (PxOUT.y). Workaround None. Do not set PxSEL.y and PxREN.y at the same time. SBW1 Spy-Bi-Wire Interface Module Function Increased current consumption Description An error in the Spy-Bi-Wire interface increases the ICC under normal operating conditions. Workaround None SDA2 SD16_A Module Function Internal reference generator performance is beyond the specification limits Description The SD16_A reference generator may not meet the maximum temperature coefficient specification of 50 ppm/°C. Workaround The SD16_A internal reference can be adjusted to operate within the specification by writing 0x61 to memory location 0xBF. This corrects the temperature coefficient of the internal reference and centers the typical voltage to 1.20 V. TA17 Timer_A Module Function Capture input CCI0B missing ACLK connection Description The Timer_A Capture Input CCI0B is not internally connected to the ACLK signal. Workaround The ACLK signal can be output on P1.0 and externally input on a Timer_A capture input pin. 8 Prior Versions SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Detailed Bug Description www.ti.com USI1 USI Module Function USICKCTL register cannot be written Description When the USI is in active operation mode (that is, when USICNTx ≠ 0), the USICKCTL register cannot be written. If written, the USICNTx value is cleared and USIIFG is set. Operation using the USISWCLK software clocking bit is not possible. Workaround None USI2 USI Module Function I2C slave mode erroneously pulls SCL low Description When the USI is configured in I2C slave mode, SCL is incorrectly pulled low when USICNTx is written with a value of 1. Workaround None USI3 USI Module Function I2C slave mode does not hold SCL low Description When the USI is configured in I2C slave mode, the module does not hold SCL low while USISTTIFG = 1 following a start condition. Workaround None SLAZ026L – October 2005 – Revised January 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Prior Versions 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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