Department of Electronic Engineering
City University of Hong Kong
LABORATORY MANUAL
EE2000 Digital Logic Circuit
Semester A 20122012-13
1
PREFACE
This document has been prepared to serve as a laboratory manual for EE2000 Digital Circuit Design
course for electrical engineering students. The manual consists of a set of experiments designed to
allow students to build, and verify digital circuits using Altera Quartus II and DE0 demonstration board.
This set of experiments cover relevant topics prescribed in the syllabus and are designed to reinforce
the theoretical concepts taught in the classroom with practical experience in the lab. By the end of the
course, students are expected to have a good understanding of digital logic design.
Information of the laboratory is available at www.ee.cityu.edu.hk/~ee2000lab.
2
Laboratory Session
Page
LAB 1.
Altera Quartus II Design Tool and DE0 Demonstration Board
6
LAB 2.
Logic Function and Combinational Logic
29
LAB 3.
Decoder and Seven Segment Display
32
LAB 4.
Sequential Logic Circuit – Traffic Light Controller
35
LAB 5.
BCD Counter, Decoder and Seven Segment Display System Integration
40
3
Student Laboratory Responsibilities:
Pre-lab:
It is assumed that you have read the lab experiment assignment carefully before attending the
laboratory. Some portions of the laboratory work must be accomplished before attending the
laboratory session (this part is called the “pre-lab).
It is important to complete the pre-lab assignment before attending the lab session since you will not
have time to perform design tasks AND construct and debug your circuits during the lab session.
The purpose of the lab session is to give you experience in implementing and debugging your designs –
not to perform the design. The pre-lab work is very important and is a significant part of your final
grade in the laboratory. Your pre-lab is due to the lab assistant AT THE BEGINNING OF YOUR LAB
SESSION. The lab assistant will initial the pre-lab.
On-line Video Tutorial:
A video tutorial is available at the laboratory home page for each laboratory experiment to
demonstrate the procedures and result. Review the information before coming to the laboratory
session.
Design Template:
Design templates for each laboratory experiment together with the pin assignment are available at the
laboratory home page.
The Laboratory:
During the lab, students should work independently. It is required to show the setup of the experiment
and demonstrate its functionality. If you have problems in constructing or debugging your experiment,
the demonstrator will be there to help to you. If you have doubts about anything in your experimental
setup, do not plug in the electricity, rather ask the demonstrator for assistance with your circuit. Please
exercise discipline and professional behavior in the laboratory. Excessive chat, and non-lab related talk
is distracting to everyone and should be avoided.
The Lab Report
ALL LAB REPORT SHOULD BE TYPED.
Each student should have his/her own report. The lab reports are intended to serve two equally
important purposes. First, they indicate your technical comprehension of the topics addressed in the
labs, and second, they indicate your ability to present and discuss your results in a clear and concise
manner. You will be graded on both aspects of your report.
4
The suggested format for your lab report is given below.
1. Objectives:
State clearly what you set out to achieve in this lab. If this differs from what you finally achieved,
explain it in the "Conclusions" section. Please do not copy the objectives verbatim from the lab
handout. Think about it, interpret it, and explain it the best you can, in your own words.
2. Design
Describe your design with the circuit diagram in your own words. Please make sure your figures are
consistent, legible and well labeled.
3. Results and Answers to Questions:
Describe what you have observed in the lab. Present your results in a clear and concise manner.
4. Conclusions:
In this section you should attempt to answer the questions: What did you learn from this lab? What
did you do wrong (or what went wrong)? How could you have improved upon your design
procedures? Were your results as expected or did you find something unusual. Try not to include
information that you have included in previous sections. Present the significance of your results
conceptually, if applicable.
5
EE2000 Digital Logic Circuit
Laboratory I
Quartus II Design Tool and DE0 Demonstration Board
Objectives
Become familiar with the Altera Quartus II software package for design entry, and hardware
implementation on DEO demonstration board.
In this laboratory, you will learn how to create a design project, entry a design of logic circuit
represented in textural form, implement the design on a FPGA and demonstrate the functionality of the
design on the DEO demonstration board.
Tool and Resource
• DEO demonstration board
• Altera Quartus II Design Tool
Information of the DEO demonstration board and Altera Quartus II is described in the next session.
Online video tutorials of how to use the DEO demonstration board and Altera Quartus II are available at
the laboratory web site.
6
DEO Demonstration Board
I/O Interface
The DEO demonstration board equips with an Altera Cyclone III EP3C16F484C6 FPGA device. I/O
resources equipped for the laboratory sessions are:
• Slide switches
• Push buttons
• LEDs
• Seven segment displays
• Expansion Headear
7
Using LEDs and Switches
The DEO board provides three pushbutton switches.
The three outputs called BUTTON0, BUTTON1, and
BUTTON2 are connected directly to the Cyclone III
FPGA. Each switch provides a high logic level (3.3 volts)
when it is not pressed, and provides a low logic level
(0 volts) when depressed.
There are also 10 slide switches (sliders) on the
DEO board. These switches are not
debounced, and are intended for use as levelsensitive data inputs to a circuit. Each switch is
connected directly to a pin on the Cyclone III
FPGA. When a switch is in the DOWN position
(closest to the edge of the board) it provides a
low logic level (0 volts) to the FPGA, and when
the switch is in the UP position it provides a high logic level (3.3 volts).
There are 10 user-controllable LEDs on the DEO board. Each
LED is driven directly by a pin on the Cyclone III FPGA; driving
its associated pin to a high logic level turns the LED on, and
driving the pin low turns it off
8
Pin Assignments for LEDs and Switches
Pin assignment for slide switches
Pin assignment for push buttons
Pin assignment for LED
9
Using the Seven Segment Display
The DEO board has four 7-segment displays. These displays are arranged into two pairs and a group
of four, with the intent of displaying numbers of various sizes. The seven segments are connected to
pins on the Cyclone III FPGA. Applying a low logic level to a segment causes it to light up, and
applying a high logic level turns it off.
Each segment in a display is identified by an index from 0 to 6.In addition, the decimal point is
identified as DP.
10
Pin assignment for the seven segment display
Digit 0 and Digit 1
Digital 2 & 3
11
Expansion Header
The expansion header is to provide extension I/O to the demonstration board. The GPIO 1 is used with
the traffic light circuit in laboratory five.
12
Altera Quartus II
The Altera® Quartus® II design software is a multiplatform design environment capable of implement
various type of digital logic system in FPGA. In this laboratory, you will learn how to create a project to
implement a simple logic function starting from project creation, design entry to hardware
implementation on DEO demonstration board.
13
Laboratory
It is to run through the basic steps to create a design in Altera Quartus II and implement a sample
design in DE0 demonstration board:
• Project creation
• Design Entry
• Pin Assignment
• Demonstration Board Programming
Project Creation
Project:
It is the highest level of a logic circuit design to hold all the logic components. To create a project, in
your computer, make a new folder called ee2000lab first; then, follows the procedure step by step.
1. Start up Quartus II
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2. Click on FILE at the top menu, then select NEW PROJECT WIZARD. It has 5 pages for the project entry.
3. Click on NEXT of the popup menu. A project information menu will be popped up. It is the first
page of the project entry sequence.
15
4. Enter the project information in the popup menu.
•
Enter the project location in the first field. Select the newly created folder ee2000lab with
the mouse clicked on the selection box.
•
•
Enter the name of the project in the second field as lab1.
Enter the top level design entity of the project as lab1. Usually the name of the project
and the top level design entity should be the same.
•
After entered information in all three field, CLICK on NEXT.
16
5. Click on NEXT on page 2 .
6. Select Cyclone III on the FAMILY field and EP3C16F484C6 on the AVAILABLE DEVICE field.
17
7. Click on NEXT of the popup page 4 and FINISH on the popup page 5. The design project is
created and according information will be shown in the main menu. Select FILE on the menu
bar and SAVE the project. The according file will appear the project folder ee2000lab.
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Design Entry
It is to create the circuit under investigation. It consists of:
• Create the design file for the circuit
• Add the design file into project
• Compile the circuit into application executable format
In this laboratory, a simple logic circuit as shown below is used as the demonstration.
1. Create the design file for the circuit
Use any text editor to create the design file for the above circuit. In this laboratory, a text editor called
notepad++ is introduced. Start the program notepad++, set the language to Verilog by selecting
LANGUAGE on the top menu bar, then move to V, and select VERILOG. The blue color texts are
reserved words, and black color texts are user defined code. Once VERILOG is selected, the edited file
will be saved with .v extension. There two ways to model the above sample circuit, the dataflow and the
structural modeling. You may use either of one. More detail information with video tutorials
concerning model is available at the laboratory web site.
Dataflow Modeling
It uses ASSIGN statement to define
the logic function of the circuit
being modeled, in this case,
1
2.
12
Detail information of the code
should refer to the laboratory
web site for explanation. Use
notpad++, entering the above code,
and save it in a file called lab1 in the
directory ee2000lab.
19
Structural Modeling
It is similar to dataflow modeling but defining the logic function in terms of logic components and their
connectivity. Detail information of the code should refer to the laboratory web site for explanation. .
2. Add the design file into project
After creating the design file lab1..v
lab1..v , it has to be added into design project.
• Select FILE on the top menu
• Select OPEN
• Select lab1.v, Click OPEN
20
The design file lab.v will be displayed in a sub-window after lab1 is selected at the Progect
Navigator window.
•
Select PROJECT on the top menu, then Select ADD CURRENT FILE TO PROJECT
21
3. Compile the circuit into application executable format
• Select PROCESSING on the top menu
• Select START COMPILATION
• Upon finish, a Full Compilation message will be shown. Ignore all the warning.
22
Pin Assignment
It is to assign the according I/O pin to link the FPGA with the I/O interface of the demonstration board.
For the sample circuit, two slide switches, SW0 and SW1,
SW1 are used as the external inputs for x1 and x2
to the example circuit. When a switch is in the DOWN position; that is, closer to the edge of the board,
the signal will be in logic '0'. Zero volts will be supplied to the assigned pin. On the other hand, when the
switch is in the UP position, it will provide a 3.3 volts, a logic '1', to the assigned pin. The LEDG[0] is used
to indicate the logic value of the output signal f.
Signal
x1
x2
f
I/O
input
input
output
Signal Name
SW[0]
SW[1]
LEDG[0]
Pin No.
PIN_J6
PIN_H5
PIN_J1
Description
Slide Switch [0]
Slide Switch [1]
LED Green [0]
1. Select ASSIGNMENT on the top menu and Select PINS
• Pin Planner window will popup
23
2. Click on LOCATION menu
3. Double CLICK on the LOCATION field for particular I/O, for example, f.
4. Type in J1 at the EMPLTY FIELD then Select PIN_J1
5. REPEAT the same steps for the I/O pin assignment of other signals
24
6. Export the pin assignment to external file through:
• Select FILE and EXPORT at the Pin Planner Windows
7. Complete the Pin Assignment Process by SAVE PROJECT at the Project Navigator Window.
8. Recompile the design through selecting PROCESSING, then START COMPILATION at the top menu
25
Demonstration Board Programming
It is to implement the design on the DE0 demonstration board.
1. Connect the USB cable to the DE0
demonstration board and the host computer.
2. Switch the toggle switch to RUN position at the programming mode control of the DE0
demonstration board and turn on POWER by pressing the RED ON/OFF Button
3. Select TOOL and PROGRAMMER at the top menu.
26
4. Set up the Hardware
• Select JTAG at the Mode field
• The default hardware should be USB Blaster. If it is NOT, as shown in the figure.
• Click on HARDWARE SETUP button
•
•
Select USB-BLASTER at the Hardware Setting menu.
Select design netlist file lab1.sof at the programmer popup windows, the click START
5. The DE0 demonstration board is ready for use with the sample circuit on board.
27
28
EE2000 Digital Logic Circuit
Laboratory II
Logic Function and Combinational Logic
Objective
It is to enforce the student’s understanding on the standard representation of a logic function and its
hardware realization in logic gates.
Canonical and Standard Form Recall
• A Boolean logic function can be expressed in a variety of algebraic forms such as
Y = ca’+cb = c (a’ + b) = c (c’ + b + a’)
• Each algebraic form entails specific gate implementation.
• A Boolean function can be uniquely described by its truth table, or in one of the canonical forms.
• Two dual canonical forms of a Boolean function are
The sum of minterms form (SOM)
The product of maxterms form (POM)
• A minterm is a product of all variables taken either in their direct or complemented form
• A maxterm is a sum of all variables taken either in their direct or complemented form
• Any logic function expressed in canonical form can be implemented in two levels of logics.
Pre-lab
1. Express the logic equation for the logic function F (A, B, C) specified in the truth table shown below
in its two canonical forms respective.
2. Using NOR gate and INVERTER, implement the logic function expressed in the canonical logic
equations from 1 respectively.
3. Using NAND gate and INVERTER, implement the logic function expressed in the canonical logic
equations from 1 respectively.
Entry A
0
0
1
0
2
0
3
0
4
1
5
1
6
1
7
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
0
1
0
1
1
0
1
29
Laboratory
It is to verify the equality of a logic function and its canonical forms and strengthen students’
understanding on logic gate realization of its canonical form, and demonstrate the hardware
implementation on DE0.
A logic function F ( x, y, z ) is given as F = x’y + z.
1. Implement the logic function in its original form and verify against its two canonical forms in
dataflow model. With SW0, SW1, and SW2 as inputs for the variables x, y, z, and LEDG0, LEDG1,
LEDG2 as the output of the logic function in its original form, the SOM and POM forms respectively,
demonstrate that they are logical equivalent.
The design template:
module lab2 (x, y, z, f, som, pom);
input x, y, z;
output f, som, pom;
assign f
assign som
assign pom
= (~x & y) | z
= ……. ;
= ……. ;
;
endmodule
2. Implement the logic function in its original form using NOR gate and INVERTER in structural model,
and verify against the implementation with NAND gates and INVERTER. With SW0, SW1, and SW2
as inputs for the variables x, y, z, and LEDG0, LEDG1 as the output of the logic function in NAND and
NOR implementations respectively.
The design template:
module lab2 (x, y, z, f_nor, f_nand);
input
x, y, z;
output f_nor, f_nand;
wire
x_bar, y_bar, z_bar, …… ;
not
not
not
q1 (x_bar, x);
q2 (y_bar, y);
q3 (z_bar, z);
nand q4 (f_nand …
nand q5 (…
);
…….
nor qx (f_nor …
nor qy (….
);
…….
);
);
endmodule
30
Post Lab Questions
• How many rows would a truth table require for an n-input logic circuit?
• What do the True and False Boolean constants represent in reality?
• What are your favorite part of this lab, and least favorite part? Why?
Lab Report
Submit an individual lab report at the beginning of the next lab session with the following
sections and requirements:
1. Cover Sheet
Include title, name, class, section, date due, date submitted, and lab supervisor‘s name.
2. Objective
Briefly describe the objective of the experiment,
3. Design
Explain your design and its purpose, testing results, obstacles encountered and how you resolve
them. Give the logic expression of your design and the corresponding logic diagram.
4. Result and Conclusion
Briefly discuss what you have observed and learned from the experiment, and how it relates to
digital logic circuit.
5. Post Lab Questions
Answer all questions completely
The lab report should be single spaced, typed, and a minimum of 1½ pages (excluding images).
Neatness and clarity are essential.
31
EE2000 Digital Logic Circuit
Laboratory III
Decoder and Seven Segment Display
Objectives:
1. To implement a decoder for seven segment display
2. Application of logic minimization with K-map for a practical digital logic device implementation.
The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive 7segment display devices to produce a decimal readout. Four input pins, marked A, B, C, and D accept
the BCD signal (A is the LSB). Eight pins - marked 0, 1, 2, 3, 4, 5, 6, and dp as output the signals to turn
ON or OFF the appropriate segments to display a decimal number on the 7-segment display device.
The decoder should have an active low output as the segment of a 7-segment display device will be
turned on by a logic ` low ’.
Pre-Lab
Complete the truth table shown in Table 1 for the 7-segment display decoder and deduce the
minimized logic expression for each of the segments including dp for the inputs A, B, C, and D using Kmap. For the input BCD code is out of range from 0 to 9, turn on the segment dp.
32
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
s0 s1 s2 s3 s4 s5 s6 dp
0 0 0 0 0 0 1 1
1 0 0 1 1 1 1
1
1
1
1
1
1
1
1
1
1 1 1
0
1 1 1
0
1 1 1
0
1 1 1
0
1 1 1
0
1 1 1
0
Table 1. Truth table for the 7-segment display decoder
Deduce the logic equations for the display segments in either the form of POS or SOP.
Laboratory
It is to implement the results from the pre-lab on the DE0 demonstration board. With your decoder, use
toggle switches, SW3, Sw2, Sw1 and SW0, as the inputs, D, C, B, and A, to turn on the HEX0 7-segment
display of the DE0.
The design template:
module ssd (s0, s1, s2, s3, s4, s5, s6, sdp, a, b, c, d);
input a, b, c, d;
output s0, s1, s2, s3, s4, s5, s6, sdp;
assign s0 = ……. . ;
assign s1 = ……. . ;
.
.
.
assign sdp = ……. . ;
endmodule
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Post Lab Questions
• When would it be best to use the POS form of an output to derive a logic circuit?
• Do SOP or POS expression forms represent an output function as minimal as possible or can
they be reduced further? Justify your reasoning.
• What are your favorite part of this lab, and least favorite part? Why?
Lab Report
Submit an individual lab report at the beginning of the ne xt lab session with the following
sections and requirements:
1. Cover Sheet
Include title, name, class, section, date due, date submitted, and lab supervisor ‘s name.
2. Objective
Briefly describe the objective of the experiment,
3. Design
Explain your design and its purpose, testing results, obstacles encountered and how you resolve
them. Give the logic expression of your design and the corresponding logic diagram.
4. Result and Conclusion
Briefly discuss what you have observed and learned from the experiment, and how it relates to
digital logic circuit.
5. Post Lab Questions
Answer all questions completely
The lab report should be single spaced, typed, and a minimum of 1½ pages (excluding images).
Neatness and clarity are essential.
34
EE2000 Digital Logic Circuit
Laboratory IV
Traffic Light Controller
Objective
To practice the design technique for sequential logic circuit and demonstrate in a practical real life
application.
A typical traffic light for intersection traffic has 3 lights: red, yellow and green. The lab experiment is to
design a traffic light controller to control the lighting sequence of two sets of traffic lights at a road
junction as shown in the following figure.
The lighting sequence is as follow: GREEN,
YELLOW, RED, RED-YELLOW, and repeat the
sequence again. Each lighting period lasts for
1 cycle. The corresponding light sequence at
the intersection is as follows:
Road 1
Road 2
GREEN
RED
YELLOW
RED-YELLOW
RED
GREEN
RED-YELLOW YELLOW
The system architecture of the traffic light controller is depicted in the figure shown below. Since there
are four states totally, it requires two registers for the state representation. The combinational circuit
consists of logic for the next state decoder and output decoder. The D register used is active low reset.
The default power reset state is GREEN at road1.
35
Pre_Lab Question
Design the traffic light sequencer using a Moore machine. Complete the following state table and draw
the state diagram for truth table. Q1Q0 represent the value of the present state, D1 and D0 are the next
state values fed back to the inputs of the D-FFs. There are two sets of output signals to control the
on/off of the two sets of traffic lights. The letters G, Y, and R are used to denote the control signals for
the green, yellow and red LEDs, respectively. The startup state is G1 on and R2 on with Q1Q0 being as
‘00’.
Derive the Boolean equations in SOP form for the signals D1, D0, G1, Y1, R1, G2, Y2, and R2 in terms of
Q1, and Q0.
Laboratory
Implement the traffic light controller as designed in the pre-lab exercise and demonstrate in DE0
demonstration board
1. Connect the traffic light circuit to the expansion header GPIO1 of DE0 demonstration board.
2. Create a project, tlc, in your working directory. With the design template, complete the design. Use
the D register with reset for your work. The design file of the D register is d_ff.v. Add the design file
into the project together with your design file.
3. Program the I/O pin as follows:
Road 1
R1
Pins
Road2
R2
Y1
Y2
G1
G2
4. Use PUSH BUTTON0 as the system clock. Whenever the button is pushed, the traffic light should be
changed accordingly.
5. Use PUSH BUTTON1 as the reset for the power up reset. Whenever the button is pushed, the traffic
light will go back to the startup state.
6. Compile your design and program the DE0 demonstration board to demonstrate your work.
36
Design Template:
module tlc(r1, y1, g1, r2, y2, g2, pb_reset, pb_clk);
input pb_reset, pb_clk;
output r1, y1, g1, r2, y2, g2 ;
wire d1, d0, q1, q0;
assign r1 = your code here ;
assign y1 = your code here ;
assign g1 = your code here ;
assign r2 = your code here ;
assign y2 = your code here ;
assign g2 = your code here ;
assign d1 = your code here ;
assign d0 = your code here ;
d_ff ff1(q1, d1, pb_reset, pb_clk);
d_ff ff2(q0, d0, pb_reset, pb_clk);
endmodule
module d_ff (Q, D, RESET, CLK);
input D, RESET, CLK;
output reg Q;
always @(negedge RESET or posedge CLK)
begin
if (~RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule
37
Post Lab Question
1. What is the major difference between a D-FF and a D-latch?
2. If the D-FFs in your circuit are replaced by D-latches, what will happen? Explain.
3. Can the traffic light sequencer be implemented using other types of flip-flops, e.g. J-K
flip-flops? Explain.
4. What are your favorite part of this lab, and least favorite part? Why?
38
Lab Report
Submit an individual lab report at the beginning of the next lab session with the following
sections and requirements:
1. Cover Sheet
Include title, name, class, section, date due, date submitted, and lab supervisor ‘s name.
2. Objective
Briefly describe the objective of the experiment,
3. Design
Explain your design and its purpose, testing results, obstacles encountered and how you resolve
them. Give the logic expression of your design and the corresponding logic diagram.
4. Result and Conclusion
Briefly discuss what you have observed and learned from the experiment, and how it relates to
digital logic circuit.
5. Post Lab Questions
Answer all questions completely
The lab report should be single spaced, typed, and a minimum of 1½ pages (excluding images).
Neatness and clarity are essential.
39
EE2000 Digital Logic Circuit
Laboratory V
BCD Counter, Decoder and Seven Segment Display System Integration
Objective
In this lab, it is to implement a BCD counter and display the counted result on a seven segment display.
1. Learning system integration with different digital circuit components demonstrated in a simple
digital logic system.
2. Application of binary code decoder
3. How to use asynchronous reset for system re-initialization
Pre-Lab
BCD stands for Binary Coded Decimal. A BCD counter has four outputs usually labeled A, B, C, D. By
convention A is the least significant bit, or LSB. The easiest way to understand what a BCD counter
does is to follow the counting sequence in truth table form:
In other words, the counter
outputs follow a binary sequence
representing
the
decimal
numbers 0-9....
The corresponding state diagram of a BCD counter is as follows:
40
Pre-Lab Question
Design the BCD counter using D-flip flop. Give the logic equation for the QD, QC, QB and QA accordingly.
Draw the logic circuit diagram of your design.
Laboratory
Design a simple digital logic system shown below consists of a BCD counter counting a single decimal
number from 0 to 9 and back to 0 with a single push button as clocking input. The counting output is
decoded by a seven segment decoder to drive a seven segment display. The simple BCD counting
circuit is resettable upon pressing a reset push button. The counter will be reset to zero upon the reset
push button is pressed.
[ bcd 3 - 0 ]
Binary
Counter
4 bits
pb_clk
Seven
Segment
Decoder
[ sg6 - 0 , sdp ]
8 bits
reset
pb_reset
reset
reset logic
BCD Counter
The simple counting circuit as shown in the figure consists of four basic components: a binary counter, a
reset logic, seven segment display decoder, and seven segment display.
Binary Counter:
A 4-bit binary ripple counter counts for the single decimal digital from 0000 to 1111 back to 0000. It can
be implemented using T flip flops with reset.
41
Reset Logic:
The reset logic detects the binary value 1010 that is 10 in decimal from the output of binary counter.
Whenever the value 10 is reached, it will reset the counter back to 0000. The desirable reset signal is
active low for the binary ripple counter. Upon the counter output reaches 1010, the reset logic will issue
a logic low signal to reset the counter back to 0000; also, upon the pressing of the reset push button.
The block diagram of the reset logic is shown in the following figure.
Seven Segment Display Decoder & Seven Segment Display
It is the logic circuit from the last laboratory experiment. It accepts a BCD code from the binary counter,
decodes the value, and sends out appropriate driving signals to light up the seven segment display.
Implement the above logic circuit in DE0 demonstration board with PUSH BUTTON [0] for the clocking
signal, PUSH BUTTON [1] as the reset push button, the seven segment display, HEX0, for displaying the
decimal number.
42
Design Template:
module bcd(s0, s1, s2, s3, s4, s5, s6, sdp, pb_clk, pb_reset);
input pb_clk, pb_reset;
output s0, s1, s2, s3, s4, s5, s6, sdp;
wire bcd0, bcd1, bcd2, bcd3; /*bcd3 MSB, bcd0 LSB*/
bin_ctr
q1(bcd0, bcd1, bcd2, bcd3, pb_clk, reset);
reset_lg q2(reset, bcd0, bcd1, bcd2, bcd3, pb_reset);
ssd
q3(s0, s1, s2, s3, s4, s5, s6, sdp, bcd0, bcd1, bcd2, bcd3);
endmodule
module bin_ctr(bcd0, bcd1, bcd2, bcd3, pb_clk, reset);
input pb_clk, reset;
output bcd0, bcd1, bcd2, bcd3;
t_ff
t_ff
t_ff
t_ff
q0(bcd0,
q1(bcd1,
q2(bcd2,
q3(bcd3,
1'b1,
1'b1,
1'b1,
1'b1,
reset,
reset,
reset,
reset,
pb_clk);
bcd0);
bcd1);
bcd2);
endmodule
module t_ff (Q, T, RESET, CLK);
input T, RESET, CLK;
output reg Q;
always @(negedge RESET or negedge CLK)
begin
if (~RESET)
Q <= 1'b0;
else
if (T)
Q <= ~Q;
else
Q <= Q;
end
endmodule
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module reset_lg (reset, bcd0, bcd1, bcd2, bcd3, pb_reset);
input bcd0, bcd1, bcd2, bcd3, pb_reset;
output reset;
wire
eq_ten, eq_ten_bar;
assign eq_ten_bar
assign reset
= ~eq_ten;
= pb_reset & eq_ten_bar;
assign eq_ten
= your code here;
endmodule
module ssd (s0, s1, s2, s3, s4, s5, s6, sdp, bcd0, bcd1, bcd2, bcd3);
input bcd0, bcd1, bcd2, bcd3;
output s0, s1, s2, s3, s4, s5, s6, sdp;
YOUR CODE HERE FROM LAST LAB.
endmodule
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Post Lab Questions
• Is there any advantage of the BCD counter implemented with a binary ripple counter and reset
decoder as given in this lab over the BCD counter asked in the Pre-Lab question implemented
as a single finite state machine?
• Is it possible to make use of the BCD counter given in this lab for counting decimal number
more than a single digital? If so, with the given BCD counter, design a logic circuit counting for
two decimal digits. Draw the logic circuit diagram of your design. If not, suggest an alternative
design to do so.
• What are your favorite part of this lab, and least favorite part? Why?
Lab Report
Submit an individual lab report at due date to be announced by the lab supervisor with the following
sections and requirements:
1. Cover Sheet
Include title, name, class, section, date due, date submitted, and lab supervisor‘s name.
2. Objective
Briefly describe the objective of the experiment,
3. Design
Explain your design and its purpose, testing results, obstacles encountered and how you resolve
them. Give the logic expression of your design and the corresponding logic diagram.
4. Result and Conclusion
Briefly discuss what you have observed and learned from the experiment, and how it relates to
digital logic circuit.
5. Post Lab Questions
Answer all questions completely
The lab report should be single spaced, typed, and a minimum of 1½ pages (excluding images).
Neatness and clarity are essential.
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