How to Start and Run Cadence
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Go to the work_cad directory by typing cd work_cad.
Get into C-shell mode by typing csh
Source the cadence variables file by typing source cadence.cshrc.
Type icfb & to start Cadence.
Creating a New Library and Getting
Started
1. When you start ICFB, Library Manager opens along with the icfb log window. You can access
the Library Manager by going to Tools -> Library Manager on the main icfb log window.
2. The organization is as follows: All your schematics, layouts, etc. are organized inside a foldertype entity which is termed as “Library” in Cadence.
3. In order to get started, go to File -> New -> Library. Enter the name of the Library that you
want to create and click OK. You will be asked next whether it is a technology library or
whether you need to attach a tech library. Choose the option of attaching a technology
library and choose umc13mmrf from the drop-down list. You are now ready with your new
library.
4. Now you can create your schematic by selecting the library of your choice and going to File > New -> Cell View. Provide a name of your choice and select Composer-Schematic as the
tool, in order open and edit a new schematic.
Creating a Schematic
1. Press i to open the “instances browser”. This is the browser using which you can add various
elements into your design. You can also access this by clicking on the Instance button on the
left hand pane.
2. All the transistors used for designing our ICs are available inside the umc13mmrf library. You
can pick the transistor of your choice.
3. The organization in Cadence is as follows: There are Libraries which contain multiple
elements. These elements can be of different types, like schematic, symbol, layout, calibre
netlist, assura netlist, vhdl, Verilog, etc. You can also create your own view type for your
organizational convenience. These elements can also be organized as categories for
convenience.
Note: To give an example, in the umc13mmrf library, you will find different categories like
MOS, Capacitors, inductors etc. (If you cannot see the categories, pls check the Show
Categories option on the top.) Under each category, you will find different devices which can
be used for your design. Each device will have multiple views listed in the adjacent column
when you click on any one of them. Be sure to select the symbol view when you are trying to
use any element in your design. This applies for all elements which you may try to use in
cadence schematic.
4. For basic simulations, the following table will help you find the right elements in the right
libraries.
Ideal R, L, C, Voltage, current sources, ports
etc., ground, all ideal electronic components
Transistors, real L, C (which will be used in
your tapeout), diodes etc.
RF specific components and blocks
Ideal functional blocks in
vhdl/Verilog/veriloga
Ideal mathematical models of functional
blocks
Examples of RF Subsystems
analogLib
umc13mmrf
rfLib
ahdlLib
Functional
rfExamples
5. Some commonly used shortcuts while creating schematics:
Drawing a wire
Adding and element (aka instance)
Labelling a wire (aka net)
Copying
Moving
Adding a Pin
Check and Save
w
i
l
c
m
m
x
6. Once the schematic is created, click on the Check and Save button on the left pane (It’s the
first button on the left pane). If there are any errors, they will be displayed. Warnings will be
also be notified. You may ignore the warnings sometimes, but you have to fix your errors.
7. Click on Tools -> Analog Environment to start your simulation setup. This is the interface
which will help you set up and run your simulations.
8. First you need to set up the type of simulation which you want to run.
To look at time-domain waveforms or
Transient
process time-domain waveforms.
DC operating point, bias voltages, currents,
DC analysis
analog device parameters etc.
Frequency-domain response, and analysis
AC analysis
S-parameters, and other classical
SP
RF/Microwave analysis
Periodic Steady State analysis for advanced
PSS
RF measurements
Please refer the Spectre Tutorial and SpectreRF Tutorial to get to know the other different
analyses available, and how each of these work.
9. For each analysis there are parameters which need to be set according to your specific
needs. For example in transient analysis, you need to specify the amount of time the
simulation needs to run and the tolerance level (10 cycles of lowest frequency in the design).
For ac/sp analyses, you need to specify the frequency range.
10. Once that is done, click on Setup -> Model Libraries to add the model files. Click on Browse
and go to the place where your PDK is located and select the model file you need. (In B09
most of the files are added by default.) Also, you can change the process corner for each of
the device models, in the space provided at the bottom when you select any of the model
libraries. The corners are tt, ff, ss, snfp, fnsp. For passives (inductors and capacitors), typ,
max and min are the corners provided.
11. Click on Outputs -> To be plotted to select the nets and nodes which you want view after
the simulation. Net voltages and node currents will be plotted. By default all voltages are
saved during simulation and only those nodes which are selected to be saved will be saved.
You can change this by going to Outputs -> Setup and changing the preferences to save only
selected nets. You may have to do this while running huge simulations, especially with PEX
extracted netlists.
12. Instead of specifying the parameters exactly, you can also use variables. For example you
can set the dc voltage source voltage to a variable name like “dc_voltage”. When such
variables are used, they must be copied to the Analog Environment window. To do it, select
Variables -> Copy from Cellview. All the variables used in the schematic will be listed in the
left bottom pane. In order to run your simulation, you need to assign values for the variables
or use them in a parametric sweep.
13. Now click on Netlist and Run button or go to Simulation -> Netlist and Run. The simulation
will start. If you haven’t Checked and saved your netlist, or if your model libraries are not
added properly, you will end up with errors. So ensure that you have done both.
14. Once the simulation is over, if you have assigned some nets/nodes to be plotted it will be
automatically displayed.
15. If you want to look at other nets, you can select Results -> Transient Signal and select the
nets you want to observe on the schematic and press escape. You can also plot Transient
Sum, Transient Difference.
16. If you are running ac analysis you can plot the appropriate parameters. You can also go to
Results -> Main Form and select what you want to plot. This option should be used when
running advanced simulations like sp, pss etc.
17. Please note that you can run more than one simulation/analysis at a time and the Main
Form will have the appropriate measurements in each tab.
Creating a Symbol for your Schematic
1. Once the design is finalized, you can make a sub-circuit out of your schematic and assign a
symbol to it. To do it, label all the input and output points, including your supply rails. You
can do this by pressing ‘l’ or selecting the ‘label’ option from the sidebar. Enter the net name
that you wish to give and place it on the appropriate wire.
2. Once all the wires that serve as inputs or outputs are labelled, you can place input/output
pins. Press ‘p’ or select the ‘Add Pins’ option from the sidebar. Enter the same net names
that you have provided in the previous step and select whether it is an input/output pin.
3. After placing all the pins, check and save your schematic. Go to Design -> Create Cellview ->
From Cellview. Click OK in the dialog box that opens. Place the pins in the order you want, in
whichever side you want and click OK.
4. You will be shown the symbol you have created. You can move the pins around and modify if
you want. You can also create your own symbol here or import existing symbols. Save it and
close it.
Creating Layout from Schematic
1. Now that you have successfully tested your schematic satisfactorily, you can do the layout
by selecting Tools -> Design Synthesis -> Layout XL. This opens the layout editor Virtuoso.
2. In order to place the elements as per your schematic, select Design -> Gen from Source.
Select the metal layer you choose to put your pins on and click OK. This will place all the
elements in layout according to the schematic.
3. You will find a LSW window also opened along with your layout. You can use this to view
selected layers etc.
4. Some commonly used short-cuts are given below
Drawing a polygon
Drawing a path
Drawing a rectangle
Stretching
Copying
Moving
Flipping, rotating etc.
Labelling
Adding a Pin
Properties
5.
p
P (mind the caps!)
r
s
c
s
m and then F3
l
Ctrl+p
q
With the layout completed, you need to check if you are violating any of the design rules. So run a
DRC (Design Rules Check). Go to Calibre -> Run DRC. The first time you use it, you need to specify the
design rule files. There are two types of design rule checks. Both need to be done. They are called
BEOL and FEOL.
a. Select File -> New Runset. On the ‘Rules’ tab on the sidebar, click on the browse button for
the rules file. Point to the location of FEOL files for 1-poly, 8-metal, 20K process. It is usually
located in the following location:
/srv/install/PDK/UM130FDKMFC_B09_PB/RuleDecks/Calibre/DRC/G-DFMIXEDMODE_RFCMOS13-1P8M2T-MMC-L130E_Calibre-drc-2.5-P1.
b. For DRC Run Directory location, go to your work_cad folder and create and separate folder
for DRC and point to it. Save this runset as a runset file for FEOL.
c. Repeat the above procedure for BEOL files. The file to be used for BEOL is
/srv/install/PDK/UM130FDKMFC_B09_PB/RuleDecks/Calibre/DRC/G-DF-GENERATION13BEOL-1P8M2T-Calibre-drc-2.5-P3_20KA
6.
7.
8.
With the initial setup done, you can choose the each of the FEOL and BEOL runset files separately and
run DRC. Correct the errors. (Density errors, Corner angle errors can be ignored.)
Now, your layout is DRC-Clean. This has to be compared to your schematic to verify if all the
connections are correctly done. To do this, go to Calibre -> Run LVS. Point to this file for LVS:
/srv/install/PDK/UM130FDKMFC_B09_PB/RuleDecks/Calibre/LVS/G-DF-MIXED_MODE_RFCMOS131P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P8.txt. Create a new folder for LVS results inside your
work_cad and point to it. Run LVS. Save the settings as a runset file.
As a last step, we need to extract the parasitic Rs and Cs in the layout. This is done by selecting Calibre
-> Run PEX. For the first time you run, you need to specify the rules file and save it as a runset file.
Point to this file to run PEX: /srv/install/PDK/UM130FDKMFC_B09_PB/RuleDecks/Calibre/LPE/G-DFMIXED_MODE_RFCMOS13-1P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P8.txt.
Using Extracted Netlists in Simulations
Once parasitic extraction is done, the original simulations can be redone with the extracted
netlist to capture the effects of the parasitic elements. This can be done selecting Setup ->
Environment in the Analog Design Environment window. Add calibre to the Switch View List in the
dialog box and click OK. Now the simulation will use the extracted to netlist.
Additional Resources
Layout
http://cutler.eecs.berkeley.edu/classes/icdesign/EE141_f03/CadenceLabs/Lab2/VirtuosoTut
orial.htm
Cadence
http://www.ee.virginia.edu/~mrs8n/cadence/Cadencetutorials.html
http://www.engr.siu.edu/~magic/tutorial/cadence_tut1.pdf
http://www.columbia.edu/~bv2152/e6312_hw/tutorial.pdf
http://www.cours.polymtl.ca/gbm8320/CADENCE_Manual.pdf