Weiss Engineering Ltd. OP1-BP
General Description
Noise
√
1 nV/ Hz voltage noise density at 1 kHz
30 nVPP voltage noise 0.1–10 Hz
√
0.7 pA/ Hz current noise density at 1 kHz
80 pAPP current noise 0.1–10 Hz
The OP1-BP is a discrete operational amplifier particularly optimised for audio applications. Its wide
output swing and superior load driving capability
(27 VPP into 200 Ω), very low distortion (−152 dB)
√
and very low noise (1 nV/ Hz) leads to signal paths
with exceptionally wide dynamic range. The excellent
AC characteristics (50 V/µs slew-rate and 95 MHz
gain bandwidth) ensures exemplary performance at
ultrasound frequencies. This is combined with low input offset voltage (±10 µV), low input bias and input
offset current (±60 nA and ±10 nA), good CMRR
and PSRR (130 dB) and wide power supply range
(±5 V to ±18 V) to form a true high performance
general purpose amplifier.
Besides high-end audio the OP1-BP is useful for
any critical application which requires very wide dynamic range and low distortion analogue signal processing; typical examples include spectrum analyzers,
infrared detectors and low distortion oscillators.
ar
y
Features
im
in
THD+N
−152 dB (+20 dBu, 1 kHz, 22 kHz BW, 600 Ω load)
−148 dB (+20 dBu, 10 kHz, 80 kHz BW, 600 Ω load)
AC characteristics
50 V/µs slew-rate, highly symmetrical
95 MHz gain bandwidth (G = 80 dB)
700 kHz full power bandwidth (20 VPP into 600 Ω)
300 kHz full power bandwidth (20 VPP into 200 Ω)
DC characteristics
±10 µV input offset voltage
±60 nA input bias current
±2 nA input offset current
Pr
el
Load driving capability
27 VPP (+21.8 dBu) into 200 Ω (±15 V supply)
20 VPP (+19.2 dBu) into 100 Ω (±15 V supply)
10 VPP (+13.2 dBu) into 50 Ω (±15 V supply)
adjustable class A output current
Applications
• high performance audio
• low noise, low distortion preamplifiers
• high resolution ADC drivers
• high resolution DAC IV converters
• headphone amplifiers and high-power line driver
• low distortion active filters
• high resolution instrumentation
1
ar
y
Contents
1 Revision History
3
2 Specifications
4
im
in
3 Absolute Maximum Ratings
5
4 Typical Performance Characteristics
6
5 Theory Of Operation
15
5.1 Discrete vs. IC Operational Amplifiers . . . . . . . . . . . . . . . 15
5.2 Amplifier Architecture and Implementation . . . . . . . . . . . . 16
5.3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . 18
Pr
el
6 Applications Information
6.1 Noise and Source Impedance Considerations . . . . .
6.2 Low Distortion Implementation . . . . . . . . . . . .
6.3 Class A Output Current Adjustment . . . . . . . . .
6.4 DC Precision . . . . . . . . . . . . . . . . . . . . . .
6.5 Ground Pin Connection . . . . . . . . . . . . . . . .
6.6 Feedback Capacitor Selection . . . . . . . . . . . . .
6.7 Power Supply Bypassing and Layout Considerations
6.8 Driving Capacitive Loads . . . . . . . . . . . . . . .
6.9 Sockets and Handling . . . . . . . . . . . . . . . . .
7 Outline Dimensions and Pinout
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
19
19
21
21
22
23
23
24
25
25
27
Revision History
ar
y
Chapter 1
im
in
2011-10-27, Revision 2: Revision history section added; typical performance
characteristics section extended; outline dimenstions section extended.
Pr
el
2011-01-21, Revision 1: Initial revision, preliminary.
3
ar
y
Chapter 2
Specifications
im
in
The following specifications apply for TA = +25◦ C, VS = ±15 V and amplifier
fully warmed up unless otherwise noted.
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Open Loop Gain
el
Gain Bandwidth Product
Unity Gain Frequency
Slew Rate
Power Supply Rejection
Input Voltage Noise Density
Pr
Input Voltage Noise
Input Voltage Noise Density 1/f Corner
Input Current Noise Density
Input Current Noise
Input Current Noise Density 1/f Corner
Output Voltage Swing
Factory Preset Class A Output Current
Recommended Power Supply Voltage
Quiescent Current
Ground Pin Current
Condition
Min
RL = 600 Ω
RL = 200 Ω
G = 80 dB
RL = 600 Ω
f = 10 Hz
f = 1 kHz
f = 10 Hz
0.1–10 Hz
f = 1 kHz
f = 10 Hz
0.1–10 Hz
RL
RL
RL
RL
=
=
=
=
600 Ω
200 Ω
100 Ω
50 Ω
Typ
±10
±2
±60
136
134
95
8
±50
130
1
1
30
0.6
0.7
1.4
80
23
±14
±13.5
±10
±5
±30
±5
no load
4
Max
±50
±150
±18
42
6.5
Unit
µV
nA
nA
dB
dB
MHz
MHz
V/µs
dB
√
nV/ Hz
√
nV/ Hz
nVPP
Hz
√
pA/ Hz
√
pA/ Hz
pAPP
Hz
V
V
V
V
mA
V
mA
µA
ar
y
Chapter 3
Absolute Maximum Ratings
Ratings
±22 V
VCC + 0.7 V
VEE − 0.7 V
±100 mA
3W
Indefinite Within Maximum Power Dissipation
−65◦ C to +125◦ C
−40◦ C to +85◦ C
300◦ C
im
in
Parameter
Supply Voltage
Input Voltage
Differential Input Current
Maximum Power Dissipation
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)
Pr
el
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
5
ar
y
Chapter 4
im
in
Typical Performance
Characteristics
Pr
el
The following typical performance characteristics apply for TA = +25◦ C, VS =
±15 V and the amplifier fully warmed up unless otherwise noted.
6
Distribution of Inverting Input Bias Current, 87 Units
20
18
18
16
16
14
14
12
10
8
12
10
8
6
6
4
4
2
2
0
−150
−50
0
50
noninverting input bias current [nA]
100
0
−150
150
−100
−50
0
50
inverting input bias current [nA]
100
150
im
in
−100
ar
y
percentage of untis [%]
percentage of untis [%]
Distribution of Noninverting Input Bias Current, 87 Units
20
Distribution of Input Offset Current, 87 Units
60
Offset Voltage Warm Up Drift, 10 Representative Units
20
10
50
0
−10
offset [µV]
percentage of untis [%]
40
30
−20
−30
20
−40
10
0
−20
el
−50
−15
−10
−5
0
5
input offset current [nA]
10
15
−60
20
0
50
Input Bias Current Warm Up Drift, 10 Representative Units
100
4
input bias current [nA]
input bias current [nA]
6
50
0
−50
−6
150
200
250
time [s]
300
350
400
350
400
450
500
−2
−150
100
300
0
−4
50
250
time [s]
2
−100
0
200
Input Offset Current Warm Up Drift, 10 Representative Units
150
−200
150
8
Pr
200
100
450
−8
500
7
0
50
100
150
200
250
time [s]
300
350
400
450
500
4
3
3
2
2
1
1
error voltage [µV]
4
0
ï1
0
ï1
ï2
ï2
ï3
ï3
ï4
ï4
ï5
ï10
ï8
ï6
ï4
ï2
0
2
output voltage [V]
4
6
8
ï5
ï10
10
ar
y
DC Transfer Characteristics, 2001 Load
5
ï8
ï6
ï4
DC Open Loop Gain, 6001 Load
140
10
DC Open Loop Gain, 2001 Load
open loop gain [dB]
open loop gain [dB]
130
128
126
132
130
128
126
124
124
122
el
122
ï8
ï6
ï4
ï2
0
2
output voltage [V]
4
6
8
120
ï10
10
Open Loop Gain
Pr
70
100
90
80
70
phase
50
60
40
50
30
40
20
30
gain
10
phase margin [°]
60
open loop gain [dB]
8
134
132
20
0
−10
1k
6
136
134
80
4
138
136
90
0
2
output voltage [V]
140
138
120
ï10
ï2
im
in
error voltage [µV]
DC Transfer Characteristics, 6001 Load
5
10
10k
100k
1M
10M
0
100M
frequency [Hz]
8
ï8
ï6
ï4
ï2
0
2
output voltage [V]
4
6
8
10
Voltage Noise Density
Voltage Noise Density
10
voltage noise density [nV/√Hz]
1
0.1
10
100
1k
1/f corner
↓
1
0.1
0.1
10k
ar
y
voltage noise density [nV/√Hz]
10
1
10
100
frequency [Hz]
im
in
frequency [Hz]
Current Noise Density
10
Distribution of Current Noise Density 1/f Corner Frequency, 84 Units
30
20
percentage of untis [%]
current noise density [pA/√Hz]
25
1/f corner
↓
1
15
10
0.1
10
el
5
100
1k
0
10
10k
15
20
25
1/f corner frequency [Hz]
frequency [Hz]
0.1−10 Hz Voltage Noise
50
35
0.1−10 Hz Current Noise
200
Pr
40
30
150
30
100
20
50
current [pA]
voltage [nV]
10
0
−10
0
−50
−20
−100
−30
−150
−40
−50
0
1
2
3
4
5
time [s]
6
7
8
9
−200
10
9
0
1
2
3
4
5
time [s]
6
7
8
9
10
Distribution of 1 kHz Voltage Noise Density, 84 Units
Distribution of 10 Hz Voltage Noise Density, 84 Units
30
20
18
25
16
14
15
12
ar
y
percentage of untis [%]
percentage of untis [%]
20
10
8
10
6
4
5
2
0.85
0.9
0.95
1
1.05
voltage noise density [nV/√Hz]
1.1
1.15
0
0.8
1.2
0.85
0.9
Distribution of 1 kHz Current Noise Density, 84 Units
30
Distribution of 10 Hz Current Noise Density, 84 Units
percentage of untis [%]
percentage of untis [%]
10
15
10
5
el
5
0.55
0.6
0.65
0.7
0.75
current noise density [pA/√Hz]
0.8
0.85
0
0.9
1
1.1
Voltage Noise Density Warmup Drift, 5 Representative Units
Pr
0.9
current noise density [pA/√Hz]
voltage noise density [nV/√Hz]
1.1
1.05
1
0.95
0.65
250
time [s]
300
350
400
450
1.8
1.9
2
0.75
0.85
200
1.7
0.8
0.7
150
1.4
1.5
1.6
current noise density [pA/√Hz]
0.85
0.9
100
1.3
Current Noise Density Warmup Drift, 5 Representative Units
0.95
50
1.2
1
1.15
0
1.2
20
15
0.8
1.15
25
20
1.2
1.1
30
25
0
0.5
0.95
1
1.05
voltage noise density [nV/√Hz]
im
in
0
0.8
0.6
500
10
0
50
100
150
200
250
time [s]
300
350
400
450
500
−110
−110
−120
−120
−130
−130
−140
−140
−150
−150
−160
10
100
1k
−160
10
10k
100
THD+N (Inverting Configuration, 10 Hz, 600Ω Load, 22 kHz Bandwidth)
−100
−120
THD+N [dB]
THD+N [dB]
THD+N (Inverting Configuration, 10 Hz, 200Ω Load, 22 kHz Bandwidth)
−110
−120
−130
−140
−130
−140
−150
el
−150
−20
−15
−10
−5
0
5
amplitude [dBu]
10
15
20
−160
−25
25
−20
THD+N (Inverting Configuration, 100 Hz, 600Ω Load, 22 kHz Bandwidth)
−120
−120
THD+N [dB]
THD+N [dB]
−110
−130
−140
−150
−150
−15
−10
−5
0
5
amplitude [dBu]
10
15
−5
0
5
amplitude [dBu]
10
15
20
25
20
25
−130
−140
−20
−10
THD+N (Inverting Configuration, 100 Hz, 200Ω Load, 22 kHz Bandwidth)
−110
−160
−25
−15
−100
Pr
−100
10k
−100
−110
−160
−25
1k
frequency [Hz]
im
in
frequency [Hz]
ar
y
THD+N (Inverting Configuration, +20 dBu, 200Ω Load, 80 kHz Bandwidth)
−100
THD+N [dB]
THD+N [dB]
THD+N (Inverting Configuration, +20 dBu, 600Ω Load, 80 kHz Bandwidth)
−100
20
−160
−25
25
11
−20
−15
−10
−5
0
5
amplitude [dBu]
10
15
−110
−120
−120
THD+N [dB]
−110
−130
−130
−140
−140
−150
−150
−160
−25
−20
−15
−10
−5
0
5
amplitude [dBu]
10
15
20
−160
−25
25
ar
y
THD+N (Inverting Configuration, 1 kHz, 200Ω Load, 22 kHz Bandwidth)
−100
−20
THD+N (Inverting Configuration, 10 kHz, 600Ω Load, 80 kHz Bandwidth)
−100
10
15
20
25
20
25
THD+N (Inverting Configuration, 10 kHz, 200Ω Load, 80 kHz Bandwidth)
THD+N [dB]
THD+N [dB]
−140
−130
−140
−150
el
−150
−20
−15
−10
−5
0
5
amplitude [dBu]
10
15
20
−160
−25
25
THD+N (Noninverting Configuration, +20 dBu, No Load, 80 kHz Bandwidth)
Pr
−110
−120
THD+N [dB]
0
5
amplitude [dBu]
−120
−130
−130
−140
−150
−160
10
−5
−110
−120
−100
−10
−100
−110
−160
−25
−15
im
in
THD+N [dB]
THD+N (Inverting Configuration, 1 kHz, 600Ω Load, 22 kHz Bandwidth)
−100
100
1k
10k
frequency [Hz]
12
−20
−15
−10
−5
0
5
amplitude [dBu]
10
15
Distortion Residual FFT (Inverting Configuration, 1 kHz, 600Ω Load)
Distortion Residual FFT (Inverting Configuration, 1 kHz, 200Ω Load)
−120
−120
−130
−130
−140
−140
−150
−150
−157.9 dB
−160
−174.4 dB
−180
−180
−190
−190
−200
−200
−210
−210
−220
0
1k
2k
3k
4k
5k
6k
frequency [Hz]
7k
8k
9k
−220
10k
−165.2 dB
−170
ar
y
−170
level [dB]
−164.9 dB
−174.5 dB
−185.5 dB
0
1k
Distortion Residual FFT (Inverting Configuration, 10 kHz, 600Ω Load)
−120
5k
6k
frequency [Hz]
7k
8k
9k
10k
90k
100k
Distortion Residual FFT (Inverting Configuration, 10 kHz, 200Ω Load)
−140
−150
−152.4 dB
−150
−157.1 dB
−157.8 dB
−162.6 dB
−160
level [dB]
−160
level [dB]
4k
−130
−140
−169.8 dB −169.3 dB
−172.6 dB
−170
−180
−160.4 dB
−159.3 dB −159.8 dB
−165.1 dB
−172.5 dB
−170
−180
−190
−190
−200
−200
−210
0
el
−210
10k
20k
30k
40k
50k
60k
frequency [Hz]
70k
80k
90k
−220
100k
Pr
−130
−150
−150
level [dB]
−173.8 dB
−180.9 dB
−210
−210
−220
3k
4k
80k
−164.4 dB
−171.8 dB
−173.4 dB
−174.6 dB −175.7 dB
−176.9 dB
−187.2 dB
−200
2k
70k
−180
−200
1k
50k
60k
frequency [Hz]
−167.1 dB
−190
0
40k
−170
−190
−220
30k
−161.9 dB
−160
−162.4 dB
−180
20k
−130
−140
−170
10k
−120
−140
−160
0
Distortion Residual FFT (Noninverting Configuration, 10 kHz, No Load)
Distortion Residual FFT (Noninverting Configuration, 1 kHz, No Load)
−120
level [dB]
3k
−186.1 dB
−120
−130
−220
2k
im
in
level [dB]
−160
5k
6k
frequency [Hz]
7k
8k
9k
10k
13
0
10k
20k
30k
40k
50k
60k
frequency [Hz]
70k
80k
90k
100k
Overload Recovery, No Load, ±15 V Supplies
Current Limiting, 50Ω Load
15
8
6
10
4
5
0
0
−2
−5
−4
−10
−6
0
0.2
0.4
0.6
0.8
1
time [ms]
1.2
1.4
1.6
1.8
−8
2
Slew−Rate, Inverting (RFB = 10 kΩ || 10 pF)
15
10
amplitude [V]
5
49.9 V/μs
0
50.2 V/μs
−5
0.5
1
1.5
2
2.5
time [μs]
3
3.5
4
4.5
5
Pr
0
el
−10
−15
0
0.2
0.4
0.6
0.8
im
in
−15
ar
y
amplitude [V]
amplitude [V]
2
14
1
time [ms]
1.2
1.4
1.6
1.8
2
ar
y
Chapter 5
Theory Of Operation
Discrete vs. IC Operational Amplifiers
im
in
5.1
Pr
el
Operational amplifiers fabricated as integrated circuits (IC) are in ubiquitous
use due to their low cost, small size and generally speaking good performance.
However discrete amplifier implementation offers substantial advantages if highest
performance is in demand; hence this route has been taken for the OP1-BP.
Within an integrated circuit all components are tightly thermally coupled.
This results in considerable interaction of the various amplifier stages; particularly
troublesome is differential heating of the input stage as a result of output stage
power dissipation. This alters open loop gain and causes additional low-frequency
and intermodulation distortion. With a discrete implementation input and output
stage (as well as any other critical circuitry) can be physically separated by a
suitable layout. As thermal coupling then mostly happens through air (which
is a weak thermal conductor) thermal effects are most effectively reduced to
insignificant levels.
Amplifiers implemented as integrated circuit typically include parasitic semiconductor elements (mostly diodes) which connect to the IC substrate. The
associated voltage-dependent junction capacitances can lead to excess highfrequency distortion at critical amplifier nodes. Particularly objectionable is
voltage dependent capacitance at the opamp noninverting input; this will lead to
very high levels of distortion if the amplifier is used in a noninverting configuration
and driven from a high source impedance. Discrete circuits are inherently free
from parasitic substrate elements and hence do not suffer from these deficiencies.
The maximum power dissipation of typical IC packages (in particular the
more recent SMD types) is very restricted. This limits both quiescent current
and maximum output current to values below that required for best distortion
performance and load driving capability. The package used for the OP1-BP can
dissipate several Watts; this allows optimum definition of bias conditions and
enables direct drive of very low impedance loads.
15
VCC
R3
R4
I5
I2
I6
Q6
Q8
C2
Q9
Q10
Q11
ar
y
Q5
Q16
Q4
Q3
C1
R7
+IN
Q1
Q14
Q2
GND
L1
Q17
R2
Q7
D1
D2
-IN
im
in
Q13
Q12
I1
OUT
R8
V1
R1
Q15
I3
R5
R6
I4
I7
Figure 5.1: OP1-BP simplified schematic.
Pr
el
Inductors of reasonable high value cannot be manufactured with current (and
likely any future) IC technology. The use of inductors in the input stage of the
OP1-BP however enable a unique combination of high slew-rate and very low
noise. This is achieved without use of nonlinear slew-enhancement techniques
(such as dynamic input stage current boosting) which typically result in excess
high-frequency distortion.
While resistors and capacitors manufactured on IC substrates can be designed
to have excellent matching characteristics their absolute tolerance is typically
quite poor (10 % or even worse), at least unless trimming techniques are used.
Due to the exclusive use of precision resistors, inductors, capacitors and bias
voltage reference elements the consistency of the OP1-BP is exemplary. In
addition to this discrete passives offer lower noise, lower voltage coefficient and
better stability over typical IC implementations.
5.2
Amplifier Architecture and Implementation
The OP1-BP features an architecture and implementation with unique properties
resulting in performance far superior to previously available operational amplifiers.
Figure 5.1 shows a simplified schematic of the amplifier. The input stage (Q1,
Q2) is designed to have frequency-dependent transconductance. At low and
medium frequencies (up to about 50 kHz) the transconductance is high because
L1 shorts the emitter degeneration resistors R1 and R2. This provides high open
16
VEE
Pr
el
im
in
ar
y
loop gain and low voltage noise at these frequencies. At high frequencies (above
50 kHz) the degeneration resistors R1 and R2 become active and reduce the
input stage transconductance. This allows the choice of low-value compensation
capacitors (C1, C2) for very high slew-rate and excellent large signal bandwidth.
The collectors of the input differential pair (Q1, Q2) are bootstrapped to
the common-mode input voltage by means of cascode transistors Q3 and Q4.
This benefits both CMRR and PSRR of the amplifier and minimises the thermal
dissipation of Q1 and Q2 which in turn lowers voltage noise and sensitivity to
thermal gradients. The bootstrapping cascode connection also greatly increases
the common-mode input impedance of the amplifier, and reduces the voltage
dependence of this parameter. The later is particularly important if the amplifier
is used in a noninverting configuration and driven by a high source impedance.
Significant voltage dependence of the common-mode input impedance results
in considerable distortion as the amplifier input impedance forms a nonlinear
voltage divider together with the source impedance. Further improvement of
the common-mode performance is achieved by the use of a precision, very high
impedance current generator I1 for the input stage.
R3 and R4 are factory trimmed for lowest input offset voltage and drift. Input
bias current compensation (not shown in the simplified schematic) is employed
to reduce DC errors from bias currents flowing into source and feedback resistors.
The conventional bias current compensation schemes typically used in operational
amplifiers increase current noise and voltage dependence of the common-mode
input impedance. Due to particular attention in the design of the OP1-BP these
effects are effectively eliminated.
The second stage (Q8–Q13) features a differential topology. The resulting
fully balanced interface to the first stage enables very high CMRR along with
high open loop gain and low drift. The Miller compensation with capacitor C2 is
carried out with reference to the ground pin (note the ground connection of C1).
In other words the output of the amplifier at high frequencies is referenced to the
ground potential. For essentially all conventional amplifiers the output at high
frequencies is referenced to one supply rail, resulting in poor high frequency power
supply rejection. The PSRR of the OP1-BP is largely frequency independent
within the audio frequency range. The Miller compensation loop formed by C2
includes the output stage; this reduces output impedance and distortion.
The output stage (Q14–Q17) is a folded darlington type. It combines high
output voltage swing with low output impedance, excellent distortion characteristics and good thermal stability. Bias is factory set such that for output
currents up to ±30 mA class A operation is ensured; the user can adjust the
class A output current to values from about ±10 mA to ±50 mA by means of
a trimmer (see section 6.3). The output current limiting circuitry (not shown
in the simplified schematic) features output voltage dependent current limiting
(i.e. for output voltages near the supply voltage maximum output current is
17
5.3
ar
y
increased). In contrast to the typically used constant current limiting this greatly
improves load driving capability and amplifier protection.
Particular attention has been paid to the thermal management of the amplifier.
The output stage can dissipate considerable power, which should not affect the
operating conditions of the small-signal stages; this has been achieved by thermal
isolation of the small-signal stages from the output stage transistors. The biasing
circuit of the amplifier is designed to keep performance independent of ambient
temperature. In particular slew-rate and output stage quiescent current are kept
constant with temperature. Amongst other design techniques this is a result
of the extensive use of dual matched transistors which ensure tight tracking of
important parameters.
Manufacturing Information
Pr
el
im
in
The manufacturing process of the OP1-BP is targeted for best performance,
consistency and reliability. After the four layer printed circuit board is assembled
and soldered the output stage heatsink is attached with a high-performance
adhesive for a reliable, low loss connection. The fully assembled amplifier circuit
is now exposed to several thermal cycles. This burn-in procedure ensures very
stable operation afterwards, particularly regarding DC precision and the various
bias points. Subsequently offset voltage, input bias current and class A output
current are trimmed with the amplifier fully warmed up. Extensive testing of
each specimen is carried out for several critical parameters.
18
ar
y
Chapter 6
Applications Information
Noise and Source Impedance Considerations
im
in
6.1
√
The very low voltage noise density of 1 nV/ Hz at 1 kHz is achieved by the use of
input transistors with low base spreading resistance and high collector currents.
Unlike typical operational amplifiers the current noise density is simultaneously
√
kept low at 0.7 pA/ Hz (1 kHz).1 For optimum noise performance it is however
important to consider the effects of source resistance and amplifier noise current.
To calculate the total input-refered voltage noise density three contributions
need to be considered:
• Thermal noise density of the source resistance:
√
4kT · RS
• Voltage noise density of the amplifier: eN
el
• Current noise density of the amplifier: iN · RS
Pr
p
The overall amplifier noise contribution is then given by e2N + (iN · RS )2
p
and the total noise by 4kT · RS + e2N + (iN · RS )2 . These two functions and
thermal source resistance noise density are plotted in figure 6.1 and 6.2 for source
resistances from 10 Ω to 100 kΩ. The graphs are valid for both balanced and
unbalanced source resistance configurations as there is no significant commonmode current noise.
It can be seen that opamp voltage noise density dominates for source resistances below 65 Ω only at both 1 kHz and 10 Hz. For source resistances
above 33 kΩ opamp current noise density is the major contribution at 1 kHz; the
according source resistance at 10 Hz is 8.3 kΩ.
Reactive source impedances (capacitors and inductors) do not have an intrinsic thermal noise contribution. However, the amplifier current noise iN still
contributes to total voltage noise. The OP1-BP is an optimum choice for low
1 The
current noise density of a typical IC amplifier with a voltage noise performance similar
√
to the OP1-BP is around 2 pA/ Hz at 1 kHz.
19
100
ar
y
voltage noise density [nV/√ Hz]
total noise →
10
← amplifier noise only
1
im
in
← resistor noise only
0.1
10
100
1k
source resistance [Ω]
10k
100k
Figure 6.1: Input-refered voltage noise density vs. source resistance at 1 kHz.
total noise →
10
Pr
voltage noise density [nV/√ Hz]
el
100
← amplifier noise only
1
0.1
10
← resistor noise only
100
1k
source resistance [Ω]
10k
100k
Figure 6.2: Input-refered voltage noise density vs. source resistance at 10 Hz.
20
noise provided the total source impedance (which includes the feedback network)
is kept below about 20 kΩ (at 1 kHz) or 5 kΩ (at 10 Hz).
6.2
Low Distortion Implementation
Pr
el
im
in
ar
y
The OP1-BP is particularly suited for low distortion applications. Unlike typical
amplifiers its distortion performance is to a great extent independent of load
impedance, source impedance and magnitude of common-mode AC input voltage.
Implementations for low distortion often have involved compromises with respect
to noise and/or complexity. This is not necessary with the OP1-BP, and high
performance signal pathes result even with basic textbook circuits.
For full benefit of the excellent opamp performance attention to the passive
components of the feedback network is needed. Low-value feedback resistors
can dissipate considerable power (e.g. 0.5 W peak for a 560 Ω resistor at full
output swing of ±17 V). To avoid introduction of low-frequency distortion due
to the temperature coefficient of these resistors the use of precision resistors
with sufficient power rating and low temperature coefficient is necessary. Also of
concern is the voltage coefficient of resistors. Metal film and wirewound resistors
typically are axcellent with this respect; if in doubt the use of series-connected
resistors instead of one single part should be considered to reduce the voltage
swing across the resistor.
Capacitors which experience considerable AC voltage swing at frequencies
of interest (e.g. in equalising and filtering networks) should have low voltage
coefficient. Suitable dielectrica include ceramic C0G/NP0, polypropylene film,
R film. Again the use of multiple series-connected
polystyrene film and Teflon
capacitors instead of a single part may be considered to reduce voltage swing
and hence distortion.
Lowest amplifier distortion is achieved for output currents which operate
the output stage in class A. Due to the high current gain of the output stage
and the inclusive Miller compensation distortion is still notably low in class AB
operation; however additional care must be given to the layout as the power
supply traces now carry heavily distorted (essentially rectified) signal-dependent
AC currents. These can induce into sensitive circuitry and cause distortion if
left unchecked. Routing of the power supply traces carrying the distorted AC
currents should be spaced away from sensitive (e.g. strongly inductive, high
impedance or low level) nodes. Additionally negative and positive supply should
be routed in close proximity as their added magnetic fields ideally result in an
undistorted replica of the opamp output current.
6.3
Class A Output Current Adjustment
The quiescent current of the output stage can be adjusted by a trimmer; this
allows a user-defined trade-off between quiescent power dissipation and maximum
21
VQ
=
ar
y
class A output current. The typical trimming range for the class A output current
is ±10 mA to ±50 mA.
There are two trimmers on the OP1-BP printed circuit board. The one used
to set the output stage quiescent current is located close to the power output
transistors and not sealed. In the corner of the printed circuit board next to
the output stage there are two test points which are used to measure the actual
quiescent current. To achieve a class A peak output current IOU T the DC voltage
across the two test points2 VQ must be set as follows:
4.1 Ω · IOU T + 7 mV
(6.1)
6.4
im
in
During the measurement it is recommended that the operational amplifier is
operated with zero output current and fully warmed up. Also the class A output
current shows a slight dependence on power supply voltage; typically it decreases
by about 18 % when going from ±5 V to ±18 V power supplies. Hence adjustment
should be done at the correct power supply voltage.
The operational amplifiers are factory preset to a class A peak output current
of ±30 mA with ±15 V power supplies; this value will be sufficient for full class
A operation in most cases.
DC Precision
Pr
el
There are three amplifier parameters which influence its DC precision at a given
temperature: offset voltage, input bias current and input offset current. The
offset voltage of the OP1-BP is trimmed to a very low value of typically ±10 µV
with the amplifier fully warmed up. As the offset and drift contribution of the
second amplifier stage have been kept low zeroing the amplifier offset voltage
will also lead to very low offset voltage drift. As there is hence no need for
further offst voltage trimming the according trimmer is sealed after adjustment
to prevent inadverted readjustment.
For configurations where the input terminals of the amplifier see a source
resistance unbalance of more than 170 Ω input bias current will typically dominate DC precision. It is hence possible to further increase the DC precision by
external input bias current cancellation. Figure 6.3 displays the suggested implementation for a noninverting amplifier (typically RS R1 k R2 ) configuration;
other amplifier configurations may use a similar bias cancellation scheme. To
approximately track the temperature coefficient of the input bias current the
cancellation current is derived from forward biased diodes. This also ensures low
noise contribution.
The input bias current cancellation scheme of the OP1-BP has been designed
to contribute little to input offset current; only with well balanced source
2 The two test points are isolated by resistors, so accidentally shorting the test points will
not damage the amplifier.
22
+15V
R3
13k
D1
1N4148
R6
10M
R7
10M
C1
ar
y
D2
1N4148
D3
1N4148
R5
100k
GND
D4
1N4148
D5
1N4148
R1
D6
1N4148
OUT
R4
13k
R2
im
in
RS
-15V
GND
GND
Figure 6.3: Input bias current cancellation.
el
resistances above 5 kΩ will the amplifier offset current dominate DC precision.
In such cases the cancellation scheme of figure 6.4 may be used. Again the
reference voltage is derived from forward biased diodes for low noise and suitable
temperature coefficient. Shown is a differential amplifier configuration (R1 = R2
and R3 = R4 ), but a similar offset current cancellation scheme may be used
for other amplifier configurations with matched source resistances at the input
terminals.
Ground Pin Connection
Pr
6.5
The ground pin of the amplifier should be connected to a signal ground point
with low high-frequency impedance; for proper operation the ground potential
should be approximately in between the two supply rails, and needs to be able
to supply a DC current of 10 µA. Operation with ground potentials as close as
2 V to the supply rails is possible but not recommended as it might adversely
affect the internal thermal balance of the amplifier circuit.
6.6
Feedback Capacitor Selection
Due to the frequency-dependent gain bandwith product of the OP1-BP simple
resistive feedback results in gain peaking and overshoot. This is easily avoided
23
+15V
R7
R5
13k
10M
R6
1M
R8
D1
1N4148
10M
R3
ar
y
D2
1N4148
C1
D3
1N4148
R1
GND
OUT
R2
R4
GND
im
in
GND
C2
Figure 6.4: Input offset current cancellation.
by the use of a suitable feedback capacitor. Figure 6.5 shows recommended
minimum time constant values t for the RC feedback network. For a given
feedback resistor value RFB the minimum feedback capacitor value CFB can be
estimated as follows:
t
CFB =
2π · RFB
Pr
el
If overshoot-free transient response is not necessary, the capacitor values can
be chosen about 30 % lower for maximum bandwidth. This will still avoid gain
peaking.
In any case the time constant as shown in figure 6.5 should be considered an
initial estimate only. Details of the exact implementation (e.g. feedback network
impedance and layout stray capacitances) may affect the required feedback
capacitor value and experimental verification is needed.
6.7
Power Supply Bypassing and Layout Considerations
The OP1-BP includes a total of 2.4 µF of high quality, low impedance on-board
decoupling capacitors. Together with the excellent power supply rejection of the
amplifier this is in essentially all cases sufficient for stability and no external
high-frequency bypassing is needed. With long power supply traces and low
impedance loads it is nonetheless advisable to arrange for electrolytic bypass
capacitors from the supply rails to load ground. Recommended values range
from 47 µF to 220 µF.
For best performance and stable operation care to layout is needed. It is
recommended to place the feeback network below the amplifier for short traces
24
12
10
ar
y
time constant [µs]
8
6
4
im
in
2
0
1
10
100
1k
noise gain
Figure 6.5: Minimum time constant of RC feedback network vs. noise gain for
overshoot-free transient response.
and minimum layout parasitics (particularly stray capacitance at the inverting
input). Ground planes should be used.
Driving Capacitive Loads
el
6.8
Pr
Due to its output stage with very low output impedance the OP1-BP is able
to drive high capacitive loads directly, typically up to 1 nF. Higher or unknown
capacitive loads (e.g. cables) should be isolated by a small resistor in series with
the amplifier output. To be effective the feedback point must be taken before
the isolation resistor. A value of 30 Ω for the isolation resistor will in most cases
enable unlimited capacitive drive, however experimental verification is suggested
and lower values might be suitable for certain conditions (e.g. if the capacitive
load is limited to a known maximum value). If low output impedance at low
frequencies is required the isolation resistor may be paralleled by an inductor.
For low distortion this inductor should be air cored only; as initial value for
experimental verification 3 µH or higher is recommended.
6.9
Sockets and Handling
It is recommended to use sockets for the OP1-BP instead of direct soldering to
the printed circuit board. Suitable sockets are available from Mill-Max as part
no. 0344-2-19-15-34-27-10-0; other manufacturers offer compatible parts.
25
Pr
el
im
in
ar
y
When handling the amplifiers, particularly during insertion into the sockets,
care should be applied in order to not bend or otherwise damage any amplifier
part. It is recommended to hold the amplifier at the printed circuit board only;
in particular any stress to the power output transistors, heatsink and trimmers
should be avoided.
26
ar
y
Chapter 7
Pr
el
im
in
Outline Dimensions and
Pinout
27