!"$ $ $! !%
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Coding guidelines for behavioral modeling and a process for generating
wire load models that satisfy most timing constraints early in the design
cycle are some of the techniques used in the design process for standard
cell ASICs.
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 Hewlett-Packard Company 1995
*''*2$)" /# . "0$ '$) . ''*2. 0. /* 1*$ ()4 /$( 6
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. +*..$' Behavioral
Model (HDL)
Custom Wire
Models
Logic
Synthesis
(Synopsys)
Netlist and Timing
Constraints
Placement and
Routing
(Cell3)
Capacitance
Static Timing
Verification
(Synopsys)
Artwork
Verification
and Output
.$ .$") !'*2
-0-4 2' //6&- *0-)'
Coding Guidelines. The HDL coding guidelines mentioned
above enable the creation of behavioral models that synĆ
thesize predictably in a shorter amount of time with better
performance than those created without guidelines.
Generic Synthesis Script. To streamline synthesis we create
generic synthesis scripts for our design that contain all of the
designĆspecific constraints such as flipĆflop types, clock
speed, behavioral model locations, and so on. These scripts
also include input and output timing constraints, external
loading, and drive capability. The scripts are used to syntheĆ
size all submodules in the design from the bottom up. Only
those modules that do not meet timing requirements when
incorporated into their parent module are resynthesized with
scripts written specifically for them. This allows the majority
of the blocks to be synthesized very quickly. Fig. 2 shows a
portion of a generic synthesis script.
Custom Wire Load Models. One of our primary goals is to perĆ
form a single route without any iteration. To accomplish this,
the wire loading (capacitance on the line) estimates that are
used during synthesis have to be conservative. However, if
they are too conservative then it is not possible to meet perĆ
formance goals. To determine a wire loading model with the
appropriate amount of conservative estimation for our library
and tool methodology, we performed several wire loading
experiments. These experiments consisted of synthesizing
modules of various sizes and design types, routing them,
and then verifying that their performance with actual wire
loads satisfies the timing constraints defined for the module.
Several passes were done for each module using a wire load
model with varying levels of conservatism. Fig. 3 summarizes
the process we used to generate the wire
/* These are fragments from the generic Synopsys dc_script */
/* the full script can be easily modified for a given model */
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
/* Read in Verilog HDL:
*/
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
read -f verilog mymodule.v
check_design
/* –––––––––––––––––––––––––––––––––––––––
/* Set the wire load model:
/* –––––––––––––––––––––––––––––––––––––––
set_wire_load block –library wire_loads
*/
*/
*/
*/
*/
/* –––––––––––––––––––––––––––––––––––––––
*/
/* Define the clocks:
*/
/* –––––––––––––––––––––––––––––––––––––––
*/
create_clock CLK –period 20 –waveform {0 10}
set_clock_skew –plus_uncertainty 0.5 –minus_uncertainty 0.5 –propagated CLK
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
/* Set block operating environment:
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
loader_pin = hp_cmos26g_table_slow/INVFF/A
driver_pin = hp_cmos26g_table_slow/NINVFF/Q
set_load 3 * load_of(loader_pin) all_outputs()
set_load load_of(loader_pin) all_inputs()
set_drive drive_of(loader_pin) all_inputs()
set_input_delay 10 –clock CLK all_inputs()
set_output_delay 10 –clock CLK all_outputs() –max
*/
*/
*/
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
/* Compile the design
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
compile
*/
/* ––––––––––––––––––––––––––––––––––––––––––––––
*/
/* Write out results
*/
/* ––––––––––––––––––––––––––––––––––––––––––––––
*/
write –hierarchy –f verilog –output mymodule.vopt
write_constraints –format sdf –output mymodle. sdf –max_paths 1000
report_design >> mymodule.sn_rpt
report_hierarchy –full >> mymodule.sn_rpt
report_timing >> mymodule.sn_rpt
A portion of a generic synthesis script.
February 1995 HewlettĆPackard Journal
*/
Original Wire
Load Models
Capacitance*
Logic
Synthesis
Place and
Route
Actual
Capacitance
Check
Timing
Timing
Constraints
Met?
No
Create more pessimistic
capacitance models based
on data from route.
Yes
Wire Load Model
Is Sufficiently
Pessimistic
*Estimated Capacitance Based on Fanout
The process for generating wire load models.
load model. This process was necessary because initial wire
load estimates might be too optimistic. For example, the
initial capacitance estimate for one connection between two
inverters might be 0.04 pF, but after placement and routing
the actual capacitance could be 0.1 pF, which might cause
the chip's timing constraints not to be met.
During these experiments, each module was first synthesized
using average wire load estimates. After routing, if the modĆ
ules failed timing, additional experiments were performed
using a progressively more pessimistic wire load model. The
wire load model that was used was generated by selecting a
point in the distribution of actual capacitances for each fanĆ
out that is greater than a given percentage of nets. Fig. 4
shows a sample distribution of interconnect capacitance for
nets with a fanout of two in a typical module. In this examĆ
ple, we wanted to use a model that would predict a capaciĆ
tance such that 90% of the wires would typically have actual
capacitance less than the predicted value. To do this we simĆ
ply used the capacitance value from the distribution that was
greater than 90% of the other wire capacitances. This was
done for each fanout to create a synthesis wire load model
called a 90% model."
We used this method to test models that fell within the
50ĆtoĆ95Ćpercent range. We found that unless we used at
least a 90% wire loading model we had some timing violaĆ
tions after backĆannotation* that were not present during
synthesis with estimated loads.
We also discovered that the magnitude and distribution of
the routed capacitance were fairly consistent across a wide
* Back-annotation in this context refers to the process of taking the actual capacitance values
extracted from routing and using them during static timing analysis.
 Hewlett-Packard Company 1995
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"$**1
Library Default
(Average)
Number of Nets
90% Point (90% of Nets Are below this Value)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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0
50
100
150 200 250 300 350 400
Interconnect Capacitance (fF)
450
500
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1- 2' 2 2'$0$ 0$ ,- 2(+(,& -0 -.$0 2(,& "-,#(2(-, 4(-* 2(-,1
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* Global wires are the interconnecting wires between submodules on a chip.
 Hewlett-Packard Company 1995
** Cell3 is the placement and routing program we use, which comes from Cadence Design
Systems.
$!03 07 $5*$229 ") 0# -30, *
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57;< 01/0C8-:.7:5)6+- ;<)6,):, +-44 %;
Table I
Cell3 to Synopsys Correlation
Timing
Analyzer Data
Cell3 (twoparameter)
Cell3 (threeparameter)
!1615=5
#)<0
6;
6;
6;
!)@15=5
#)<0
6;
6;
6;
•
•
-);< ::7:
>-:;=; %A678;A;
•
:-)<-;< ::7:
>-:;=; %A678;A;
::7: $)6/>-:;=; %A678;A;
<7
<7
; ;07?6 16 &)*4- -44; <0:--C8):)5-<-: 57,-4 8:7C
>1,-; /:-)<4A 158:7>-, ,-4)A 57,-416/ +758):-, <7 <0<?7C8):)5-<-: 57,-4
-+)=;- 7. 1<; 158:7>-, )++=:)+A <0<0:--C8):)5-<-: 57,-4 1; 67? =;-, ); <0- ;<)6,):, ,=:16/
<1516/C,:1>-6 84)+-5-6<
• ++=:)<- -;<15)<-; 7. 16<-:+766-+<
7: ;A6<0-;1; 16<-:+76C
6-+< ,-4)A 1; ;8-+1.1-, *A <0- ?1:- 47), 57,-4;
7:
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Clock Tree Synthesis and Verification. &A81+)4 %% ):- ,:1>-6
*A ;16/4- 7: 5=4<184- 01/0C;8--, +47+3;
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;=++-;;
@+-44-6< :-;=4<; +)6 *- 7*<)16-, *A =;16/
<0- ,-<)14-, *)4)6+-, :7=<-: ?01+0 1; 16+4=,-, ); 8):< 7.
-44; +47+3 <:-- ;A6<0-;1; 78<176
7?->-: ;16+- <01; <774
To Flip-Flops
Clock Input
<A81+)4 +47+3 *=..-: <:--
6;-:<176 ,-4)A .7: <01; +76.1/=:)C
<176 1; <0- )>-:)/- ,-4)A .:75 <0- +47+3 168=< <7 <0- .418C.478;
%3-?
1; <0- ,1..-:-6+- *-<?--6 <0- ;07:<-;< )6, 476/-;< ,-4)A;
-*:=):A -?4-<<C#)+3):, 7=:6)4
•
•
+<=)4 +47+3 ,-4)A )6, ;3-? ):- >-:1.1-, =;16/ <0- $ -@C
<:)+<176 +)8)*141<A 8:7>1,-, 16 0-+3!)<-
&0- /-6-:)4
;<-8; 16>74>-, 16 =;16/ <01; )88:7)+0 16+4=,-
7584-<- <0- 80A;1+)4 1584-5-6<)<176 7. <0- +47+3;
@<:)+< >1) 0-+3!)<- $ 16.7:5)<176 .7: )44 6-<; 16 <0,-;1/6
:-)<- ) %81+- 6-<41;< +76<)1616/ 764A <0- +-44; )6, 6-<; 16
<0- +47+3 <:--;
&0- ,-;1:-, 6-<; )6, +-44; ):- ;8-+1.1-, <7
0-+3!)<-; %81+- ?:1<-:
,, +=;<75 +1:+=1< +76,1<176; -@<-:6)4 47),; -<+
$=6 <0- %81+- 27*
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+76.1,-6+- 16 <0- -44 6=5*-:;
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5)6+- 1;;=-;
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)6, 78<151B)<176
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<;
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1/
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)+01->16/ <0- %; )//:-;;1>- 8-:.7:5)6+- /7)4;
* CheckMate is an artwork verification and parasitic extraction tool from Mentor Graphics Corp.
 Hewlett-Packard Company 1995
550
90
500
80
450
70
400
60
350
Capacitance (fF)
Number of Flip-Flops
100
50
40
300
250
30
200
20
150
10
100
0
6.40
HP C26101SH
Library
HP C26102SH
Library
50
6.45
6.50
6.55
6.60
6.65
6.70
0
Delay (ns)
0
2
4
6
8
10
Fanout
Spice clock delay and skew results.
It is our goal to characterize Cell3's delay calculation to the
point at which we can use its delay numbers for clock skew
verification without the additional complexity of using Spice.
Table II shows the correlation obtained between Cell3 and
Spice for the clocks on the XĆterminal ASIC.
Table II
Cell3 to Spice Correlation
Cell3
Spice
Delta
Best Case
2.84 ns
2.56 ns
-9.9%
Worst Case
2.96 ns
2.57 ns
-13.2%
The results of this correlation are very encouraging. The offset
is relatively constant, and the Cell3 numbers are always
more conservative than the Spice numbers. This is because
Cell3's perĆlayer capacitance constants are intentionally
skewed toward the conservative end of the range.
Wire capacitance versus fanout in two cell libraries. The HP
C26101SH library is the older CMOS26 library.
router model generation provides fully gridded routing and
optimum pin locations, which improves both density and
run time. These factors result in a reduction in average wire
length for a given fanout. The improvement in wire capaciĆ
tance as compared to the previous cell library is shown in
Fig. 7.
Another area of improvement is in the drive sizes of the
cells. The stairstep design"3 approach was used to deterĆ
mine appropriate drive increments. The stairstep design apĆ
proach is a method of sizing gates to provide optimum area
versus performance characteristics for each cell in the liĆ
brary. As a result of using this approach, the HP C26102SH
library provides more drive increments for Synopsys to map
to, avoiding the excessive area penalty imposed when a
higher drive cell must be swapped into a path that is just
missing timing.
The following factors played a part in producing the
results mentioned above and providing a chip that met the
specifications.
Finally, this is the first library to use the more accurate tableĆ
driven Synopsys models. As discussed previously, this allows
more accurate delay calculations and eliminates correlation
issues with other timing verification tools.
Library Design. One of the major contributing factors for
meeting our density and performance goals is the use of
highĆquality libraries such as the new HP C26102SH (0.8 m)
standard cell library. This library is a scaledĆup version of the
HP C14104SH library developed for our CMOS14 (0.5 m)
process.2
Since the HP C26102SH library is a scaledĆup version of the
HP C14104SH library, all these advantages will continue into
the next process generation.
One major improvement introduced with the HP C26102SH
library is that it is tuned for Cell3 while maintaining comĆ
patibility with other routers. For a roughly square core, the
library allows a very even distribution of horizontal and verĆ
tical routing resources. This gives the placer more freedom
to find an optimal solution. The use of advanced layout
techniques, along with the exploitation of new process deĆ
sign rules, allows smaller cells that provide the same funcĆ
tionality as previous library versions. Finally, advanced
 Hewlett-Packard Company 1995
Design Methodology. Our design methodology was carefully
constructed to produce a chip that met aggressive timing
goals in a reasonable amount of time. The 90% wire load
models improved the chances of first time perfect through
the routing cycle, albeit at some loss of performance and die
size. This was an intentional choice designed to minimize the
design cycle time, while still meeting performance targets.
The HDL coding guidelines enabled the creation of a design
that was easily synthesized. They also enabled the use of
automatic scan insertion and test vector generation.
February 1995 HewlettĆPackard Journal
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 Hewlett-Packard Company 1995