Application Note 039
Discussion of Linear Regulators
By Nicolas Reginelli, Paul Musil, and Bryan Horton Anaren Inc. -MSK Products;
Revised 11/24/2015
Introduction
Linear voltage regulators are some of the most cost effective building blocks of power
supplies. Their simple topologies and small footprint make them an excellent choice for
budget designs and compact systems. Three different types of linear regulators exist;
standard, low dropout (LDO) and quasi-LDO. Standard regulators offer the lowest ground
pin current at the cost of requiring the largest minimum voltage drop to maintain output
voltage regulation. LDO regulators are able to maintain regulated output voltages with a
smaller dropout voltage but the ground pin current is typically much higher when compared
to standard regulators. Quasi-LDO regulators have a dropout voltage that typically falls
between that of LDOs and standard regulators and similar can be said of their ground pin
current. The goal of this discussion is to give the reader a basic understanding of linear
regulators and how to determine the best type of linear regulator to use based on the
application.
Standard Linear Regulators
Standard regulators are normally three terminal devices with a VIN, a VOUT and an ADJ or
a GND pin. They typically have an NPN Darlington configuration for the pass transistor.
Figure 1 below shows the simplified schematic for the MSK5251 fixed voltage standard
NPN linear regulator.
Figure 1: MSK5251 Standard Regulator Simplified Schematic
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Pin 1 on the schematic is VIN, pin 2 is VOUT and pin 3 is GND. This configuration is
responsible for the higher dropout voltage relative to an LDO regulator. To maintain
regulation, the pass transistor must have a minimum voltage across it which is approximated
by equation 1 below.
𝑉𝐷 (𝑀𝐼𝑁) = 3𝑉𝐵𝐸
(Equation 1)
The 3VBE is due to the base-to-emitter voltage of both NPN transistors plus the voltage drop
internal to the control circuitry. The dropout voltage of standard regulators tends to fall in
between 1.5V and 2.2V. Dropout voltage is dependent on the load current and temperature
of the transistors. A higher load current will cause the dropout voltage to increase due to an
increase in internal transistor resistance. The ground pin current in fixed standard regulators
such as the MSK5251 is the current that flows through the resistive feedback divider. In
standard regulators with an external output voltage adjust pin, there will be no ground pin
current in the regulator itself but there will be some ground current sourced from the
external feedback network. All of the base current from the pass transistor and the drive
transistor is sourced to the load. Because the Darlington pair emitter output presents a very
low impedance, standard regulators are more inherently stable and require much less
capacitance than LDO regulators.
Low Dropout Regulators
The majority of MSK’s linear regulator offerings are in the Low-Dropout (LDO) category.
The primary difference between LDOs and standard regulators is the pass transistor
network. Traditional LDO regulators only have one PNP transistor as the pass device with
an NPN driver. Figure 2 below shows the simplified schematic of the MSK5450 fixed
voltage LDO regulator. These are now sometimes referred to as “super” or “ultra” LDO
regulators because they have the lowest dropout voltage.
Figure 2: MSK5450 LDO Regulator Simplified Schematic
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Pin 1 on the schematic is VIN, Pin 2 is VOUT and Pin 3 is GND. This configuration reduces
the minimum voltage drop required to maintain regulation. The dropout voltage is given by
equation 2 below.
𝑉𝐷 (𝑀𝐼𝑁) = 𝑉𝐶𝐸𝑆𝐴𝑇
(Equation 2)
MSK offers LDO regulators such as the MSK5810RH with dropout voltages as low as
0.11V at a load current of 1A. Typically, the dropout voltage of an LDO is between 0.7V
and 0.8V at maximum load current. The lower dropout voltage does have a trade-off
however. The ground pin current of an LDO is the highest among the various types of linear
regulators. This is due to only having one PNP transistor as the pass device. The gain is
much lower than that of the pass network in the standard regulator leading to a higher base
current, which translates to a higher ground pin current. Unlike the standard regulator where
the pass transistor base drive current is supplied to the load, the pass transistor base drive
current of the LDO is shunted to the system ground. Ultra LDO regulators typically require
more capacitance than other regulators to bypass the high impedance output. They typically
rely on the zero created by the ESR of the capacitor for stability also.
Quasi-LDO Regulators
Quasi LDO regulators are a subcategory of LDO reglators and are often simply referred to
as LDO regulators. The quasi-LDO uses a PNP gain transistor and an NPN transistor as the
pass device. The dropout voltage is typically between that of an LDO and a standard
regulator, while the ground pin current is similar to a standard regulator. Dropout voltages
of quasi-LDO’s usually do not exceed 1.5V. The minimum voltage drop across the regulator
in order to maintain regulation is approximated by equation 3 below.
𝑉𝐷 (𝑀𝐼𝑁) = 𝑉𝐵𝐸 + 𝑉𝐶𝐸
(Equation 3)
The MSK5971RH is one of MSK’s quasi-LDO offerings with a max dropout voltage of
1.5V at full load current. The MSK5971RH has a maximum adjust pin current of only
120µA at full load current. The quasi-LDO is great for medium-power application where
lower dropout voltages are desired but ultra low dropout is not required. Quasi LDO
regulators typically require much less capacitance for stability than LDO’s but more than
standard linear regulators.
Efficiency
One major drawback of using a linear regulator is that the power dissipation is typically
larger than switching regulators. A linear regulator can be looked at as a variable resistor
where its efficiency is approximated by equation 4 below.
𝜂=
𝑉𝑜 ∗ 𝐼𝑜
𝑉𝐼𝑁 (𝐼𝐼𝑁 + 𝐼𝐺𝑁𝐷 )
𝑥 100%
(Equation 4)
The closer the output voltage is to the input voltage, the better the efficiency will be. A large
voltage drop across the linear regulator will dissipate a lot of power and decrease the
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efficiency substantially. An ideal linear regulator with an input voltage of 5V and an output
voltage of 2.5V will have an efficiency of only 50%. However, a regulator that has an input
voltage of 3.3V with an output voltage of 2.5V will have an efficiency closer to 76%. A
standard regulator would not work in the second scenario but an LDO would. Since an LDO
has a lower dropout voltage than a standard regulator an input voltage closer in value to the
output voltage, can be used, thereby increasing the system efficiency. At larger input and
output voltage differences however, the efficiency of the LDO is lower than that of a
standard regulator at similar conditions due to the ground pin current of the LDO being
shunted to system ground.
Stability
Both standard and LDO regulators use feedback loops in order to keep the output voltage
constant. Along with tight regulation, closed loop feedback brings overall stability into
question. Overall system stability is determined by how much phase shift has occurred at
unity gain. The Bode plot provides a graphical survey of the system stability across a range
of frequencies plotted logarithmically versus the gain in dB. Phase margin is a measure of
how much phase remains when the gain reaches 0dB. In order for a system to be stable the
phase margin technically only needs to be greater than 0° but greater than 45° is preferred.
Gain margin is a measure of how much the loop gain has fallen below 0dB at the point
where the phase crosses 0°. It indicates how much the gain would have to increase to cause
instability. Poles and zeroes of the system are plotted on a Bode plot and contribute a set
amount of gain and phase shift. A pole changes the gain slope by -20dB per decade and adds
-90° of total phase shift. A zero changes the gain slope by +20dB per decade and adds +90°
of total phase shift. The effects of poles and zeroes are additive so each additional pole or
zero will add another -20dB or +20dB per decade to the slope. Typically an LDO regulator
will have more poles than zeroes and will need to have zeroes added in order to compensate.
An LDO left uncompensated will be unstable due to the gain and phase shift of the poles.
Compensation of linear regulators is typically limited to selection of the output capacitance.
Compensation
The standard regulator has a Darlington pair pass transistor connected in the common
collector configuration. The emitter output provides a low impedance at the output of the
regulator pushing the power pole to a very high frequency. Because of this, the standard
regulator is typically considered inherently stable and requires very little capacitance for
stable operation. The PNP pass transistor in a traditional or ultra LDO is connected in
common emitter configuration. The collector output presents a higher impedance that
dominates the power pole frequency (fpo) at light load, see equation 5. This creates a lowfrequency pole with a break frequency that is dependent on both load resistance and output
capacitance. The error amplifier inside the regulator keeps ZO low at very low frequencies
but the EA pole reduces loop gain at higher frequencies proportionately increasing ZO and
adds -90° phase shift. As ZO increases fpo decreases. This second pole, or output pole fpo,
adds another -90° of phase shift. Output capacitance is required to keep ZO sufficiently low
as frequency increases. The output power pole is difficult to precisely locate because it
moves with load impedance and regulator characteristics but it can be understood using
equation 5 on the next page.
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𝑓𝑝𝑜 =
Where,
1
(Equation 5)
2𝜋 𝑥 𝑍𝑃 𝑥 𝐶𝑜𝑢𝑡
ZP = RL // ZO
RL = Load Resistance
ZO = Regulator Output Impedance
A zero must be added to the gain loop to reduce the negative phase shift produced by the
second pole. The zero is derived from the equivalent series resistance or ESR of the output
capacitor. The ESR of a capacitor can be modeled as a resistance in series with a capacitor.
The frequency of the ESR zero can be found with equation 6 below.
𝑓𝑧𝑒𝑟𝑜 =
1
(Equation 6)
2𝜋 𝑥 𝐶𝑜𝑢𝑡 𝑥 𝐸𝑆𝑅
A high ESR will shift the zero to a lower frequency, increasing the bandwidth of the loop
but decreasing the phase margin. A low ESR will increase the frequency of the zero which
will delay any positive phase shift. Positive phase shift is required well before the 0dB
crossing point to increase the phase margin to stable levels. For most LDO applications, a
tantalum capacitor with an ESR between 20mΩ and 50mΩ is sufficient but it is well advised
to follow datasheet recommendations. MSK recommends using the CWR series of tantalum
capacitors for their acceptably low ESR and their performance in extreme applications.
Load Regulation
Load regulation is the ability of the linear regulator to maintain its output voltage despite
changes in load current. It is typically represented as a % change with respect to the output
voltage. Equation 7 defines the load regulation of a linear regulator.
𝐿𝑜𝑎𝑑 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 =
𝑉min_𝑙𝑜𝑎𝑑 − 𝑉max_𝑙𝑜𝑎𝑑
𝑉𝑚𝑖𝑛_𝑙𝑜𝑎𝑑
𝑥 100%
(Equation 7)
Vmin_load is the voltage at the output of the linear regulator at the smallest load current
specified. Vmax_load is the voltage at the output at the largest load current specified. A smaller
load regulation percentage infers a better designed linear regulator. A well designed
regulator should have very little variation in the output when the load changes. There are
some design guidelines that can be followed to improve load regulation. For three-terminal
standard regulators with an adjust pin, it is best to connect the top of the voltage divider as
close to the output pin as possible and the bottom of the divider as close to the load as
possible. This will reduce the parasitic line resistance and improve the load regulation. A
voltage drop on the output line will occur due to the load current. If the top of the voltage
divider is any distance away from the output pin, the lower voltage due to the voltage drop
will force an inaccurate voltage at the adjust pin. Any change in the load current will cause
the adjust pin voltage to fluctuate leading to poor load regulation performance. Figure 3
below illustrates this design practice using the MSK5970RH adjustable regulator.
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Figure 3: Adjust Pin Connection to Improve Load Regulation
The output voltage of the MSK5970RH in the configuration shown above is given by
equation 8 below.
𝑉𝑜 = 𝑉𝑅𝐸𝐹 𝑥 �1 +
𝑅2
𝑅1
� − 𝐼𝑜 𝑅𝑆
(Equation 8)
The drop across the parasitic line resistance is directly subtracted from the feedback term. If
the top of the voltage divider was connected to the other side of the parasitic line resistance,
RS, the output voltage would be given by equation 9 below.
𝑉𝑜 = (𝑉𝑅𝐸𝐹 − 𝐼𝑜 𝑅𝑆 ) �1 +
𝑅2
𝑅1
�
(Equation 9)
The drop across the parasitic line resistance is multiplied by a factor greater than one. From
these two equations it can be seen that the output current affects the output voltage greater in
the regulator with the voltage divider connected after the parasitic line resistance due to the
multiplication factor. To achieve the best layout for regulator performance, attach the
feedback voltage divider directly to the output pin. Figure 4 below illustrates the optimal
ground pin connection of a fixed voltage regulator to maximize load regulation
performance.
Figure 4: Ground Pin Connection to Improve Load Regulation
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Layout
The performance of the linear regulator is not only dependent on the circuit design but also
the PCB layout design. The output capacitor should be placed as close to the output pin of
the voltage regulator package as possible. The input ceramic capacitor should be placed as
close to the input pin of the voltage regulator package as possible. The ground side of the
input and output capacitor should be physically close as well. This will reduce any stray
capacitance and inductance. The path containing the heaviest current load should have a
large conductor trace to reduce voltage drops and parasitic resistance. The load return
current path that goes back to the input should also have a large conductor trace to reduce
voltage drops. The techniques discussed in the load regulation section should be followed as
well to improve the performance of the regulator.
Conclusion
Standard regulators are typically the better choice when low dropout is not required.
Standard regulators also require less output capacitance because they are considered more
inherently stable due to their emitter output. This will further simplify the design of the
layout. LDO’s should be selected when lower dropout is required. They will require more
capacitance for stability due to their collector output. Traditional or “ultra” LDO’s will
require the most capacitance. Quasi-LDO’s will have a dropout voltage between that of a
standard regulator and a traditional LDO. Quasi-LDO’s will also require less capacitance
than traditional LDO’s but more than standard regulators for stability. In addition to
selecting the proper type of regulator for a specific application, careful component selection
and board layout must be observed to optimize performance.
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