VLSI Design – 1
Introduction to
VLSI Design Styles
Professor Yusuf Leblebici
Microelectronic Systems Laboratory (LSM)
yusuf.leblebici@epfl.ch
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Main Challenge is Complexity !
Remember the key message from our
previous lecture:
We will need efficient design approaches
and methodologies to deal with the very
high complexity of integrated systems.
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Structured Design Principles
Hierarchy:
“Divide and conquer” technique involves dividing a module into submodules and then repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable.
Regularity:
The hierarchical decomposition of a large system should result in not only
simple, but also similar blocks, as much as possible. Regularity usually
reduces the number of different modules that need to be designed and
verified, at all levels of abstraction.
Modularity: The various functional blocks which make up the larger system must have
well-defined functions and interfaces.
Locality:
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Internal details remain at the local level. The concept of locality also
ensures that connections are mostly between neighboring modules,
avoiding long-distance connections as much as possible.
Structured Design
Decomposition of a
complex design into
hierarchical, regular
components.
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Structured Design
Further
decomposition...
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Resulting in blocks
with manageable
complexity, that
can be designed
individually.
VLSI Design Styles
FPGA
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Full Custom Design
Following the partitioning, the
transistor level design of the
building block is generated
and simulated.
The example shows a 1-bit
full-adder schematic and its
SPICE simulation results.
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Full Custom Design
After the initial transistor level
schematic design is completed
and verified, work begins on the
full custom mask layouts of the
cells.
Most regular structures are built
with a relatively small number
of elementary components. The
three blocks shown above are
the only blocks required for a
typical fast adder.
Special care is given to ensure
the modularity and regularity of
the structure.
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Full Custom Design
In full-custom style, the designer has many degrees of freedom to
optimize a circuit design:
• Adjust individual transistor dimensions (channel width, channel
length, aspect ratio, etc.) to satisfy:
•DC specifications (voltage levels, switching thresholds)
•Transient specifications (delay times, rise- and fall-times)
• Freely choose the most appropriate topology (placement and routing)
for each circuit block.
• Decide for the interconnection strategy between neighboring blocks.
• Decide for the global distribution of power, ground and clock.
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Full Custom Design
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Full Custom Design
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Full Custom Design Flow
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Full Custom Design
The main objective of full custom design is to ensure fine-grained
regularity and modularity.
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Full Custom Design
A carefully crafted
full custom block
can be placed both
along the X and Y
axis to form an
interconnected
two-dimensional
array.
Example:
Data-path cells
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Full Custom SRAM Cell Design
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Mapping the Design into Layout
Manual full-custom
design can be very
challenging and
time consuming,
especially if the
low level regularity
is not well defined !
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Design Hierarchy
4-input logic gate
Flip-Flop
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Design Hierarchy
4-bit register
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Design Hierarchy
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Design Hierarchy
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Full Custom Design
Full-custom design style allows the designer to have complete control
over all aspects of the design.
Potentially achievable:
Highest possible performance (speed)
Smallest silicon area
Lowest power dissipation
However, full-custom design requires extensive experience, and the
design time can be very long !!
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VLSI Design Styles
FPGA
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HDL Design
1980’s
Hardware Description Languages (HDL) were conceived to
facilitate the information exchange between design
groups.
1990’s
The increasing computation power led to the introduction
of logic synthesizers that can translate the description in
HDL into a synthesized gate-level net-list of the design.
2000’s
Modern synthesis algorithms can optimize a digital design
and explore different alternatives to identify the design
that best meets the requirements.
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HDL Design
Modern hardware description languages allow structural
descriptions that basically determine all interconnections
between well-defined blocks:
adder: component adder port map (a,b,ci,co,s);
as well as purely behavioral descriptions like:
sum <= a + b - c;
The synthesizer is responsible for converting the
behavioral description into an optimized design.
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HDL Design
The design
problem is
divided into
blocks and
sub blocks.
A separate
description is
entered for
each block.
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HDL Design
This is the main
window of the
Synopsys HDL
compiler.
At this stage the
VHDL files have
been read into the
program.
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HDL Design
This is the cell “one-bit”
that describes a one-bit
full adder. The synthesizer
was able to map the HDL
code definition to a gate
level description.
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HDL Design
The design is
completely
synthesized and
mapped into the
target technology.
The logic gates
have one-to-one
equivalents as
standard cells
in the target
technology.
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Standard Cells
AND
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DFF
INV
XOR
Standard Cells
Each standard cell is pre-designed, with:
Same cell height for all elements in the library
Horizontal PWR and GND lines at the top and at the bottom
Fixed pin locations (inputs and outputs)
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Standard Cells
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Standard Cells
“routing”
between
the cells
completed
in the
channel
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Standard Cells
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Standard Cells
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Standard Cells
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Standard Cells
Rows of standard
cells with routing
channels between
them
Memory array
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Standard Cells
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Automatic Placement of Cells
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Automatic Routing between Cells
Close-up detail in
Silicon Ensemble:
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VLSI Design Styles
FPGA
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Mask Gate Array
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Mask Gate Array
Before customization
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Mask Gate Array
After customization
(metal lines)
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VLSI Design Styles
FPGA
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Field Programmable Gate Array
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Field Programmable Gate Array
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Field Programmable Gate Array
Internal structure of a CLB
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Field Programmable Gate Array
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