Figure 2.1 (p. 58)
Basic fabrication steps in the silicon planar
process: (a) oxide formation, (b) selective
oxide removal, (c) deposition of dopant atoms
on wafer, (d) diffusion of dopant atoms into
exposed regions of silicon.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.2 (p. 59)
Evolution of IC technology.
(a) First commercial silicon
planar transistor (1959).
(b) Diode-transistor logic
(DTL) circuit (1964).
(c) 256-bit bipolar random
access memory (RAM) circuit
(1970).
(d) VLSI central-processor
computer chip containing
450,000 transistors (1981).
The different functions carried
out by the IC are labeled on
the figure.
[(a), (b), and (c) courtesy of B.E. Deal—
Fairchild Semiconductor. (d) courtesy of
Hewlett-Packard Co.]
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.3 (cont., p. 60)
(e) Block diagram of Pentium 4 processor with 42 million transistors (2000).
[Courtesy Intel Corporation.]
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.2 (cont., p. 60)
(f) Minimum feature size versus year of first commercial production.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.2 (cont., p. 61)
(g) Another embodiment of Moore’s law shows that the number of transistors per chip has
doubled every 18-24 months for approximately 30 years.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.2 (cont., p. 61)
(h) Along with decreasing feature size, the number of electrons in each device decreases.
[(f)-(h) adapted from Mark Bohr, Intel; Howard Huff, Sematech; Joel Birnbaum, Hewlett-Packard; Motorola.]
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.3 (p. 63)
Formation of a single-crystal semiconductor ingot by the Czochralski process: (a) initiation
of the crystal by a seed held at the melt surface, (b) withdrawal of the seed “pulls” a single
crystal.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.4 (p. 65)
The float-zone process. A molten zone
passes through a polycrystalline-silicon
rod, and a single crystal grows from a
seed at the bottom end.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.5 (p. 67)
An insulating layer of silicon dioxide is grown on silicon wafers by exposing them to
oxidizing gases in a high-temperature furnace.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.6 (p. 67)
Three fluxes that characterize the oxidation rate: F(1) the flow from the gas stream to the
surface, F(2) the diffusion of oxidizing species through the already formed oxide, and F(3)
the reaction at the Si-SiO2 interface. The concentration of the oxidizing species varies in
the film from Co near the gas interface to Ci near the silicon interface.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.10 (p. 73)
The intrinsic carrier density ni in
silicon between 300 and 1200°C
[10].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figures 2.11a and 2.11b (p. 75)
(a) The areas from which the oxide is to be etched are defined by exposing a lightsensitive resist through a photographic negative (mask). (b) The hardened resist protects
the oxide in the masked areas from chemical removal.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.11c (p. 75)
(c) In a stepper-type
lithography system, exposure
light passes through features
on a mask. The image of each
feature is reduced and focused
on one die on the wafer, and all
features on the die are exposed
simultaneously. The wafer is
then moved (stepped) to the
next die position where the
exposure process is repeated.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.12 (p. 76)
(a) The illumination intensity varies gradually near the edge of a fine feature because of
diffraction. (b) The intensity between two closely spaced features does not reach zero.
Shifting the phase of the electric field by 180° by locally changing the path length through
the mask (c) allows the intensity to become zero between the features (d).
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.13a (p. 77)
(a) Cross-sectional transmission electron micrograph of a polysilicon gate approximately
180 nm across, the gate oxide under the polysilicon, and the surrounding shallow
junctions in the silicon substrate (Courtesy of Accurel Systems International Corp.)
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.13b (p. 77)
(b) Anisotropically etched lines 500 nm wide spaced 1.5 μm apart. Resist covers the
double-layer structure consisting of 180 nm TaSi2 over 260 nm of polycrystalline silicon.
Note the uniformity of the vertical surface through the various layers. (Courtesy of G.
Dorda, Siemens Corporation).
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.14 (p. 79)
(a) Isotropic wet etching or dry etching that is dominated by chemical reactions cause
significant undercut of the masking layer. (b) Anisotropic, ion-assisted, dry etching creates
a near-vertical profile, retaining the dimensions of the masking layer.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.15 (p. 80)
In ion implantation, a beam of high-energy ions strikes selected regions of the
semiconductor surface, penetrating into these exposed regions.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.18 (p. 84)
The increase in dopant concentration in a region dx is related to the net flux of atoms into
the region: F(x) – F(x + dx).
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.20 (p. 86)
Temperature dependence of the
diffusities (at low concentrations)
of commonly used dopant
impurities in silicon [12].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.22 (p. 88)
Temperature dependence of the
solid solubilities of several elements
in silicon [13].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.23 (p. 92)
(a) Scanning electron micrograph showing cross section through a bipolar transistor,
(b) sketch identifying the regions shown. The boron-doped base region has been pushed
ahead (emitter push) by the concentration-dependent diffusion effects associated with heavy
phosphorus doping in the emitter [15].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.24 (p. 93)
Section of a silicon wafer showing
deeper diffused n-type region (dark
area) under oxidized silicon
surface (bottom) than underneath
a surface protected from oxidation
(top) [16].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.25 (p. 96)
(a) Lightly doped epitaxial layer grown on heavily doped silicon substrate. (b) Singlewafer, epitaxial deposition system showing silicon wafer on support plate that is heated by
infrared lamps located outside the quartz deposition chamber.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.26 (p. 98)
LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide
and Si3N4 covering the area over which further oxidation is not desired, (b) thick oxide layer
grown over the bare silicon region, (c) stress-relief oxide and Si3N4 removed by etching to
permit device fabrication, (d) scanning electron micrograph (5000 X) showing LOCOSprocessed wafer at step (b).
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.27 (p. 99)
Trench isolation is used to form very narrow isolation regions between adjacent devices.
After the trench pattern is etched in a masking material (a), the trench is etched
directionally using a reactive ion etch process (b). A thin, high-quality oxide is formed (c),
and the trench is filled with polysilicon or with oxide [shown for oxide in (d)]. The excess
material is removed by chemical-mechanical polishing (e).
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.28 (p. 100)
(a) Section along horizontal,
open-flow reactor showing gas
flow parallel to the wafer surface
and indicating the location of the
boundary layer in which the gas
flow is nearly perpendicular to the
wafer surface, (b) representation
of gas velocity distribution across
the reaction chamber.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.31 (p. 102)
(a) Gases in a high-capacity reactor flow
through the annular space between the
wafers and reactor wall and then diffuse
between the closely spaced wafers.
(b) The basic elements of a LPCVD
reactor.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.32a (p. 103)
(a) Schematic cross section of a remote plasma-enhanced CVD reactor, in which the
plasma generation, the chemical reaction, and the ion bombardment are partially
decoupled.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.32b (p. 103)
(b) Schematic cross section of an
electron cyclotron resonance, highdensity plasma reactor.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.33 (p. 104)
A thin layer of aluminum can be used to connect various doped regions of a semiconductor
device.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.34 (p. 105)
(a) In the salicide process Ti is
deposited over the entire wafer
and annealed to form TiSi2 over
the exposed silicon. The unreacted
Ti over the oxide is then removed
by wet chemical etching.
(b) Cross-sectional transmission
electron micrograph of silicide
formed by the salicide process
over the gate, source, and drain
regions of an MOS transistor.
(Courtesy of Accurel Systems
International Corp.)
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.35 (p. 107)
Cross-sectional transmission electron micrograph of three levels of a multilevel interconnection system. Three levels of aluminum metallization and associated barrier layers are
visible, along with the tungsten-filled (black) vias between metal layers. Polysilicon lines are
visible just above the substrate. (Courtesy of Rudolph Technologies, Inc.)
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.36 (p. 107)
Cross-sectional transmission electron micrograph showing a more detailed view of
tungsten plugs connecting the underlying silicide layer and the overlying aluminum first
metallization layer. (Courtesy of Accurel Systems International Corp.)
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.37 (p. 111)
Electromigration mechanism in a
conducting stripe. Directions of electron
flux Fe, electrostatic force qξ and
resultant atomic flux FA (upper left).
Scanning electron micrograph showing
void formation to the left of the break
and accumulation of material in the form
of hillocks to the right of the break
(lower figure). The steps leading to
electromigration failure are indicated at
the upper right [18].
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.38 (p. 112)
The IC chip is mounted in a package, and wires are connected to the external leads.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.39 (p. 115)
Electrical device performance can be improved by combining two semiconductors with
different bandgaps. However, lattice mismatch and the associated strain limit the useful
heteroepitaxial combinations of materials.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.
Figure 2.45 (p. 129)
(a) An IC resistor defined by diffusing acceptors into selected regions of an n-type wafer.
The p+ regions are highly doped to assure good contact between the metal electrodes and
the p-type resistor region. (b) The dimensions of a thin region in the resistor having
conductance dG given by Equation 2.10.3.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
Copyright © 2003 John Wiley & Sons. Inc. All rights reserved.