TM
Quantum-SI
DDR2 SoDIMM
Design Kit
Signal Integrity Software, Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01764
Phone: (978) 461-0449
Fax: (978) 461-5092
www.sisoft.com
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Copyright Notice and Proprietary Information
Copyright © 2005 Signal Integrity Software, Inc. All rights reserved. No part of this copyrighted
work may be reproduced, modified or distributed in any form or by any means, without the prior
written permission of Signal Integrity Software, Inc.
Right to Copy Documentation
Signal Integrity Software, Inc. permits licensee to make copies of the documentation for its
internal use only. Each copy shall include all copyrights, trademarks, disclaimers and proprietary
rights notices.
Disclaimer
Signal Integrity Software, Inc. has made reasonable efforts to ensure that the information in this
document is accurate and complete. However, Signal Integrity Software, Inc. assumes no liability
for errors, or for any incidental, consequential, indirect, or special damages, including, without
limitation, loss of use, loss or alteration of data, delays, or lost profits or savings, arising from the
use of this document or the product which it accompanies.
Trademarks
Quantum-SI, SiAuditor, SiSoft and Core-to-Core are trademarks of Signal Integrity Software,
Inc. Other product and company names may be trademarks of their respective owners.
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1
Introduction ............................................................................................................................ 5
2
Kit Overview ............................................................................................................................ 6
2.1
Block Diagrams.............................................................................................................. 6
2.2
System Configurations (Schematic Sets) ..................................................................... 8
2.3
Net Classes (Transfer Nets)........................................................................................... 8
2.4
Libraries ....................................................................................................................... 11
2.4.1
SiSoft Parts ............................................................................................................ 11
2.4.2
IBIS Files ............................................................................................................... 11
2.4.3
Timing Models....................................................................................................... 11
2.4.4
Spice Subcircuits.................................................................................................... 11
3
4
Using the Design Kit ............................................................................................................. 12
3.1
Unzipping the Kit......................................................................................................... 12
3.2
Opening the Design Kit Interface............................................................................... 12
3.3
Opening a Schematic Set............................................................................................. 14
3.4
Reviewing Schematic Sheets ....................................................................................... 17
3.5
Setting up for Simulation ............................................................................................ 19
3.6
Running Simulations ................................................................................................... 19
3.7
Viewing Waveforms..................................................................................................... 23
3.8
Viewing Reports........................................................................................................... 32
Customizing the Design Kit .................................................................................................. 36
4.1
Transfer Net Bit Times (Data Rates) ......................................................................... 36
4.2
Solution Space .............................................................................................................. 37
4.3
Timing Models.............................................................................................................. 38
4.4
Stimulus Patterns......................................................................................................... 40
4.5
Process, Voltage and Temperature Corners (PVT).................................................. 40
4.6
Selective Schematic Sheet Simulation ........................................................................ 43
4.7
Transfer Model Overides (ODT)................................................................................ 44
4.8
Waveform processing and Slew Rate Derating......................................................... 44
4.9
Replacing the DDR2 Controller Models .................................................................... 46
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Table of Figures
Figure 1: One Slot Block Diagram_________________________________________________ 6
Figure 2: Two Slot Block Diagram_________________________________________________ 6
Figure 3: Extracted Directory Structure ___________________________________________ 12
Figure 4: Opening One Slot Project Interface _______________________________________ 13
Figure 6: Opening Two Slot Project Interface _______________________________________ 13
Figure 7: Schematic Set A of one slot system ________________________________________ 14
Figure 8: Schematic Set AA of two slot system_______________________________________ 15
Figure 9: Opening One Slot Schematic Set _________________________________________ 16
Figure 10: Opening Two Slot Schematic Set ________________________________________ 16
Figure 11: Quantum-SI Pre-Layout Tab, Schematic Set A, Sheet addcmd_8L ______________ 18
Figure 12: Pre-Layout Simulation Dialog __________________________________________ 20
Figure 13: Running Simulation and Analysis________________________________________ 21
Figure 14: Automatic Display of Result Spreadsheet and Waveforms_____________________ 22
Figure 15: Viewing Waveforms and Reports ________________________________________ 23
Figure 16: SiViewer Open Waveform Files Dialog ___________________________________ 24
Figure 17: Opening Waveform Files ______________________________________________ 25
Figure 18: dq_2R/dqs_2R Read/Write Waveforms with Data Rates ______________________ 26
Figure 19: Adding waveforms From Filtered Files ___________________________________ 27
Figure 20: Switching Between Eye Diagram and Overlay /Shift and remove from aperture ___ 28
Figure 21: Accessing Display Preferences (General Tab)______________________________ 29
Figure 22: Thresholds Tab of Display Preferences ___________________________________ 30
Figure 23: Aperture Tab of Display Preferences _____________________________________ 30
Figure 24: Mask Tab of Display Preferences________________________________________ 31
Figure 25: Viewing Waveform & Timing Report _____________________________________ 32
Figure 26: Waveform Summary Tab ______________________________________________ 33
Figure 27: Eye Rollups Tab _____________________________________________________ 34
Figure 28: Timing Tab _________________________________________________________ 34
Figure 29: Timing by Transfers Tab_______________________________________________ 35
Figure 30: Source Synchronous Details Tab ________________________________________ 35
Figure 31: Clock Domain File ___________________________________________________ 36
Figure 32: Solution Space Panel _________________________________________________ 37
Figure 33: addcmd timing (1T) __________________________________________________ 38
Figure 34: ctrl timing __________________________________________________________ 38
Figure 35: dq/dm write timing ___________________________________________________ 38
Figure 36: dq read timing_______________________________________________________ 39
Figure 37: dqs write timing _____________________________________________________ 39
Figure 38: Sheet Simulation Corner Selection _______________________________________ 41
Figure 39: Schematic Set Simulation Corner Selection ________________________________ 41
Figure 40: Default Corner Conditions _____________________________________________ 42
Figure 41: Selective Schematic Sheet Simulation_____________________________________ 43
Figure 42: Viewing and Customizing Transfer Model Overrides ________________________ 44
Figure 43: Quantum-SI Waveform Processing Levels _________________________________ 45
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1 Introduction
SiSoft’s Quantum-SI DDR2 SoDIMM kit provides a preconfigured pre-layout analysis
environment consisting of parameterized topologies, net classes (Transfer nets), SiSoft parts, IBIS
models of Micron Technology, Inc. ("Micron")DDR2 SDRAM and a generic memory controller,
and Micron memory timing models for each one slot and two slot SoDIMM configuration
utilizing JEDEC raw cards A, B, C and D.
The kit is ready-to-use and designed to be easily reconfigured to meet your specific requirements.
It allows signal integrity, timing and crosstalk analysis to be quickly performed over process,
voltage and temperature conditions for a wide range of parametric variations. In addition, on die
termination (ODT) and slew rate derating are performed automatically and all DDR2 waveform
processing levels are supported.
This document provides a kit overview, including block diagrams, system configurations, net
classes and libraries, along with step-by-step instructions on how to use and customize the kit for
your specific implementation.
Note: Unless you are running Windows and have opened the DDR2 SoDIMM kit from the
startup dialog or the File | Kits menu item, you will need to unzip the DDR2 SoDIMM
kit to a writable location prior to performing the steps outlined in this document. The
DDR2 SoDIMM kit project and interfaces are included in the product installation
directory as well as in the compressed file design_kits.zip (on Windows) or
design_kits.tar (on Unix). These files are located in the
<install path>/share directory.
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2 Kit Overview
2.1 Block Diagrams
The block diagrams shown in Figure 1 and Figure 2 below reflect the connectivity captured in the
kit for a one slot and two slot SoDIMM system, respectively. Each system is comprised of
multiple configurations, where a configuration is a unique SoDIMM population.
SoDIMM
JEDEC Raw Card
A, B, C or D
DDR2
Memory
Controller
addcmd
22
ctrl
6
dm
8
dq
64
dqs
8
ck
2
Figure 1: One Slot Block Diagram
DDR2
Memory
Controller
addcmd
22
ctrl_slot1
6
ctrl_slot2
6
dm
8
dq
64
dqs
8
ck_slot1
2
ck_slot2
2
Slot 1 SoDIMM
Slot 2 SoDIMM
JEDEC Raw Card
A, B, C, D or Empty
JEDEC Raw Card
A, B, C or D
Figure 2: Two Slot Block Diagram
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There are four JEDEC Raw Card SoDIMM module designs in the DDR2 Design Kit. They are
Raw Cards A, B, C and D. They differ in the number and width of the DDR2 SDRAM
components and number of ranks, as shown in Table 1. Table 2 shows Micron part numbers for
DDR2 SODIMM modules as they relate to the various JEDEC Raw Card configurations. More
information on Micron DDR2 SODIMM modules can be found at the following url:
http://www.micron.com/products/modules/ddr2sdram/partlist.aspx?pincount=200pin&version=Unbuffered&package=SODIMM.
DDR2 SoDIMM Module
Raw Card A
Raw Card B
Raw Card C
Raw Card D
SDRAM
Width
x16
x8
x16
x8 (stacked)
#
SDRAMs # Ranks
8
2
8
1
4
1
16
2
Table 1: JEDEC SoDIMM Raw Cards
JEDEC Raw Card
RCA
RCA
RCA
RCA
RCA
RCA
RCA
RCA
RCB
RCB
RCB
RCC
RCC
RCC
RCC
RCC
RCC
RCD/E*
Micron Part Number
MT8HTF3264HDY-40E
MT8HTF3264HDY-53E
MT8HTF3264HDY-667
MT8HTF6464HDY-40E
MT8HTF6464HDY-53E
MT8HTF6464HDY-667
MT8HTF12864HDY-40E
MT8HTF12864HDY-53E
MT8HTF3264HY-40E
MT8HTF3264HY-53E
MT8HTF6464HY-667
MT4HTF1664HY-40E
MT4HTF1664HY-53E
MT4HTF1664HY-667
MT4HTF3264HY-40E
MT4HTF3264HY-53E
MT4HTF3264HY-667
MT16HTF12864HY-667
Density
256MB
256MB
256MB
512MB
512MB
512MB
1GB
1GB
256MB
256MB
512MB
128MB
128MB
128MB
256MB
256MB
256MB
1GB
Speed
PC2-3200
PC2-4200
PC2-5300
PC2-3200
PC2-4200
PC2-5300
PC2-3200
PC2-4200
PC2-3200
PC2-4200
PC2-5300
PC2-3200
PC2-4200
PC2-5300
PC2-3200
PC2-4200
PC2-5300
PC2-5300
Data Rate
400 MT/s
533 MT/s
667 MT/s
400 MT/s
533 MT/s
667 MT/s
400 MT/s
533 MT/s
400 MT/s
533 MT/s
667 MT/s
400 MT/s
533 MT/s
667 MT/s
400 MT/s
533 MT/s
667 MT/s
667 MT/s
Table 2: JEDEC Raw Card to Micron Part Number Decoder
* Note: Raw Card E is the planar version of Raw Card D which has stacked SDRAM
components.
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2.2 System Configurations (Schematic Sets)
The Quantum-SI DDR2 kit implements each system configuration as a Schematic Set. Table 33
and Table 4 below show the Schematic Sets included in the kit for both one slot and two slot
systems. Each Schematic Set contains the appropriate net classes and respective topologies preconfigured for simulation.
Schematic Set
A
B
C
D
Slot 1 Module
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Slot 2 Module
N/A
N/A
N/A
N/A
Table 3: One-Slot Schematic Sets
Schematic Set
AA
AB
AC
AD
BA
BB
BC
BD
CA
CB
CC
CD
DA
DB
DC
DD
XA
XB
XC
XD
Slot 1 Module
Raw Card A
Raw Card A
Raw Card A
Raw Card A
Raw Card B
Raw Card B
Raw Card B
Raw Card B
Raw Card C
Raw Card C
Raw Card C
Raw Card C
Raw Card D
Raw Card D
Raw Card D
Raw Card D
Empty
Empty
Empty
Empty
Slot 2 Module
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Raw Card A
Raw Card B
Raw Card C
Raw Card D
Table 4: Two-Slot Schematic Sets
2.3 Net Classes (Transfer Nets)
Quantum-SI implements net classes as Transfer Nets. A Transfer Net is similar in concept to a
net class, but it is a reusable data structure that includes additional properties used during
simulation, including valid transfers, data rate, on-die termination configurations and probe
points.
The Transfer Nets in the DDR2 Design Kit are listed in Table 55 and Table 6 (below) with the
Schematic Sets in which they are included for one-slot and two-slot systems, respectively. The
transfer net names contain the number of loads/ranks contained in each slot. For two slot systems,
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there are independent transfer nets for ck and ctrl for slot 1 and slot 2 to properly calculate
timing margins and account for delay variations between slots on the respective transfer nets.
A Transfer Net is captured in a “schematic sheet”. Note: only one Transfer Net may be captured
per schematic sheet. However, a Transfer Net may contain multiple signals, as long as they
belong to the same Transfer Net (e.g., an address bus or a data bus). Further, a Transfer Net may
be used to represent multiple instances of the same type of bus (e.g., data_bus_A[63:0] and
data_bus_B[63:0]).
Transfer Net
(Also known as a Schematic Sheet)
addcmd_16L
addcmd_4L
addcmd_8L
ck_2L
ck_4L
ck_8L
ctrl_4L
ctrl_8L
dm_1R
dm_2R
dq_1R
dq_2R
dqs_1R
dqs_2R
Schematic Sets
D
C
A, B
C
A, B
B, D
A, C
B, D
B, C
A, D
B, C
A, D
B, C
A, D
Table 5: One-Slot System Transfer Nets
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Transfer Net
(Also known as a Schematic Sheet)
addcmd_0L_16L
addcmd_0L_4L
addcmd_0L_8L
addcmd_16L_16L
addcmd_16L_4L
addcmd_16L_8L
addcmd_4L_16L
addcmd_4L_4L
addcmd_4L_8L
addcmd_8L_16L
addcmd_8L_4L
addcmd_8L_8L
ck_2L_slot1
ck_2L_slot2
ck_4L_slot1
ck_4L_slot2
ck_8L_slot1
ck_8L_slot2
ctrl_4L_slot1
ctrl_4L_slot2
ctrl_8L_slot1
ctrl_8L_slot2
dm_0R_1R
dm_0R_2R
dm_1R_1R
dm_1R_2R
dm_2R_1R
dm_2R_2R
dq_0R_1R
dq_0R_2R
dq_1R_1R
dq_1R_2R
dq_2R_1R
dq_2R_2R
dqs_0R_1R
dqs_0R_2R
dqs_1R_1R
dqs_1R_2R
dqs_2R_1R
dqs_2R_2R
Schematic Sets
XD
XC
XA, XB
DD
DC
DA, DB
CD
CC
CA, CB
AD, BD
AC, BC
AA, AB, BA, BB
CA, CB, CC, CD
AC, BC, CC, DC, XC
AA, AB, AC, AD, BA, BB, BC, BD
AA, AB, BA, BB, CA, CB, DA, DB, XA, XB
DA. DB, DC, DD
AD, BD, CD, DD, XD
AA, AB, AC, AD, CA, CB, CC, CD
AA, AC, BA, BC, CA, CC, DA, DC, XA, XC
BA, BB, BC, BD, DA, DB, DC, DD
AB, AD, BB, BD, CB, CD, DB, DD, XB, XD
XB, XC
XA, XD
BB, BC, CB, CC
BA, BD, CA, CD
AB, AC, DB, DC
AA, AD, DA, DD
XB, XC
XA, XD
BB, BC, CB, CC
BA, BD, CA, CD
AB, AC, DB, DC
AA, AD, DA, DD
XB, XC
XA, XD
BB, BC, CB, CC
BA, BD, CA, CD
AB, AC, DB, DC
AA, AD, DA, DD
Table 6: Two-Slot System Transfer Nets
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2.4 Libraries
This kit consists of library elements for SiSoft parts, of Micron DDR2 SDRAM and a generic
memory controller, and Micron memory timing models and spice subcircuits. These library
elements are described in the following subsections.
2.4.1 SiSoft Parts
A SiSoft Part is the central Quantum-SI library element and serves to map an IBIS Component to
a timing model. It can also contain CAD part numbers for mapping post-layout components to
their models. SiSoft Parts can be viewed/edited using the Libraries | Edit Part Properties menu
item. The SiSoft parts contained in the design kit are shown in Table 7 along with their associated
IBIS and timing models.
SiSoft Part
ddr2_controller
ddr2_sdram
IBIS Model
ddr2_controller.ibs
ddr2_sdram.ibs
IBIS Component
ddr2_controller
ddr2_sdram
Timing Model
ddr2_controller.tmg
ddr2_sdram.tmg
Table 7: SiSoft Parts
2.4.2 IBIS Files
IBIS Files are located in the directory si_lib/ibis under the project. They can be edited
using the Libraries | Edit IBIS Models menu item. Table 88 shows the IBIS files that are
referenced from the SiSoft Parts in this kit. To learn more about IBIS, you may visit
http://www.eigroup.org/ibis.
IBIS File
ddr2_controller.ibs
ddr2_sdram.ibs
Description
Generic DDR2 Memory Controller
DDR2 SDRAM developed from Micron Spice
Models
Table 8: IBIS Files
2.4.3 Timing Models
Timing models contain the output timing delays and setup/hold constraints for the design
components. Table 99 shows the timing files that are used in this kit.
Timing Model File
ddr2_controller.tmg
ddr2_sdram.tmg
Timing Model
ddr2_controller
ddr2_sdram
Description
DDR2 Memory Controller
x4 Micron DDR2 SDRAM Component
Table 9: Timing Models
2.4.4 Spice Subcircuits
Item
Connector
File Name
dimm_connector.mod
Subcircuit Name
dimm_connector
Table 10: Spice Subcircuits
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3 Using the Design Kit
3.1 Unzipping the Kit
If you are running on Windows and have opened the DDR2 SoDIMM kit from the startup dialog
or the File | Kits menu item, you do not have to perform this step. Otherwise, you will need to
unzip the DDR2 SoDIMM kit zip archive to a writable location prior to performing the steps
outlined in this document. The DDR2 SoDIMM kit project and interfaces are included in the
product installation directory as well as in the compressed file design_kits.zip (on
Windows) or design_kits.tar (on Unix). These files are located in the
<install path>/share directory.
The extracted design kit directory structure should look similar to that shown in Figure 3 below.
Figure 3: Extracted Directory Structure
3.2 Opening the Design Kit Interface
Start the Quantum-SI application and then click the File | Project | Open Project Interface
menu item to open a file browser window.
For a one-slot system (see Figure 1 for block diagram):
1. Browse to the location where you unzipped the kit and then navigate to the
DDR2_Kit/interfaces/ddr2_1slot directory.
To open the interface, double click on ddr2_1slot.edk (Figure 4: Opening One Slot Project
Interface
2. ).
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Figure 4: Opening One Slot Project Interface
For a two-slot system (see Figure 2 for block diagram):
1. Browse to the location where you unzipped the kit and then navigate to the
DDR2_Kit/interfaces/ddr2_2slot directory.
2. To open the interface, double click on ddr2_2slot.edk (Figure 5).
Figure 5: Opening Two Slot Project Interface
Once you have selected an interface, you are ready to open the desired Schematic Set.
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3.3 Opening a Schematic Set
As discussed in Section 2.2, the DDR2 kit implements each system configuration (slot raw card
population) as a Schematic Set.
For example, a one slot system populated with Raw Card A is implemented in Schematic Set A
in the one slot interface shown below in Figure 6.
Current Schematic Set
Figure 6: Schematic Set A of one slot system
The complete list of one slot Schematic Sets is shown in Table 3 above.
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A two slot system populated with Raw Card A in slot 1 and Raw Card A in slot 2 is implemented
in Schematic Set AA in the two slot interface shown in Figure 7 below.
Current Schematic Set
Figure 7: Schematic Set AA of two slot system
The complete list of two slot Schematic Sets is shown in Table above.
After opening either the one or two slot interface, you are ready to select the Schematic Set that is
associated with the desired configuration.
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To open a slot one Schematic Set from the Quantum-SI application:
1. Click the File | Schematic Set | Open Schematic Set menu item.
This command will display the Open Schematic Set browser window (shown in Figure 8).
Figure 8: Opening One Slot Schematic Set
To open a slot two Schematic Set from the Quantum-SI application:
1. Click the File | Schematic Set | Open Schematic Set menu item.
This command will display the Open Schematic Set browser window (shown in Figure 9).
Figure 9: Opening Two Slot Schematic Set
Once you have opened the desired Schematic Set, you are ready to review the schematic sheets,
perform simulation setup or simulate the selected Schematic Set.
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3.4 Reviewing Schematic Sheets
In a Schematic Set, there is one schematic sheet for each net class shown in the respective block
diagrams (e.g., addcmd, ctrl, etc. in Figure 1 and ctrl_slot1, ctrl_slot2, etc. in
Figure 2).
For one slot and two slot systems with only one slot populated, there will be six transfer nets:
1.
2.
3.
4.
5.
6.
addcmd
ctrl
ck
dq
dm
dqs
For two slot systems with both slots populated, there will be eight transfer nets:
1.
2.
3.
4.
5.
6.
7.
8.
addcmd
ctrl_slot1
ctrl_slot2
ck_slot1
ck_slot2
dq
dm
dqs
Note: It is necessary to have independent ck and ctrl transfer nets for slot1 and slot2 in
two slot systems to properly account for delay variations between slots when performing
static timing margin analysis.
Note: The schematic sheet/transfer net names also contain the number of loads/ranks
contained in each slot as is discussed in Section 2.3.
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Figure 10 below shows the Pre-Layout tab of the Quantum-SI application for Schematic Set A of
the one slot interface.
Sheet Simulation Control
Schematic Topology
Element Properties
Schematic Sheet Selection
Solution Space
Schematic Set
Figure 10: Quantum-SI Pre-Layout Tab, Schematic Set A, Sheet addcmd_8L
The figure highlights the Sheet Simulation Control panel, Element Properties panel, Schematic
Topology panel, Solution Space panel and the current Schematic The addcmd_8L sheet is
selected. The other sheets in this Schematic Set may be viewed by selecting the corresponding tab
at the bottom of the Schematic Topology panel (ck_4L, ctrl_4L, dm_2R, dq_2R and
dqs_2R).
The Sheet Simulation Control panel contains data stored in the current sheet simulation state
that affects the simulation including data rate, simulation corners, topology and AC noise.
The Element Properties panel contains one entry for every element in the schematic topology.
This panel is used to parameterize elements for solution space analysis. By default, the
motherboard etch length and termination have been parameterized in the kit.
The Solution Space panel contains the solution space for parameterized elements and global
variables. The solution values can be altered prior to simulation as is discussed in the Section 4.2.
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3.5 Setting up for Simulation
The kit is setup and ready for simulation. However, you may customize the kit in many ways as
discussed in Section 4.
Tip: Prior to customizing the kit, you should familiarize yourself with the pre-configured kit
contents, perform simulations and view waveforms/reports.
Note: A detailed description on how to setup pre-layout analysis may be found in the Product
User Guide.
3.6 Running Simulations
Once you have loaded the desired interface and associated Schematic Set you are ready to
simulate the design.
Quantum-SI’s simulation flow consists of six steps:
1. Validation - The validation process ensures that the data environment is as complete as
possible and is self-consistent.
a. Validation checks for the presence of the Transfer Nets, parts, IBIS files, timing
files, Spice subcircuits, clock domains, clock skew data, common project file
(.cpf) and interface file (.edk).
b. Validation also crosschecks the data among these files for completeness and
consistency.
Note: This step helps eliminate errors early in the analysis process prior to simulation,
waveform analysis and timing analysis.
2. Generate Spice Decks - This process prepares simulation data by generating Spice
netlists for the defined solution space.
Note: The Spice decks that are generated will either be for Quantum-SI’s internal
IsSpice4 simulator or HSPICE™.
3. Run Spice – This process submits spice decks to the simulation engine, either locally or
remotely to a compute farm (depending on your setup). It also manages the simulations
as they run.
4. Analyze Waveforms - The process analyzes every edge of every simulation for
waveform quality, interconnect delay and eye-diagram characteristics using threshold and
DRC data defined in the IBIS models. It also utilizes the defined AC noise levels as part
of the analysis process.
5. Analyze Timing – This process performs full static timing verification using extracted
interconnect delays, clock skew, derating and AC timing specifications from the timing
models to determine setup and hold margins.
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6. Display Results Spreadsheet - This process displays the waveform and timing analysis
results in the spreadsheet tool defined in your user preferences (defaults to Excel on
Windows).
7. Display Waveforms - This process displays the waveforms for the currently selected
sheet in SiSoft’s SiViewer application.
The Pre-Layout Simulation dialog is accessed from the Run | Simulate Selected menu item or
from the toolbar as is shown in Figure 11.
Run Simulations
Select Simulation Steps
Display Waveforms for Selected Sheet
Figure 11: Pre-Layout Simulation Dialog
Once the dialog is opened, you may select any of the available steps for simulation.
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To simulate:
1. Click the Run button as shown in Figure 12.
Note: This will begin running the selected steps and launch the queue monitor after the
simulation process is initiated.
Click Run After Selecting Steps
Figure 12: Running Simulation and Analysis
Upon completion of the simulation steps shown in Figure 12 (i.e., all steps checked), a
spreadsheet and SiViewer application are displayed. Once you have completed running
simulations and analysis, you are ready to review waveforms and analysis results.
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The spreadsheet application contains the waveform/timing analysis results and the SiViewer
application is pre-loaded with waveforms for the selected sheet as shown in Figure 13 below.
Autoload of Waveforms & Reports
Figure 13: Automatic Display of Result Spreadsheet and Waveforms
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3.7 Viewing Waveforms
SiViewer is SiSoft’s waveform display tool. SiViewer may be automatically launched from the
simulate dialog by selecting Display Waveforms. It can also be accessed from the
SimData | Waveforms menu item or from the toolbar as shown in Figure 14.
Note: When SiViewer is launched from the simulate dialog, the waveform files in the selected
sheet will be automatically loaded.
Viewing Waveforms & Reports
Figure 14: Viewing Waveforms and Reports
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To open waveform files:
1. Click the Open File toolbar button and browse to the desired waveform files (.csd
files for Quantum-SI’s IsSpice4 simulator or .tr0 files for HSPICE) as shown in Figure
15 below.
Figure 15: SiViewer Open Waveform Files Dialog
Pre-layout waveforms are stored in the following directory relative to the project directory:
interfaces/<interface_dir>/pre_sims/<sheet_name>/<state>.ssm/sims
Where
<interface_dir> is the interface name ddr2_1slot or ddr2_2slot
<sheet_name> is based on the Schematic Set as shown in Table 5 or Table
<state> is the schematic sheet state, which in this kit is always the Schematic Set name
As an example, the schematic sheet simulations for Schematic Set A in the one slot interface are
stored in the following directories relative to the project directory:
dq_2R - interfaces\ddr2_1slot\pre_sims\dq_2R\A.ssm\sims
dqs_2R - interfaces\ddr2_1slot\pre_sims\dqs_2R\A.ssm\sims
dm_2R - interfaces\ddr2_1slot\pre_sims\dm_2R\A.ssm\sims
ck_4L - interfaces\ddr2_1slot\pre_sims\ck_4L\A.ssm\sims
addcmd_8L - interfaces\ddr2_1slot\pre_sims\addcmd_8L\A.ssm\sims
ctrl_4L -
interfaces\ddr2_1slot\pre_sims\ctrl_4L\A.ssm\sims
A common operation is to display the dqs and dq waveform with associated dq aperture and
threshold levels.
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Perform the following steps to display typical simulation waveforms for Schematic Set A in
the one slot interface:
1. Select the dq_2R sheet tab.
2. Launch SiViewer (Figure 14).
3. Click the Open Files tool bar button (Figure 16).
4. Select all files and click Open (Figure 16).
Note: As shown in Figure 16, you can select whether to hide standard load simulations and to
enable selection of multiple simulations when adding waveforms to the display.
Enable Selection of Multiple Sims
Show Standard Load Sims
Figure 16: Opening Waveform Files
5. Click the Open Files tool bar button (Figure 16).
6. Browse to the dqs_2R simulations.
Note: The dqs_2R simulation results are located in the project directory
named:
interfaces\ddr2_1slot\pre_sims\dqs_2R\A.ssm\sims
7. Select all files and click Open (Figure 16).
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8. Uncheck the View Std Load checkbox (standard load sims are now hidden).
Note: SiViewer should now looks similar to Figure 17 where the typical (ttte)
simulation files are shown loaded for both dq_2R and dqs_2R.
Standard Load Waveforms Hidden
Simulation Data rates
dq and dqs read/write waveforms
Figure 17: dq_2R/dqs_2R Read/Write Waveforms with Data Rates
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9. Use the Filename Wildcard Filter to select only “write” operations by clicking
the Wildcard is Off button and typing:
*controller in the wildcard text box as shown in Figure 18.
Show Thresholds on Selected Waveforms
1.
Select Simulation File(s)
2.
Select Node
3.
Click Add or Add Group
to Display
Simulation File Filter
Figure 18: Adding waveforms From Filtered Files
Note: Simulation names contain the driving designator as part of the name.
10. Select the dq_2R waveform file and the node V(ddr2_sdram_1_pad) from
the node table and click the Add or Add Group button (Figure 18).
11. Repeat the previous operation for dqs_2R with node:
V(ddr2_sdram_1_c_pad)
Note: Both dq and dqs waveforms as sdram1 should now be shown in the
viewer. You can select the waveform nodes after they are displayed in order to
show thresholds as is shown in Figure 18.
Note: The kit is set up for read/write operations to only one SDRAM on a two
rank DIMM module to minimize disk space requirements and increase
performance, since the results would be nearly identical. As a result, probing the
sdram_2 nodes in the simulations will not show thresholds, measurement data or
apertures.
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12. Once the waveforms are displayed, you may toggle between the overlay and eye
diagram mode as shown in Figure 19 below.
Toggle between Overlay and
Eye Diagram Mode
Shift Strobe and Exclude From Aperture
Figure 19: Switching Between Eye Diagram and Overlay /Shift and remove from aperture
Note: When in eye diagram mode you will see an aperture if it has been enabled
from the Display Preferences Dialog.
13. You can shift the dqs waveform to the middle of the dq eye (half of a bit time =
1.25nS by default) and remove it from the aperture as shown in Figure 19 above.
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14. You can customize numerous display preferences settings by clicking the
Display | Display Preferences menu item (Figure 20).
Figure 20: Accessing Display Preferences (General Tab)
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In addition, Figure 20 through Figure 23 show the General, Thresholds, Aperture and Mask tabs
of the display preference dialog. A detailed description on how to customize display preferences
and use SiViewer is contained in the Product User Guide.
Figure 21: Thresholds Tab of Display Preferences
Figure 22: Aperture Tab of Display Preferences
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Figure 23: Mask Tab of Display Preferences
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3.8 Viewing Reports
In addition to viewing waveforms, you may view the detailed results in industry standard
spreadsheet format. The Waveform and Timing Report contains multiple tabs indicating
waveform quality, eye diagram and timing margins. This report may be accessed from the
Reports | Waveform & Timing Report menu item, the tool bar or from the simulate dialog as
shown in Figure 24.
Viewing Waveforms & Reports
Figure 24: Viewing Waveform & Timing Report
Quantum-SI provides a tiered result viewing approach called progressive discovery, which allows
you to drill-down from high-level summaries of waveform quality, eye diagram and timing
information to low-level detailed reports.
Note: Some tabs, such as Waveform Overshoot and Waveform Quality are only present when
there is valid data to display. If no waveform quality issues were flagged during the analysis,
these tabs are not included in the spreadsheet. Please see Viewing the Waveform and Timing
Analysis Report section in the Product User’s Guide for more detailed information.
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Some tabs of interest include the following:
Waveform Summary
Eye Rollups
Timing
by Transfers
by Variation Details
Source Synchronous Details.
Screen shots of these tabs are shown below for reference.
Figure 25: Waveform Summary Tab
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Figure 26: Eye Rollups Tab
Figure 27: Timing Tab
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Figure 28: Timing by Transfers Tab
Figure 29: Source Synchronous Details Tab
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4 Customizing the Design Kit
The following subsections describe ways to customize the kit to meet your needs.
4.1 Transfer Net Bit Times (Data Rates)
The bit times for each net class are defined in terms of the clock period, where 1T is equal to the
period of ck. The clock period is set in the clock domain file, which can be accessed from the
Setup | Clock Domain menu item shown in Figure 30.
Clock Domain File
Figure 30: Clock Domain File
The clock period is set by the parameter ddr2_ck_rate in the Clock Domain file. The values
that correspond to the DDR2 speeds are shown in Table 21.
Speed
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Clock (ck) Period (T)
5.0ns
3.75ns
3.0ns
2.5ns
Clock (ck) Frequency
200MHz
266MHz
333MHz
400MHz
Table 21: Clock Periods
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The bit times for the Transfer Nets are shown in Table 32 By default, the addcmd bit time is set
to 1T for one slot systems and 2T for two slot systems. If you desire to change this, you must set
the clock domain variable addcmd1t2t to 1 or 2.
Net Class
dq/dm/dqs
addcmd
Ctrl
Ck
Bit
Time/Pulse
Width
0.5T
1T or 2T
1T
0.5T
Table 32: Bit Times for Net Classes
4.2 Solution Space
It is common to modify the solution space defined in the kit based on actual motherboard etch
lengths, topology and termination. By default, motherboard etch lengths and termination have
been parameterized and set up for solution space analysis. These parameterized elements have
been set to global solution space variables that are shared amongst all the Schematic Sets (see
Figure 31). This eliminates the need to redundantly re-enter solution space data for each system
configuration.
Note: MBL (mother board length) and MBT (motherboard termination) variation groups have
been utilized to control the combinations of variable values that are used during simulation. In
many cases, the different lengths are related (e.g. all sum up to the same value), so to run with no
variation group may lead to invalid cases in your solution space.
Global Variables
Parameterized Elements
Solution Space Values
Figure 31: Solution Space Panel
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4.3 Timing Models
The kit contains two timing models, one for the DDR2 controller (ddr2_controller.tmg)
and one for the Micron DDR2 SDRAM (ddr2_sdram.tmg). These timing models consist of
parameterized delays and timing constraints for the source-synchronous transactions occurring on
the interface. The timing models are frequency agile, and as such, the timing characteristics will
change based on the operating data rates of the interface.
Figure 32 thru Figure 36 below show the timing diagrams and associated timing model
parameters used during Quantum-SI’s static timing analysis for addcmd, ctrl, dq/dm
write, dq read and dqs write transactions respectively.
Figure 32: addcmd timing (1T)
Figure 33: ctrl timing
Figure 34: dq/dm write timing
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Figure 35: dq read timing
Figure 36: dqs write timing
The controller timing parameters that may be modified to match specific controller timing
characteristics are shown in Table 43, along with their associated descriptions. All of these
parameters are frequency agile and as such, will vary as a function of the ddr2_ck_period or
addcmd1t2t clock domain variables (section 4.1).
Controller Timing Parameter
Description
ADDCMD_SKEW_MIN
ADDCMD_SKEW_MAX
CTRL_SKEW_MIN
CTRL_SKEW_MAX
DQ_SKEW_MIN
DQ_SKEW_MAX
DQS_SKEW_MIN
DQS_SKEW_MAX
DQ_SETUP
DQ_HOLD
ADDCMD_PRELAUNCH
Minimum output delay of addcmd relative to ck
Maximum output delay of addcmd relative to ck
Minimum output delay of ctrl relative to ck
Maximum output delay of ctrl relative to ck
Minimum output delay of dq/dm relative to dqs
Maximum output delay of dq/dm relative to dqs
Minimum output delay of dqs relative to ck
Maximum output delay of dqs relative to ck
DQ setup time requirement relative dqs
DQ hold time requirement relative dqs
Programmable pre-launch of addcmd relative
to ck. Used in ADDCMD_SKEW_MIN/MAX
Programmable pre-launch of ctrl relative to ck.
Used in CTRL_SKEW_MIN/MAX
Programmable pre-launch of dq/dm relative to
dqs. Used in CTRL_SKEW_MIN/MAX
Internal Controller DQS Delay for dq read
operations
CTRL_PRELAUNCH
DQ_PRELAUNCH
CONTROLLER_READ_DQS_DELAY
Frequency
Agile
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 43: Controller Timing Parameters
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The timing models can be accessed from the Libraries | Edit Timing Models menu item. A
detailed reference to the timing model file format is contained in the Product Reference Manual.
Caution: SiSoft recommends that you don’t change the DDR2 SDRAM timing models.
4.4 Stimulus Patterns
The DDR2 kit is setup to use a default 34 bit stimulus pattern for each net class as shown in Table
54 below.
Net Class
dq/dm/addcmd/ctrl
dqs
ck
Stimulus Pattern
0000010110010001111101001101110000
0101010101010101010101010101010101
0101010101010101010101010101010101
Table 54: Stimulus patterns for Net Classes
The stimulus pattern can be customized on a net class basis from the Setup Stimulus menu item.
A detailed description on how to customize stimulus files is contained in the Product User Guide.
4.5 Process, Voltage and Temperature Corners (PVT)
You can customize the etch and process corner combinations that are simulated on a
sheet-by-sheet basis.
Note: For process, you can select FF, TT and SS (fast, typical and slow silicon/temperature
corners) in combination with SE, TE and FE (fast, typical and slow etch corners). You may
perform this selection on a sheet-by-sheet basis as is shown in Figure 37. You can also customize
the simulation corners for all sheets in the Schematic Set simultaneously from the Schematic Set
simulation corner dialog shown in Figure 38.
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Customize Sheet
Simulation Corners
Figure 37: Sheet Simulation Corner Selection
Customize Schematic Set
Simulation Corners
Figure 38: Schematic Set Simulation Corner Selection
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Figure 39 shows the default process, voltage and temperature corner conditions for fast, typical
and slow simulations. The corner conditions can be customized from the Setup | Corner
Conditions menu item.
Figure 39: Default Corner Conditions
A detailed description on how to customize corner conditions is contained in the Product User
Guide.
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4.6 Selective Schematic Sheet Simulation
By default, all schematic sheets within one of the kit Schematic Sets are included in simulation.
You can easily include or exclude sheets for simulation on a sheet-by-sheet basis from the Sheet
Simulation Control Panel or from the Schematic Set Simulation Control dialog for all sheets
simultaneously (Figure 40).
Selective Sheet
Simulation
Figure 40: Selective Schematic Sheet Simulation
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4.7 Transfer Model Overides (ODT)
The dq,dm and dqs transfer nets in the kit come with pre-configured on-die termination (ODT).
The other transfer nets also change their driver model based on loading configuration.
You can view and modify the ODT settings on a specific transfer net from the transfer net
properties dialog. This is done from the dialog by selecting the transfer net of interest, then
selecting the transfer of interest.
Note: The transfer model overrides are shown in the lower right corner of the dialog next to the
selected transfer for each designator in the transfer net. These can be modified from the pulldown list box if desired (Figure 41).
1.
Launch Transfer Net Properties Dialog
2.
Select Transfer Net
3.
Select Transfer
4.
View and Customize Transfer Model Overrides
Figure 41: Viewing and Customizing Transfer Model Overrides
4.8 Waveform processing and Slew Rate Derating
This kit supports all DDR2 waveform thresholds, quality checks and slew rate derating for dq,
dm, dqs, addcmd, ctrl and ck net classes. During an analysis, every edge of every
simulation is processed according to these rules. The waveform processing thresholds span those
shown in Figure 42 below, but include additional levels for slew rate calculation, slew rate
derating and other quality checks such as overshoot area.
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Figure 42: Quantum-SI Waveform Processing Levels
The DDR2 waveform processing parameters and quality requirements vary based on bit time and
are implemented as frequency agile parameters similar to those in timing models. These
parameters are defined in independent files in the si_lib/ibis directory and are included
directly from the IBIS files for the SDRAM (ddr2_sdram.ibs) and the controller
(ddr2_controller.ibs). These include files are unique for each transfer net as shown in
Table 65 below.
Net Class
Waveform
Processing File
Dq_dm_sstl_18.inc
dqs_sstl_18.inc
Add_ctrl_sstl_18.inc
Add_ctrl_sstl_18.inc
ck_sstl_18.inc
dq/dm
dqs
addcmd, ctrl
ctrl
ck
Table 65: Waveform Processing Files
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4.9 Replacing the DDR2 Controller Models
To replace the DDR2 controller IBIS and timing models perform the following steps:
1. Change the pin names on every controller designator in every transfer net.
2. Update controller transfer model overrides on every transfer net.
3. Change the pin names in the timing groups in the ddr2 controller timing model to
match the new IBIS component pin names.
Note: These changes span many Schematic Sets and transfer nets as shown in Table 5
and Table . Performing this task manually is time intensive and error prone, therefore, it
is not recommended that you manually perform this operation SiSoft will work directly
with its customers to perform custom modifications, if required.
Note: If you need a custom kit, please contact support@sisoft.com.
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