Module No 3
Lecture No 15
Electrical Characteristics and Bus-Cycle
Objective:
- To examine the electrical-characteristics of the 8088 processor
- To introduce the 8284 clock generator.
- To define the Bus-cycle and Time-states associated with 8086 and
8088 microprocessor.
Slide 1: Electrical characteristics of 8086/8088 processors:
- In the 8086/8088 processors, the power is applied between pin 40
(VCC) and pins 1 (GND) or 2 (GND).
- At room temperature (25°C), the value of VCC is specified to be
+5V DC with a tolerance of ±10% and the maximum current
drawn by the processor is 340 mA.
- The minimum (during stand-by mode) and maximum power
dissipated by 8086/8088 processors are 0.0025 watt and 1.28
watt respectively.
- The operating temperature for 8088/8086 ranges from 0 - 80°
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Slide 2: The electrical characteristics (cont’d):
- The accepted range of voltage levels for logic-high and logic-low
Input and Output signals of 80x86 processors are tabulated below:
Test
Condition
Symbol
Meaning
Minimum
Maximum
VIL
Input low voltage
- 0.5 V
+ 0.8 V
VIH
Input high voltage
+ 2.0 V
VCC+ 0.5 V
VOL
Output low voltage
0v
+ 0.45 V
IOL = 2.0 mA
VOH
Output high voltage
+ 2.4 V
VCC
IOH = - 400 µA
Slide 3: The System Clock of 8086/8088 processors:
- The time base for synchronization of the internal and external
operations of the microprocessors in a microcomputer system is
provided by the clock (CLK) input signal
- The clock speed supported by the 80X86 family are:
o Standard 8086 operate at 5 MHz clock speed, whereas
8086-2 and 8086-1 processors operate at 8-MHz and 10
MHz clock speed, respectively.
o Standard 8088 operate at 5 MHz, whereas 8088-2
processor operates at 8 MHz clock speed.
- The CLK signal is externally generate by 8284 clock generator and
driver IC and feed into the processor using Pin number 19.
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Slide 4: The System Clock (Cont’d):
- The connection between the 8284 clock generator and 8088/8086
microprocessor is shown in figure below.
- Note that 8284 outputs the crystal frequency as oscillator (OSC)
frequency, one third of crystal frequency as clock (CLK) frequency
and half of clock frequency as peripheral (PCLK) clock frequency.
Pin 17
XTAL of
15-24 MHz
Pin 18
X1
OSC
8088
Pin 12
8284
Microprocessor
Clock generator
Pin 8
X2
CLK
F/C
PCLK
Pin 19
CLK
CL
Pin 19
The value of
CL is typically
12 pF when
used with 15
MHz crystal
This input allows
the IC to be
driven by an
external clock
instead of the
crystal (XTAL)
The TTL compatible
peripheral clock
frequency is 2.5-MHz,
which are half the
CLK frequency
The fundamental crystal
frequency is divided by 3
with in the 8284 to give
5-MHz MOS compatible
clock signal.
Thus, if a 8284 clock generator IC is supported by a 15 MHz crystal
oscillator and connected via a 12 pF capacitor, it outputs three
frequencies, such as, Oscillator frequency of 15 MHz, clock
frequency of 5 MHz and peripheral clock frequency of 2.5 MHz.
Slide 5: Voltage levels and Waveforms of a System clock:
- For 8284 clock, the logic Low ranges from -0.5v < VLow < 0.6v
and logic High voltage ranges from (VCC + 1) < VHigh < 3.9v
- The typical waveforms generate by the 8284 IC are as follows:
OSC frequency:
(15 MHz)
CLK frequency:
(5 MHz)
PCLK frequency:
(2.5 MHz)
The output at PCLK is half the CLK frequency and CLK is one third of
the OSC or crystal frequency.
- Note that the period of 5MHz clock input of the processor can range
from 200 ns to 500 ns with maximum rise and fall times of 10 ns
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Slide 6: Example 1:
Question 1: If the CLK input of an MPU is to be driven by a 8-MHz
signal, what speed version of the 8088 must be used and
what frequency crystal must be attached to the 8284.
Solution 1: Since the 8088-2 processor operated at 8-MHz, it seems
to be the best choice. Also the CLK frequency is 1/3 of the
OSC frequency, so a 8284 clock generator IC with 24-MHz
crystal is required.
Question 2: Find the period of the signal for an 8-MHz 8088 system.
Solution 1: As T=1/f, the period (T) of this system is: 125 ns
Resources: http://www.cpu-world.com/CPUs/8086/MANUF-Intel.html
Slide 7: Bus-Cycle and Time States of 8086/8088 processor:
- A bus-cycle defines the basic operation process of a
microprocessor to communicate with external devices.
Such as, memory read bus-cycle, where data stored in main
memory is read into the internal registers of the CPU (such as AX).
- Typically, the bus-cycle of the 8086 and 8088 processors consist of
four clock cycles or pulses. Thus, duration of a bus-cycle is = ‘4*T’
- A bus-cycle involving a data transfer operation between the CPU
and external storage device (memory) is shown in the figure below.
Bus Cycle
(4-clock pulses)
Data transfer
process of CPU
(Read/write)
T1
Address
T2
Buffer
T4
T3
Data
- Note that during time state ‘T1’, the MPU puts the address on the
system-bus and writes or reads data during time states ‘T3’ and ‘T4’.
More detail discussion on this data read/write bus cycle will be
presented later.
Slide 8: Bus Cycle and Time States (cont’d) :
- During the absence of bus activity or bus-cycles, the processor
performs what are known as “ideal-states”.
- Each ideal-state is one CLK period long and any number of them
can be inserted between bus-cycles, as shown in figure below.
Ideal clock
Cycles
1st Bus
Cycle
ideal click cycle
2nd Bus
Cycle
- Typically, ideal-states are performed when the instruction queue
inside the microprocessor becomes full and their execution does not
involve any memory or input/output operands.
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Slide 9: Bus Cycle and Time States (cont’d) :
- Often the microprocessor requires interfacing with slower memory
and input/output devices and needs to prolong its bus-cycle.
- This is achieved by inserting “wait-states” between the time states
‘T3’ and ‘T4’, as long as the slower external device keep supplying
logic “0” to the “Ready” pin of 8088/8086 CPU.
Extended Bus
Cycle by inserting
Wait-states
READY pin input
of CPU, provided
by external device
Extended data
read/write time
due to wait-states
T1
T2
T3
TW
Input of CPU “Ready” pin = ‘0’
Ready=‘1’
Address
Buffer
Data
T4
Slide 10: Example 2:
Question: What is the duration of the bus-cycle in a 8088 based
microcomputer, if the clock frequency is 12 MHz and the
three wait states are inserted?
Solution: The period of a 12 MHz microprocessor is, T = 1/f = 83 ns.
Thus, the duration of the bus-cycle, without any wait-states
is given by; tbus-cycle = 4* Period = 4 * 83 ns = 333 ns.
Duration of the wait-states is, twait-states = 3* Period = 249 ns.
So, extended bus-cycle, t(bus-cycle with wait-states) = 538 ns.
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Slide 11: Example 3:
Question: The execution of instructions “label:DEC CX” and “JNZ
label” requires 2 and 16 clock-cycles, respectively. Find
the time period required for executing the instruction
“label:LOOP label” by a 4-MHz microprocessor.
Solution: For a 4-MHz microprocessor, the period, T= 250 ns.
If we assume CX=’N’, the time duration for the ‘LOOP’
instruction to be executed for ‘N’ times are given by;
(total clock cycle) x (N) x(period) = 18 x N x 250 ns