4 — Clock Generator 8284A
Objectives
1. Discuss the pin configurations and operations of the 8284A clock generator.
2. Start the first phase of designing a single-board 8086-based microcomputer system.
This phase involves making the basic connections of the 8086 microprocessor in minimum mode and interfacing the 8284A clock generator.
4.1 Background
The 8284A is an integrated circuit designed specifically for use with the 8086/8088 microprocessors. This circuit provides the following basic functions or signals : clock generation,
RESET synchronization, and READY synchronization.
4.1.1 Pin Configuration of the 8284A Clock Generator
Figure 4.1 illustrates the pin-out of the 8284A clock generator. The functions of these pins
are briefly discussed in next paragraphs (refer to the 8284A data sheet for more details).
AEN1 and AEN2
Address Enable (AEN ) is an active LOW signal serves to qualify its respective bus Ready
Signal (RDY 1 or RDY 2). AEN 1 validates RDY 1 while AEN 2 validates RDY 2. The two
AEN signal inputs are useful in system configurations which permit the processor to access
two multi-master system busses. In non-multi-master configurations, the AEN signal inputs
are tied true (LOW).
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Clock Generator 8284A
CYNC
1
18
VCC
AEN1
3
16
X2
PCLK
RDY1
READY
RDY2
AEN2
CLK
GND
2
4
5
6
7
8
9
17
8284A
15
14
13
12
11
10
X1
ASYNC
EFI
F/C
OSC
RES
RESET
Figure 4.1 – 8284A pin diagram.
RDY1 and RDY2
Bus Ready (Transfer Complete) RDY is an active HIGH signal which is an indication from
a device located on the system data bus that data has been received, or is available RDY 1
is qualified by AEN 1 while RDY 2 is qualified by AEN 2.
ASYNC
Ready Synchronization Select (ASY N C) is an active LOW input which defines the synchronization mode of the READY logic. When ASY N C is LOW, two stages of READY synchronization are provided. When ASY N C is left open or HIGH, a single stage of READY
synchronization is provided.
READY
READY is an active HIGH output signal which is the synchronized RDY signal input.
READY is cleared after the guaranteed hold time to the processor has been met.
X1 and X2
Crystal Inputs (X1 and X2) are the pins to which a crystal is attached. The crystal frequency
is 3 times the desired processor clock frequency. Note that if the crystal inputs are not used
X1 must be tied to V CC or GN D and X2 should be left open.
F/C
Frequency/Crystal Select (F/C) is an input used as a strapping option. When strapped
LOW, F/C permits the processor’s clock to be generated by the crystal. When F/C is
strapped HIGH, CLK is generated for the EF I input.
EFI
External Frequency Input (EF I) is strapped HIGH, CLK is generated from the input
frequency appearing on this pin. The input signal is a square wave 3 times the frequency
of the desired CLK output.Frequency/Crystal Select (F/C) is an input used as a strapping
option. When strapped LOW, F/C permits the processor’s clock to be generated by the
crystal. When F/C is strapped HIGH, CLK is generated for the EF I input.
4.1 Background
31
CLK
Processor Clock (CLK) is the clock output used by the processor and all devices which
directly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of
the crystal or EF I input frequency and a 1/3 duty cycle.
PCLK
Peripheral Clock (P CLK) is a peripheral clock signal whose output frequency is 1/2 that
of CLK and has a 50% duty cycle.
OSC
Oscilloscope Clock (OSC) is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal.
RES
Reset Input (RES) is an active LOW input signal which is used to generate RESET . The
82C84A provides a schmitt trigger input so that an RC connection can be used to establish
the power-up reset of proper duration.
RESET
RESET is an active HIGH output signal which is used to reset the 80x86 family processors.
Its timing characteristics are determined by RES.
CSYNC
Clock Synchronization (CSY N C) is an active HIGH input signal which allows multiple
8284A chips to be synchronized to provide clocks that are in phase. When CSY N C is
HIGH the internal counters are reset. When CSY N C goes LOW the internal counters are
allowed to resume counting. CSY N C needs to be externally synchronized to EF I. When
using the internal oscillator CSY N C should be hardwired to ground.
VCC and GND
Power (VCC) and Ground (GND) input pins. A 0.1μF capacitor between V CC and GN D
is recommended for decoupling.
4.1.2 Operations of the 8284A Clock Generator
The 8284A clock generator has three main functions : (1) clock generator, (2) RESET logic,
and (3) READY synchronization.
Clock Generator
The 8284A can derive its basic operating frequency from one of two sources : (1) an external
frequency source connected to the EF I pin, and (2) a quartz crystal connected to X1 and
X2. The control input F/C is used to select one of these sources. The crystal frequency
should be selected at three times the required CPU clock. The 8284A generates three clock
signals : OSC, CLK and P CLK. The OSC has the same frequency as the crystal (or the
external frequency) and can be used to test the clock generator or as and external frequency
32
Clock Generator 8284A
input to other 8284A chips. The CLK is 1/3 the frequency of the crystal (or the external
frequency) with a 33% duty cycle designed to drive the 8086 processor directly. The P CLK
is a peripheral clock signal whose output frequency is 1/2 that of the CLK with 50% duty
cycle.
RESET Logic
The 8284A generates an active HIGH signal (RESET ) which is used to reset the 8086
microprocessor. This signal must be held high for at least 50μs in order to guarantee a
correct reset of the microprocessor. This requirement can be achieved using a simple RC
circuit as will be explained later in this experiment.
READY Synchronization
The READY signal is used by slow devices (memory or I/O peripherals) to request the
processor to extend the bus cycle to allow these device to finish reading/writing from/to
the bus. The 8284A generates a READY signal that is synchronized with the CPU clock.
For this project, READY synchronization is not required.
4.2 Required Components
1. Clock Generator (8284A)
2. Dummy Crystal (Crystal)
3. Resistor 510Ω (MINRES510R)
4. Resistor 10KΩ (MINRES10K)
5. SPST Push Button (BUTTON)
6. Capacitor Primitive (CAPACITOR)
7. Silicon Rectifier, MRPRV 50V , MAFRC 1.0A (1N4001)
4.3 Schematic Entry
In this section, we will start building the first phase of our 8086-based microcomputer
system. This phase involves two main tasks : (1) connect the 8284A to generate the required
clock signal and reset logic for the 8086 microprocessor, and (2) make the basic connections
of the 8086 microprocessor necessary to run the 8086 in minimum mode. The first task
will be accomplished in this experiment, while the second part will be deviated to the next
experiment. The procedure to build the 8284A interface circuit is summarized below :
1. Open the 8284A project file provided by your instructor and save it with a new name
of your choice (say "8284A_Clock_Generator.pdsprj").
2. Get the required circuit components from the Library.
3. Interface the crystal circuit to the 8284A (Section 4.3.1).
4. Interface the reset circuit to the 8284A (Section 4.3.2).
5. Add clock and reset terminals (Section 4.3.3).
(a)
i. text
4.3 Schematic Entry
33
4.3.1 Interfacing the Crystal Circuit to the 8284A
Place the following components on to the Editing Window :
— 8284A (clock generator)
— Crystal (dummy crystal)
— MINRES510R (two 510Ω resistors)
Connect the components as shown in Figure 4.2 and set the frequency of the crystal to
15KHz. Note that this frequency is just for simulation purposes (in real implementation a
crystal of 15M Hz is used).
Figure 4.2 – Crystal interface to the 8284A clock generator.
4.3.2 Interfacing the Reset Circuit to the 8284A
On the same design sheet place the following components and connect them as shown in
Figure 4.3 :
— BUTTON (SPST Push Button)
— RESISTOR (Analog resistor primitive)
— CAPACITOR (Capacitor primitive)
— 1N4001 (Silicon Rectifier, Maximum Recurrent Peak Reverse Voltage 50V , Maximum
Average Forward Rectifier Current 1.0A)
Edit the properties of the capacitor and change the capacitance value to 10μF and the
initial conditions to IC = 0V as shown in Figure 4.4. Similarly, edit the properties of the
resistor and change the resistance value to 10KΩ.
4.3.3 Clock and Reset Terminals
The final step in schematic entry of the 8284A is to add two terminals to the schematic :
CLK and RESET as shown in Figure 4.5. The purpose of these terminals is allow the clock
signal and reset logic to be connected to the 8086 design sheet which will be added to our
project in the next LAB experiment.
34
Clock Generator 8284A
Figure 4.3 – Reset circuit of the 8284A clock generator.
Figure 4.4 – Setting properties of the capacitance in the reset circuit.
Figure 4.5 – Adding CLK and RESET terminals to the 8284A schematic.
4.4 Testing the Design
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4.4 Testing the Design
To test your design, follow the procedure summarized below :
1. Run the simulation and determine the frequency and duty cycle of the three clock
outputs : OSC, CLK and P CLK.
2. Calculate the minimum reset time mathematically (Section 4.4.1).
3. Measure the minimum reset time using analog analysis (Section 4.4.2).
4.4.1 Calculating the Minimum Reset Time Mathematically
As indicated before, the RESET signal must be held high for at least 50μs in order to
guarantee a correct reset of the microprocessor. Equivalently, we should make sure that the
the time required for the RES signal to go from logic 0 to logic 1 on power-on (or after
pushing the reset button) is at least 50μs. This requirement can be achieved by using the
reset circuit discussed above with properly selected values for the resistor and capacitor.
The reset time is determined by the capacitor charging timing which can be calculated using
the following RC charging formula :
Vc = Vs (1 − exp−t/RC )
(4.1)
Where,
— Vc is the voltage across the capacitor,
— Vs is the supply voltage,
— t is the elapsed time since the application Vs, and
— RC is the time constant of the RC charging circuit .
Exercise 4.1 Using the RC charging formula, calculate the duration of the reset signal assuming that
the minimum high voltage of the 8284A is 2.5V (i.e. Vc = 2.5V ) .
4.4.2 Measuring the Minimum Reset Time Using Analog Analysis
In this part of the experiment, we will measure the minimum reset time (i.e. the charging
time of the capacitor) using analog analysis.
Choose the Graph Mode and then select ANALOG analysis from the list box and place
it on the Editing Window as shown in Figure 4.6.
Choose the Voltage Probe Mode and then select ANALOG probe from the list box and
connect it to the output of the reset circuit as shown in Figure 4.7. Note that in order to
perform the analog analysis, you need to disconnect the line from the RES of the 8284A.
Double click the title-bar of the Analog Analysis Window to open the Prospice Window
as shown in Figure 4.8. Click on the "Add Trace" button and then select the voltage probe
signal Vc as illustrated in the figure.
Click on the "Edit Graph" button to open the Edit Transient Graph Window as shown
in Figure 4.9. Modify "stop time" to 200ms and uncheck the "initial DC solution" box as
illustrated in the figure.
36
Clock Generator 8284A
Figure 4.6 – Inserting an analog analysis window.
Figure 4.7 – Inserting analog voltage probe.
Figure 4.8 – Inserting a trace signal into Prospice window.
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4.4 Testing the Design
Figure 4.9 – Edit transient graph.
To complete the analog analysis click on the "Simulate Graph" button as shown in
Figure 4.10. The analog analysis simulation shows that the capacitor charge will reach 2.5V
after 69.5ms as illustrated in the figure.
Exercise 4.2 Compare the minimum reset time calculated in Exercise 4.1 with the minimum reset time
measured using analog analysis.
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Clock Generator 8284A
Figure 4.10 – Analog analysis simulation.